Title:

Design of Computer Systems

Code:INP
Ac.Year:2017/2018
Term:Winter
Curriculums:
ProgrammeBranchYearDuty
IT-BC-3BIT2ndCompulsory
Language:Czech
Private info:http://www.fit.vutbr.cz/study/courses/INP/private/
Credits:6
Completion:accreditation+exam (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:39120014
 ExaminationTestsExercisesLaboratoriesOther
Points:52150033
Guarantee:Sekanina Lukáš, prof. Ing., Ph.D., DCSY
Lecturer:Bidlo Michal, Ing., Ph.D., DCSY
Sekanina Lukáš, prof. Ing., Ph.D., DCSY
Vašíček Zdeněk, doc. Ing., Ph.D., DCSY
Instructor:Bidlo Michal, Ing., Ph.D., DCSY
Vašíček Zdeněk, doc. Ing., Ph.D., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Prerequisites: 
Digital Systems Design (INC), DCSY
Machine Level Programming (ISU), DITS
Follow-ups:
Computer Communications and Networks (IPK), DIFS
Schedule:
DayLessonWeekRoomStartEndLect.Gr.St.G.EndG.
MonexerciselecturesD10512:0012:502BIA
MonexerciselecturesD10512:0012:502BIB
MonexerciselecturesD10512:0012:503BIT
MonlecturelecturesD10513:0015:502BIA
MonlecturelecturesD10513:0015:503BITxxxx
Monexam - 1. oprava2018-01-15D10513:0014:502BIA
Monexam - 1. oprava2018-01-15D10513:0014:502BIB
Monexam - 1. oprava2018-01-15D10513:0014:503BIT
Monexam - 1. oprava2018-01-15D020613:0014:502BIA
Monexam - 1. oprava2018-01-15D020613:0014:502BIB
Monexam - 1. oprava2018-01-15D020713:0014:502BIA
Monexam - 1. oprava2018-01-15D020713:0014:502BIB
TueexerciselecturesD10513:0013:502BIA
TueexerciselecturesD10513:0013:502BIB
TueexerciselecturesD10513:0013:503BIT
WedlecturelecturesE11208:0010:502BIB
WedlecturelecturesE10408:0010:502BIB
WedlecturelecturesE10508:0010:502BIB
WedlecturelecturesE11208:0010:503BITxxxx
Wedexam - řádná2018-01-03D10510:0011:502BIA
Wedexam - řádná2018-01-03D10510:0011:502BIB
Wedexam - řádná2018-01-03D10510:0011:503BIT
Wedexam - řádná2018-01-03D020610:0011:502BIA
Wedexam - řádná2018-01-03D020610:0011:502BIB
Wedexam - řádná2018-01-03D020710:0011:502BIA
Wedexam - řádná2018-01-03D020710:0011:502BIB
Wedexam - řádná2018-01-03E11210:0011:502BIA
Wedexam - řádná2018-01-03E11210:0011:502BIB
Wedexam - řádná2018-01-03E10410:0011:502BIA
Wedexam - řádná2018-01-03E10510:0011:502BIB
Wedexam - řádná2018-01-03G20210:0011:502BIA
Wedexam - řádná2018-01-03A11210:0011:502BIB
Thuexam - 2. oprava2018-01-25D10509:0010:502BIA
Thuexam - 2. oprava2018-01-25D10509:0010:502BIB
Thuexam - 2. oprava2018-01-25D10509:0010:503BIT
 
Learning objectives:
  To give the students knowledge of organization and functioning of a (single core) processor, in particular, the operation, memory and control units, the algorithms with fixed and floating point operations, the way of controlling them, the subsystem communication level, and integration of the processor to a parallel system.
Description:
  Principles of a processor. Introduction to VHDL. Von Neumann computer. Data types, formats and coding. Instructions, formats, coding and addressing, instruction set architecture. VHDL models of algorithms and subsystems. Pipelining. Arithmetic and logic operations. Algorithms and function units. Sequencer: basic function, hard-wired and microprogram implementation. Memories: types, organization, controlling. Memory hierarchy, cache memory. Peripheral units, buses and bus control. Performance evaluation. Reliability of computer systems. Introduction to parallel architectures.
Knowledge and skills required for the course:
  Understanding of development trends and possibilities of computer technology.
Learning outcomes and competences:
  Students are able to describe functionality of the operation, memory and control units and their communication in a computer. They are familiar with VHDL.
Syllabus of lectures:
 
  • Introduction, processor and its function.
  • Data representation.
  • Instruction sets, register structures.
  • Modelling in VHDL.
  • Pipeline processing.
  • Algorithms of fixed point operations.
  • Algorithms of floating point operations, iterative algorithms.
  • Controllers.
  • Memories, cache memory.
  • Buses, peripheral interfacing and control.
  • Computer performance and performance evaluation.
  • Reliability of computer systems.
  • Introduction to parallel architectures.
Syllabus of numerical exercises:
 
  • VHDL - introduction
  • VHDL - synthesizable code
  • Introduction to FITkit
  • Processor in VHDL
  • Huffman code, Hamming code
  • Modular arithmetic, adders
  • Multipliers
  • Division
  • Iterative algorithms
  • Performance evaluation, reliability
  • Parallel architectures
Syllabus - others, projects and individual work of students:
 
  • Two projects will be assigned during the semester.
Fundamental literature:
 
  • Hennessy, J. L., Patterson, D. A.: Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann Publ., 1996
  • Hamacher, C., Vranesic, Z., Zaky, S.: Computer Organization, 5th edition, McGraw Hill, 2002
Study literature:
 
  • Drábek, V: Computer organization. Lecture notes of Brno University of Technology, PC-DIR publ., Brno, 1995
  • Pinker, J., Poupa, M.: Číslicové systémy a jazyk VHDL, BEN - technická literatura, Praha, 2006
  • Dvořák, V.: Architektura a programování paralelních systémů. Skriptum FIT VUT v Brně, 2004, 170 s., ISBN 80-214-2608-X
  • Soubor materiálů prezentovaných na přednáškách dostupný na internetových stránkách kurzu.
Controlled instruction:
  Within this course, attendance on the lectures and demonstrations is not monitored. The knowledge of students is examined by the projects, the mid-term exam and by the final exam. The minimal number of points which can be obtained from the final exam is 20. Otherwise, no points will be assigned to a student.
Progress assessment:
  Written final exam, mid-term exam and submitting projects in due dates.
Exam prerequisites:
  For receiving the credit and thus for entering the exam, students have to get at least 20 points during the semester.

Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.