Title:  Digital Systems Design 

Code:  INCe 

Ac.Year:  2017/2018 

Term:  Winter 

Curriculums:  

Language:  English 

News:  * This course is prepared for incoming Erasmus+ students only, and it is instructed in English. * This course will be open if a certain/sure minimum of enrolled students is at least five students. * The first meeting will be in L314 at Wed0920 in 800 h. * Stop and Check Test will take place at Wed 20171025, 900 h a.m., in seminar room L314 during the 1st hour of lecture.. * MidTerm Test will take place at Wed 20171025, 900 h a.m., in seminar room L314 during the 1st hour of lecture.


Credits:  5 

Completion:  examination (written) 

Type of instruction:  Hour/sem  Lectures  Sem. Exercises  Lab. exercises  Comp. exercises  Other 

Hours:  39  13  0  0  0 

 Examination  Tests  Exercises  Laboratories  Other 

Points:  60  40  0  0  0 



Guarantee:  Eysselt Miloš, Ing., CSc., DCSY 

Lecturer:  Eysselt Miloš, Ing., CSc., DCSY 
Instructor:  Eysselt Miloš, Ing., CSc., DCSY 

Faculty:  Faculty of Information Technology BUT 

Department:  Department of Computer Systems FIT BUT 

Followups:  

Schedule:  Day  Lesson  Week  Room  Start  End  Lect.Gr.  St.G.  EndG. 

Wed  lecture  lectures  L314  09:00  11:50  INTE   


 Learning objectives: 

  To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. To learn about design of digital circuits consisting of combinational and sequential logic devices.  Description: 

  Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: logic expressions, reduction methods, design of combinational logic networks. Analysis of logic networks behaviour: signal races, hazards. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Sequential logic networks, latches and flipflops. State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital equipment: design CAD tools, description tools, design strategy. Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: gate arrays, PROM, PLA, PAL. Simple asynchronous networks: design, analysis of behaviour, hazards.  Knowledge and skills required for the course: 

  The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.  Learning outcomes and competences: 

  A practical use of selected methods for specification of combinational and sequential logic networks. An encompassment of analysis and design of simple combinational and sequential networks. An encompassment of analysis and design of simple digital equipments using combinational and sequential circuits and blocks.  Syllabus of lectures: 


 Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
 Boolean algebra, logic functions and their representations, logic expressions.
 Reduction methods: QiuneMcCluskey tabular method, Petrick's cover function.
 Reduction methods: Karnaugh maps, logic and functional diagrams.
 Analysis of logic networks behaviour: signal races, hazards.
 Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit.
 Sequential logic networks, latches and flipflops.
 State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider.
 Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: gate arrays, PROM, PLA, PAL.
 Simple asynchronous networks: design, analysis of behaviour, hazards.
 Syllabus of numerical exercises: 


 Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
 Boolean algebra, logic functions and their representations, a behaviour analysis of contactswitch networks.
 Logic expressions. QiuneMcCluskey tabular reduction method, Petrick's cover function.
 Reduction methods: Karnaugh maps, logic and functional diagrams.
 Logic functions implementation using SSI i.cs. Behaviour analysis of logic networks: signal races, hazards.
 Selected logic modules: adders, subtractor.
 State machines and their representations. Design of synchronized sequential networks.
 Design of logic networks based on MSI and LSI i.cs. Programmable logic devices: gate arrays, PROM, PLA, PAL.
 Fundamental literature: 


 McCluskey, E.J.: LOGIC DESIGN PRICIPLES. PrenticeHall, USA, ISBN 0135397685, 1986.
 Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0314478280, 1990.
 Bolton, M.: Digital Systems Design with Programmable Logic. AddisonWesley Publishing Company, Cornwall, GB, ISBN 0201145456, 1990.
 Katz, R.H.: Contemporary Logic Design. AddisonWesley/BenjaminCummings Publishing CO, Redwood City, CA, USA, ISBN 0805327037, 1993.
 Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0792384563, 1999.
 Study literature: 


 Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
 Bolton, M.: Digital Systems Design with Programmable Logic. AddisonWesley Publishing Company, Cornwall, GB, ISBN 0201145456, 1990.
 McCluskey, E.J.: LOGIC DESIGN PRICIPLES. PrenticeHall, USA, ISBN 0135397685, 1986.
 Cheung, J.Y.  Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0314478280, 1990.
 Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0792384563, 1999.
 Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I. University of Alberta, Edmonton, CA, 2003.
 Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II. University of Alberta, Edmonton, CA, 2003.
 Eysselt, M.: Digital Systems Design: Basic Set of Problems 1 (SSI Circuits Networks). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Basic Set of Problems 2 (MSI Circuits Networks). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Binary Logic Elements (Grafic Symbols for Diagrams). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Laboratory (TTL Family Circuits and Functional Diagrams). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Slides 2003 (Set of Basic Slides). StudentText of the FIT, Brno UT, 2003.
 Eysselt, M.: Digital Systems Design: Programmable Logic Devices (Foundations & Examples). StudentText of the FIT Brno UT, FIT Brno UT, 2003 (WWW version).
 Controlled instruction: 

  Test, midterm exam and final exam are the monitored, and points earning, education. Test and midterm exam are without correction eventuality. Final exam has two additional correction eventualities.  Progress assessment: 

 
 Stop and Check Test: 20 points.
 MidSemester Exam: 20 points.
 Final Exam: 60 points.
Passing bounary for ECTS assessment: 50 points.  Exam prerequisites: 

  Requirements for class accreditation are not defined.  
