Title:

VHDL Seminar

Code:IVH
Ac.Year:2018/2019
Sem:Summer
Curriculums:
ProgrammeField/
Specialization
YearDuty
IT-BC-3BIT1stCompulsory-Elective - group T
IT-BC-3BIT2ndCompulsory-Elective - group T
Language of Instruction:Czech
Private info:http://www.fit.vutbr.cz/study/courses/IVH/private/
Credits:4
Completion:credit
Type of
instruction:
Hour/semLecturesSeminar
Exercises
Laboratory
Exercises
Computer
Exercises
Other
Hours:0260013
 ExamsTestsExercisesLaboratoriesOther
Points:0000100
Guarantor:Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Deputy guarantor:Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Lecturer:Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Instructor:Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Follow-ups:
Design of Computer Systems (INP), DCSY
Digital Systems Design (INC), DCSY
Schedule:
DayLessonWeekRoomStartEndLect.Gr.Groups
WedlecturelecturesD0207 12:0013:501BIA 1BIB 2BIA 2BIB 3BIT xx
Wedcomp.lab - nepravidelně dle potřebylecturesN205 12:0013:50
 
Learning objectives:
  To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.
Description:
  Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
Knowledge and skills required for the course:
  Basic skills in programming and digital design, fundamentals of Boolean algebra.
Learning outcomes and competencies:
  The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioral and structural description. This course is recommend as a co-requisite for INC and INP.
Why is the course taught:
  The VHDL Seminar supports INC and INP courses and is recommended to deepen the knowledge of VHDL language and issues connected with advanced hardware design. Students will receive a more detailed knowledge of VHDL not only theoretically but also practically as there are not only practical demonstrations but also a project on FITkit, development board equipped with programmable gate array XILINX. Mastering the hardware description language is a key element in the successful and efficient design of FPGA-based systems having a dominant position especially in the field of high-performance computing (network operations acceleration, acceleration of digital signal and video processing, acceleration of bioinformatic tasks, cryptographic applications, etc.), where the acceleration platforms based on FPGAs can achieve significant speedup gain at minimum power levels compared to the conventional parallelization techniques based on CPUs and GPUs. Knowledge of hardware description techniques enables students to actively engage in a number of research projects in the area of network data and security processing.
Syllabus of lectures:
 
  1. Moderní návrh hardware (design flow), jazyky pro popis hardware (VHDL, Verilog), FPGA, úvod do číslicových systémů.
  2. Základní konstrukce jazyka VHDL, lexikální popis, zdrojový text ve VHDL.
  3. Datové typy, datové objekty, třídy objektů, deklarace datových objektů.
  4. Příkazy jazyka VHDL
  5. Pokročilé vlastnosti jazyka VHDL, zpoždění a plánování času.
  6. Popis kombinačních obvodů, třístavové obvody.
  7. Popis synchronních sekvenčních obvodů, popis konečných automatů, asynchronní sekvenční obvody.
  8. Modelování obvodů a událostně řízená simulace, testování obvodů a návrh testů, funkční simulace (ModelSIM), co-simulace.
  9. Syntéza obvodů, omezení (constraints), syntéza pro FPGA, časová simulace.
  10. Pokročilé techniky (pipelining, retiming, sdílení komponent, flattening a strukturování)
  11. Příkladová studie komplexních obvodů: řízení maticového LED displeje, UART, ETHERNET
  12. Příkladová studie komplexních obvodů: RISC procesor
  13. Obvody FPGA, využití masivního paralelismu v kryptografii (RC4, DES), DNA-alignment
Syllabus - others, projects and individual work of students:
 Individual project dividend into several parts.
Fundamental literature:
 
  • Jasinski, R.: Effective Coding with VHDL: Principles and Best Practice. The MIT Press. 2016.
  • Pedroni, V. A.: Circuit Design and Simulation with VHDL (Second Edition). The MIT Press. 2011
  • Armstrong, J.R. - Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
  • Chang, K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997
  • Armstrong, J.R. - Gray F.G.: Structured Logic Design with VHDL, Prentice-Hall, 1993
Study literature:
 
Progress assessment:
  Project supported by the written technical report in English language.
Exam prerequisites:
  Class credit is gained when minimal total score of 50% points is gained during a semester.
 

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