Title:

Advanced Digital Systems

Code:PCS
Ac.Year:2018/2019
Term:Winter
Curriculums:
ProgrammeFieldYearDuty
IT-MSC-2MBI-Compulsory-Elective - group C
IT-MSC-2MBS-Elective
IT-MSC-2MGM-Compulsory-Elective - group C
IT-MSC-2MIN-Elective
IT-MSC-2MIS-Elective
IT-MSC-2MMM-Elective
IT-MSC-2MPV2ndCompulsory
IT-MSC-2MSK-Elective
Language of Instruction:Czech
Credits:5
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSeminar
Exercises
Laboratory
Exercises
Computer
Exercises
Other
Hours:26001016
 ExamsTestsExercisesLaboratoriesOther
Points:601801012
Guarantor:Fučík Otto, doc. Dr. Ing. (DCSY)
Lecturer:Kořenek Jan, Ing., Ph.D. (DCSY)
Martínek Tomáš, Ing., Ph.D. (DCSY)
Matoušek Jiří, Ing. (DCSY)
Instructor:Dvořák Milan, Ing. (DCSY)
Kajan Michal, Ing. (DCSY)
Matoušek Denis, Ing. (DCSY)
Matoušek Jiří, Ing. (DCSY)
Zachariášová Marcela, Ing., Ph.D. (DCSY)
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Schedule:
DayLessonWeekRoomStartEndLect.Gr.St.G.EndG.
ThulecturelecturesD020714:0015:501MITxxxx
ThulecturelecturesD020714:0015:502MIT17 MPV17 MPV
 
Learning objectives:
  To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.
Description:
  Combinatorial and sequential logic design techniques, algorithms, and tools review. Review of digital design target technologies (ASIC, FPGA). Algorithms for minimization of digital circuits. Advanced synthesis techniques (pipelining, retiming). Constraint conditions. Modern approaches to synthesis of digital circuits (models, methods, logic optimization, optimization for target technology). Synergy of modern syntehesis and verification. Low power design methodologies. Reconfigurable computing. Verification of digital circuits (OVM methodology).
Knowledge and skills required for the course:
  Digital system design, basic programming skills.
Learning outcomes and competences:
  The students are able to design complex constrained digital systems using contemporary design techniques and they know modern methods for synthesis and verification of these systems.
Syllabus of lectures:
 
  • Combinatorial and sequential logic design techniques, algorithms, and tools review.
  • Review of digital design target technologies (ASIC, FPGA).
  • Algorithms for minimization of digital circuits.
  • Advanced synthesis techniques (pipelining, retiming).
  • Constraint conditions.
  • Models and methods for modern synthesis of digital circuits (AIG, BDD, SAT solvers).
  • Modern synthesis of digital circuits (logic optimization).
  • Modern synthesis of digital circuits (optimization for target technology).
  • Synergy between synthesis and verification of digital circuits.
  • Low power design methodologies.
  • Reconfigurable computing.
  • Verification of digital circuits (OVM methodology).
Syllabus of computer exercises:
 
  • Synthesis of the basic logic circuits, pipelining, retiming.
  • Constraint conditions.
  • Synthesis of basic digital circuits using ABC tool.
  • Synthesis of advanced digital circuits using ABC tool.
  • Verification of digital circuits.
Syllabus - others, projects and individual work of students:
 
  • Individual project focused on digital design using CatapultC environment.
Fundamental literature:
 
  • Gajsky D., Dutt N., Wu A., Lin S.: High-Level Synthesis: Introduction to Chip and System Design, ISBN 079239194-2, 1992
  • Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008
  • Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996
Study literature:
 
  • Lecture notes in e-format
Controlled instruction:
  Presence in any form of instruction is not compulsory. An absence (and hence loss of points) can be compensated in the following ways: 
  1. presence in another laboratory group dealing with the same task. 
  2. showing a summary of results to the tutor at the next lab. 
  3. sending a short report (summarizing the results of the missed lab and answering the questions from the assignment) to the tutor, in 14 days after the missed lab.
Progress assessment:
  Written mid-term exam and project in due dates.
Exam prerequisites:
  Requirements for class accreditation are not defined.
 

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