Title:

VHDL Seminar (in the EU)

Code:IVH
Ac.Year:2003/2004
Term:Summer
Study plans:
ProgramBranchYearDuty
IT-BC-3BIT2ndCompulsory-Elective - group T
Language:English
Private info:http://www.fit.vutbr.cz/study/courses/IVH/private/
Credits:6
Completion:classified accreditation
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:0260013
 ExaminationTestsExercisesLaboratoriesOther
Points:00000
Guarantee:Fučík Otto, doc. Dr. Ing., DCSY
Lecturer:Fučík Otto, doc. Dr. Ing., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Follow-ups:
Design of Computer Systems (INP-IT), DCSY
Digital Systems Design (INC), DCSY
 
Learning objectives:
To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.
Description:
Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
Learning outcomes and competences:
The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioral and structural description.
Syllabus of lectures:
  1. Basic VHDL language constructs, lexical description, VHDL source code.
  2. Data types, data objects, data classes, data objects declaration.
  3. VHDL language commands.
  4. Advanced VHDL features, VHDL 93.
  5. Delay modelling, time scheduling in VHDL.
  6. Combinational circuits modelling, "don't cares", tri-state-output circuits.
  7. Sequential circuits modelling, Mealy and Moore automata.
  8. Models testing, test benches.
  9. Designing at algorithm, register-transfer, and gate levels.
  10. Modelling for synthesis.
  11. Semantics for simulation and synthesis, delay in model.
  12. Programming techniques, shared components, flattening and structuring.
  13. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
Syllabus - others, projects and individual work of students:
Individual project.
Fundamental literature:
  1. Chang K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997
  2. Armstrong, J.R. - Gray F.G.: Structured Logic Design with VHDL, Prentice-Hall, 1993
  3. Armstrong, J.R. - Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
Study literature:
  1. Lecture notes
  2. Internet
Progress assessment:
Project and its defence supported by the written technical report in English language.
Exam prerequisites:
Classified "duty/class credit" is based on the successful project defence.