Title:

Diagnosis and Safe Systems

Code:DIA
Ac.Year:ukončen 2004/2005
Sem:Summer
Language of Instruction:Czech
Public info:http://www.fit.vutbr.cz/study/courses/DIA/public/
Credits:6
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSeminar
Exercises
Laboratory
Exercises
Computer
Exercises
Other
Hours:39106010
 ExamsTestsExercisesLaboratoriesOther
Points:50250025
Guarantor:Drábek Vladimír, doc. Ing., CSc. (DCSY)
Lecturer:Drábek Vladimír, doc. Ing., CSc. (DCSY)
Instructor:Drábek Vladimír, doc. Ing., CSc. (DCSY)
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Prerequisites: 
Digital and Impulse Circuits (CIO), DCSY
Logic Systems (LOS), DCSY
Follow-ups:
Fault-Tolerant Systems (SOP), DCSY
 
Learning objectives:
  To give the students the knowledge of methods for generation the tests for logic circuits, minimization and compression algorithms, and approaches to the design of testable circuits.
Description:
  Fault models of TTL, CMOS, PLA and bridge faults. Test generation methods. Structural tests. Functional tests. Sequential circuit testing. RTL level test generation. Random and pseudorandom test generation. Locating sequences. Fault dictionaries. Diagnostic data compression. Design for testability, structured methods. Built-in diagnosis. Memory testing. Processor and wiring testing. Fail-safe circuits. Instrumentation for diagnosis. Verification approaches.
Learning outcomes and competencies:
  Basic approaches to test generation and design for testability.
Syllabus of lectures:
 
  • Poruchové modely obvodů TTL, CMOS, PLA, zkratů.
  • Test generation approaches.
  • Funkctional tests.
  • Sequential circuit testing.
  • Test generation at RTL level.
  • Random and pseudorandom test generation.
  • Location sequences.
  • Fault dictionaries.
  • Diagnostic data compression.
  • Design for testability.
  • Built-in diagnosis.
  • Memory testing.
  • Processor and wiring testing.
  • Fail-safe circuits.
  • Fault-tolerance priciples.
  • Diagnostic equipment.
Syllabus of numerical exercises:
 
  • Fault models for TTL, CMOS, PLA and bridge faults.
  • Test generation approaches.
  • Functional tests.
  • Sequential circuit testing.
  • RTL-level test generation.
  • Random and pseudorandom test generation.
Syllabus of laboratory exercises:
 
  • Adder with built-in self test.
  • Linear feedback shift register.
  • Linear cellular automata.
  • Boundary scan testing.
  • Memory testing.
Fundamental literature:
 
  • Abramovici, M. - Breuer, M.A. - Friedman, A.D.: Digital Systems Testing and Testable Design, Computer Science Press, 1990
Study literature:
 Lecture notes in electronic format.
Controlled instruction:
  Mid-term exam and a project.
Progress assessment:
  Mid-term exam and a project.
Exam prerequisites:
  Pass a mid-term exam and a project.
 

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