Processor Architecture

IT-MSC-2MBS-Compulsory-Elective - group C
IT-MSC-2MMI1stCompulsory-Elective - group C
Language of Instruction:Czech
Completion:credit+exam (written)
Type of
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Guarantor:Dvořák Václav, prof. Ing., DrSc., DCSY
Lecturer:Dvořák Václav, prof. Ing., DrSc., DCSY
Jaroš Jiří, doc. Ing., Ph.D., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Design of External Adapters and Embedded Systems (NAV), DCSY
Graphic and Multimedia Processors (GMU), DCSY
Substitute for:
Advanced Computer Architecture (ARP), DCSY
Learning objectives:
  To familiarize students with architecture of the newest processors exploiting the instruction-level and thread-level parallelism. To clarify the role of a compiler and its  cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical, signal and multimedia processors. To master basic principles of low power architectures, texture compression, mapping algorithms for multiprocessors and data flow processors. 
  The course covers architecture of universal as well as special-purpose processors. Instruction-level parallelism (ILP) is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism (TLP) are discussed. Data parallelism is illustrated on SIMD-style processing and vector processors. The main type of specialized processors are graphical, signal and multimedia processors. The main techniques of parallelization and pipelining of graphical and multimedia operations are explained. Basic compression techniques of graphical data are also discussed.
Knowledge and skills required for the course:
  Von Neumann computer architecture, memory hierarchy,  microprogramming basics, programming in JSI, compiler's tasks and functions
Learning outcomes and competences:
  Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. The knowledge of architectureand hardware support of graphical and multimedia signals, their coding and compression.
Syllabus of lectures:
  • Scalar processors. Pipelined instruction processing and instruction dependencies. Typical CPU architecture.
  • Compiler-aided pipelined processing. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
  • Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
  • Optimization of instruction and data fetching. Examples of superscalar CPUs.
  • VLIW processors. SW pipelining, predication, binary translation.
  • Thread-level parallelism. Multithreaded processors, network processors.
  • Data paralelism: vector processors.
  • SIMD ISA extension, GPU and SIMT.
  • Architecture of graphics processing units.
  • Parallel computation on GPU, stream processing, CUDA/OpenCL.
  • Multimedia processors, Cell processor..
  • Signal processors.
  • Low power processors.


Syllabus of numerical exercises:
 Tutorials are not scheduled for this course.
Syllabus - others, projects and individual work of students:
  • Superscalar technique of instruction processing (SuperScalar simulator)
  • Performance simulation of memory hierarchy.
  • GPGPU, programming assignment. 


Fundamental literature:
  • Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1.
  • Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 4. vydání, Morgan Kaufman Publishers, Inc., 2006, 1136 s., ISBN 1-55860-596-7. 
Study literature:
  • Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1.
Progress assessment:
  Assessment of three small projects, 4 hours each, and a midterm examination.
Exam prerequisites:
  To get 20 out of 40 points for projects and midterm examination.

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