Title:

Design of Computer Systems

Code:INP
Ac.Year:2010/2011
Term:Winter
Curriculums:
ProgrammeBranchYearDuty
IT-BC-3BIT2ndCompulsory
Language:Czech
Private info:http://www.fit.vutbr.cz/study/courses/INP/private/
Credits:5
Completion:accreditation+exam (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:396007
 ExaminationTestsExercisesLaboratoriesOther
Points:52200028
Guarantee:Sekanina Lukáš, prof. Ing., Ph.D., DCSY
Lecturer:Bidlo Michal, Ing., Ph.D., DCSY
Sekanina Lukáš, prof. Ing., Ph.D., DCSY
Instructor:Bidlo Michal, Ing., Ph.D., DCSY
Vašíček Zdeněk, doc. Ing., Ph.D., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Prerequisites: 
Digital Systems Design (INC), DCSY
Machine Level Programming (IAS), DITS
Follow-ups:
Computer Communications and Networks (IPK), DIFS
 
Learning objectives:
  To give the students the knowledge of organization and functioning of operation, memory and control units, the algorithms with fixed and floating point operations, the way of controlling them and subsystem communication level.
Description:
  Principles of a processor. Introduction to VHDL. Von Neumann computer.  Data types, formats and coding. Instructions, formats, coding and addressing, ISA. VHDL models of algorithms and subsystems. Pipelining. Arithmetic and logic operations. Algorithms and function units. Sequencer: basic function, hard-wired and microprogram implementation. Memories: types, organization, controlling. Memory hierarchies, virtual memory. Peripheral units, buses and bus control, parallel and serial digital interfaces. Performance evaluation. Reliability of computer systems. Introduction to parallel architectures.
Knowledge and skills required for the course:
  Boolean algebra, basics of electrical circuits, basic computer elements, design of combinatorial and sequential circuits.
Subject specific learning outcomes and competences:
  Students are able to describe the functionality of operation, memory and control units and their communication using VHDL.
Generic learning outcomes and competences:
  The opinion on development trends and possibilities of computer technology.
Syllabus of lectures:
 
  • Introduction, processor and its function.
  • Data representation, accuracy and errors.  
  • Instruction sets, register structures.
  • Modelling in VHDL.
  • Pipelined processing.
  • Algorithms of fixed point operations.
  • Algorithms of floating point operations, iterative algorithms.
  • Controller.
  • Memories, cache memory.
  • Buses, peripheral interfacing and control.
  • Computer performance and performance evaluation.
  • Reliability of computer systems.
  • Introduction to parallel architectures.
Syllabus of numerical exercises:
 
  • VHDL
  • Processor in VHDL
  • Huffman code, Hamming code, modular arithmetics 
  • Adders and multipliers
  • Division
  • Iterative algorithms
  • Pipelined processing
  • Performance evaluation, reliability
Syllabus - others, projects and individual work of students:
 
  • Two projects will be assigned during the semester.
Fundamental literature:
 
  • John L. Hennessy, David A. Patterson: Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann Publ., 1996
  • Hamacher C., Vranesic Z., Zaky S.: Computer Organization, 5th edition, McGraw Hill, 2002
Study literature:
 
  • Vladimír Drábek: Computer organization, lecture notes of Brno University of Technology, PC-DIR publ., Brno, 1995
Controlled instruction:
  Within this course, attadance on the lectures and demonstrations is not monitored. The knowledge of students is examined by the projects, the mid-term exam and by the final exam. The minimal number of points which can be obtained from the final exam is 23. Otherwise, no points will be assigned to a student.
Progress assessment:
  Written final exam, mid-term exam and submitting projets in due dates.
Exam prerequisites:
  For receiving the credit and thus for entering the exam, students have to get at least 20 points during the semester.

Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.