Advanced Digital Systems
|Language of Instruction:||Czech|
|Hour/sem||Lectures||Sem. Exercises||Lab. exercises||Comp. exercises||Other|
|Guarantor:||Fučík Otto, doc. Dr. Ing., DCSY|
|Lecturer:||Kořenek Jan, Ing., Ph.D., DCSY|
Martínek Tomáš, Ing., Ph.D., DCSY
|Instructor:||Puš Viktor, Ing., DCSY|
|Faculty:||Faculty of Information Technology BUT|
|Department:||Department of Computer Systems FIT BUT|
| || ||To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.|
| || ||Combinational and sequential logic design techniques, algorithms, and tools review. Structured design concept. Design strategies. Design decomposition. Design tools. Introduction to VHDL Basic features of VHDL. Simulation and synthesis. Basic VHDL modeling techniques. Algorithmic level design. Register Level Design. HDL-based design techniques. Constrained design. ASIC and PLD design process. Fast prototyping. Modeling for synthesis. Top-down design methodology in VHDL. Design case study. Design automation algorithms. HW/SW co-design.|
|Knowledge and skills required for the course:|
| || ||Digital system design, basic programming skills.|
|Learning outcomes and competences:|
| || ||The students are able to design complex constrained digital systems using contemporary design techniques, hardware description language VHLD, and professional CAD tools.|
|Syllabus of lectures:|
- Combinational and sequential logic design techniques, algorithms, and tools review.
- Structured design concept. Design strategies. Design decomposition. Design tools.
- Introduction to VHDL
- Basic features of VHDL. Simulation and synthesis.
- Basic VHDL modeling techniques.
- Algorithmic level design.
- Register Level Design.
- HDL-based design techniques. Constrained design.
- ASIC and PLD design process. Fast prototyping.
- Modeling for synthesis.
- Top-down design methodology in VHDL.
- Design case study.
- Design automation algorithms. HW/SW co-design.
|Syllabus of computer exercises:|
- Design, schematic diagram drawing, and simulation of a 4-bit full ripple-carry adder.
- Combinational logic circuits modeling and simulation using VHDL.
- Sequential logic circuits modeling and simulation using VHDL.
- A 16-bit, in VHDL described, sequential multiplier modeling, simulation, and implementation.
|Syllabus - others, projects and individual work of students:|
- Individual five-hour VHDL project.
- Armstrong, J.R., Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
- Lecture notes in e-format
| || ||Written mid-term exam, submitted 4 PC ab reports and project in due dates.|
| || ||Requirements for class accreditation are not defined.|