Title:

Processor Architecture

Code:ACH
Ac.Year:2012/2013
Sem:Winter
Curriculums:
ProgrammeField/
Specialization
YearDuty
IT-MSC-2MBI-Elective
IT-MSC-2MBS-Compulsory-Elective - group C
IT-MSC-2MGM2ndElective
IT-MSC-2MIN-Elective
IT-MSC-2MIS-Elective
IT-MSC-2MMI-Compulsory-Elective - group C
IT-MSC-2MMM-Elective
IT-MSC-2MPV2ndCompulsory
IT-MSC-2MSK-Compulsory-Elective - group C
Language of Instruction:Czech
Credits:5
Completion:credit+exam (written)
Type of
instruction:
Hour/semLecturesSeminar
Exercises
Laboratory
Exercises
Computer
Exercises
Other
Hours:3900013
 ExamsTestsExercisesLaboratoriesOther
Points:60100030
Guarantor:Dvořák Václav, prof. Ing., DrSc. (DCSY)
Lecturer:Dvořák Václav, prof. Ing., DrSc. (DCSY)
Martínek Tomáš, Ing., Ph.D. (DCSY)
Instructor:Dvořák Václav, prof. Ing., DrSc. (DCSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Follow-ups:
Design of External Adapters and Embedded Systems (NAV), DCSY
Graphic and Multimedia Processors (GMU), DCSY
 
Learning objectives:
  To familiarize students with architecture of the newest processors exploiting the instruction-level and thread-level parallelism. To clarify the role of a compiler and its  cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical processors and its use for acceleration of numerical calculations (GPGPU), with digital signal processors (DSP) and with low-power techniques in processors for mobile applications.  
Description:
  The course covers architecture of universal as well as special-purpose processors. Instruction-level parallelism (ILP) is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism (TLP) are discussed. Data parallelism is illustrated on vector processors, SIMD streaming instructions and on graphical processors (SIMT). Parallelization of numerical calculations for GPU is also covered (CUDA). Other specialized processors covered in the course are network processors, DSPs, and low-power processors.
Knowledge and skills required for the course:
  Von Neumann computer architecture, memory hierarchy,   programming in JSI, compiler's tasks and functions
Learning outcomes and competencies:
  Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. The knowledge of architecture and hardware support of parallel computation on graphic processors can be directly applied for acceleration of intensive calculations. 
Syllabus of lectures:
 
  • Scalar processors. Pipelined instruction processing and instruction dependencies. Typical CPU architecture.
  • Compiler-aided pipelined processing. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
  • Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
  • Optimization of instruction and data fetching. Examples of superscalar CPUs.
  • VLIW processors. SW pipelining, predication, binary translation.
  • Thread-level parallelism. Multithreaded processors, network processors.
  • Data paralelism: vector processors.
  • SIMD ISA extension, GPU and SIMT.
  • Architecture of graphics processing units.
  • Parallel computation on GPU, stream processing, CUDA/OpenCL.
  • Multimedia processors, Cell processor.
  • Signal processors.
  • Low power processors.
Syllabus of numerical exercises:
 Tutorials are not scheduled for this course.
Syllabus - others, projects and individual work of students:
 
  • Superscalar technique of instruction processing (SuperScalar simulator)
  • Performance simulation of memory hierarchy.
  • GPGPU, programming assignment. 

 

Fundamental literature:
 
  • Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1
  • Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 5. vydání, Morgan Kaufman Publishers, Inc., 2012, 493 s., ISBN: 978-0-12-383872-8
  • Kirk, D., and Hwu, W.: Programming Massively Parallel Processors: A Hands-on Approach, Elsevier, 2010, s. 256, ISBN: 978-0-12-381472-2
Study literature:
 
  • current PPT slides for lectures
Progress assessment:
  Assessment of three small projects, 4 hours each, and a midterm examination.
Exam prerequisites:
  To get 20 out of 40 points for projects and midterm examination.
 

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