Computer Organization and Architecture

Ac.Year:ukončen 2004/2005
Language of Instruction:Czech
Private info:http://www.fit.vutbr.cz/study/courses/VPO/private/
Completion:credit+exam (written)
Type of
Guarantor:Drábek Vladimír, doc. Ing., CSc. (DCSY)
Lecturer:Drábek Vladimír, doc. Ing., CSc. (DCSY)
Instructor:Bryan Luděk, Ing. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Strnadel Josef, Ing., Ph.D. (DCSY)
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Digital and Impulse Circuits (CIO), DCSY
Logic Systems (LOS), DCSY
Graphic Processors (GMP), DCSY
Practical Parallel Programming (PPP), DCSY
Learning objectives:
  To give the students the knowledge of the design and operation of basic operation, memory and control blocks of a computer, the algorithms of basic fixed and floating point operations, the way of controlling them and communications between separate subsystems.
  Von Neumann computer. Introduction to VHDL. Performance evaluation. Information types, representation and coding. Instructions, formats and coding, addressing and instruction set architecture ISA. Modelling algorithms and subsystems using VHDL. Pipelined processing. Arithmetic and logic operations, algoritms and function units. Controller: basic functions, wired and microprogram implementation. Memories: types, organization, control algorithms. Memory hierarchy, virtual memory. Peripheral units, buses, control, parallel and serial interfaces.
Learning outcomes and competencies:
  Students are able to describe the functionality of operation, memory and control units and their communication using VHDL.
Syllabus of lectures:
  • Introduction, classification, empirical laws, performance.
  • Instruction set architectures, addressing, instruction coding.
  • Coding of data, signed number representation, floating point numbers, accuracy.
  • Hamming code. Adder, carry look-ahead. Barrel shifter.
  • Multiplication, Booth recoding, high-radix recoding, carry-save multipliers.
  • Division, non-restoring algorithm, SRT division. Floating point operations.
  • Newton iterative division. CORDIC. Interrupts.
  • Hardwired and microprogram sequencers, nanoprogramming.
  • Semiconductor memories, DRAM, block structure, refresh, magnetic memories.
  • Memory hierarchy, cache, directories, virtual memory, TLB.
  • Bus structures, asynchronous and synchronous transmission, PCI, IO subsystem.
  • IO processor. RAID.
Syllabus of numerical exercises:
  • 18.2. Digital circuits design - overview, introduction to VHDL
  • 25.2. Basic constructs and modules in VHDL, testbench, ModelSim
  • 4.3. Performance, Amdahl law, SPEC, Huffman code
  • 4 - 11.3. Hamming code (in VHDL), information coding, floating point
  • 18.3. ALU in VHDL
  • 25.3. Residue number system, CLA (VHDL)
  • 1.4. Barrel shifter (VHDL), multiplication, Booth recoding
  • 8.4. Multiplication in VHDL
  • 15.4. Division, (mid-term exam+classes)
  • 22.4. Division + Newton iteration algorithm
  • 29.4. Pipelined processing (filter in VHDL)
  • 6.5. Sequential circuits in VHDL
  • 13.5. Procesor DSP in VHDL
Syllabus - others, projects and individual work of students:
    Homeworks (sum of 24 points)
  • HW1 (?p) -
  • HW2 (?p) -
  • HW3 (?p) -
  • HW4 (?p) -
Fundamental literature:
  • John L. Hennessy, David A. Patterson: Computer Architecture: A quantitative Approach, 2nd edition, Morgan Kaufmann Publ., 1996
Study literature:
  • Vladimír Drábek: Computer organization, lecture notes of Brno University of Technology, PC-DIR publ., Brno, 1995
Controlled instruction:
  Realization of projects, mid-term exam passing.
Progress assessment:
  Written mid-term exam and submitting projets in due dates.
Exam prerequisites:
  Duty credit consists of mid-term exam passingand completing projects in due dates.

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