Functional Verification of Digital Systems
|Language of Instruction:||Czech|
|Hour/sem||Lectures||Sem. Exercises||Lab. exercises||Comp. exercises||Other|
|Guarantor:||Kotásek Zdeněk, doc. Ing., CSc., DCSY|
|Lecturer:||Zachariášová Marcela, Ing., Ph.D., DCSY|
|Instructor:||Zachariášová Marcela, Ing., Ph.D., DCSY|
|Faculty:||Faculty of Information Technology BUT|
|Department:||Department of Computer Systems FIT BUT|
|Tue||lecture - posunuta prednaska z FVS||2018-02-27||A113||12:00||13:50|
|Wed||exam - 2. oprava||2018-06-06||G202||15:00||16:50||1MIT|
|Wed||exam - 2. oprava||2018-06-06||G202||15:00||16:50||2MIT|
|Thu||exam - 1. oprava||2018-05-24||A112||09:00||10:50||1MIT|
|Thu||exam - 1. oprava||2018-05-24||A112||09:00||10:50||2MIT|
|Fri||exam - řádná||2018-05-11||A113||14:00||15:50||1MIT|
|Fri||exam - řádná||2018-05-11||A113||14:00||15:50||2MIT|
| || ||Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (OVM, UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.|
| || ||Importance of functional verification. Requirements specification and verification plan. Simulation and creating testbenches. Functional verification and its methods (pseudo-random stimuli generation, coverage-driven verification, asserion-based verification, self-checking mechanisms). Verification methodologies and SystemVerilog language. Reporting and correction of errors. Emulation and FPGA prototyping.|
|Knowledge and skills required for the course:|
| || ||Digital system design, basic programming skills.|
|Learning outcomes and competences:|
| || ||A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to OVM/UVM verification methodology.|
|Syllabus of lectures:|
- History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
- Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
- Introduction to functional verification. Functional verification techniques.
- Verification methodologies. HVL languages.
- Pseudo-random stimuli generation, direct tests, constraints.
- Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
- Self-checking mechanisms.
- Assertions. Assertion languages. Errors reporting.
- Assertion-based verification.
- Emulation and prototyping.
- Hardware debugging.
- Industry lecture.
- Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.
|Syllabus of laboratory exercises:|
- Creating testbench for arithmetic-logic unit (ALU).
- Creating verification environment for ALU.
Coverage-driven verification of ALU.
- Assertion-based verification of ALU.
|Syllabus - others, projects and individual work of students:|
| ||Design and implementation of verification environment for a selected digital systém.|
- Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175.
- Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217
- Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141.
- Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418.
- Amos, D., Lesea, A., Richter, R.: FPGA-Based Prototyping Methodology Manual: Best Practices in Design-For-Prototyping, Synopsys Press, USA,2011. ISBN: 1617300047.
| ||Lecture notes in e-format.|
| || |
- Participation in computer labs is not checked but active participation and presentation of results to the tutor is evaluated by 5 pts.
- If students cannot attend a lab, it is possible to create a review from a selected verification paper (possible just during active labs weeks).
| || ||Labs and project in due dates.|
| || ||Requirements for class accreditation are not defined.|