Department of Computer Systems

Application of functional verification in the digital circuits development process
Reseach leader:Lengál Ondřej
Team leaders:Kajan Michal, Kotásek Zdeněk
Agency:FRVŠ MŠMT
Code:FR1798/2012/G1
Start:2012
End:2012
Files: 
+Type Name Title Size Modified
iconlab_cviceni_podklady.pdfPokročilé číslicové systémy - lab. úlohy - podklady330 KB2013-01-03 09:57:14
iconpcs_verifikace_extended.pdfPokročilé číslicové systémy - přednáška733 KB2013-01-04 23:32:27
iconpcs_verifikace_short.pdfPokročilé číslicové systémy - přednáška - zkrácená verze431 KB2013-01-05 10:07:36
iconverifikace2012.pdfPokročilé číslicové systémy - přednáška631 KB2013-01-04 23:32:27
iconverifikace.pdfPokročilé číslicové systémy - lab. cvičení - text363 KB2013-01-03 09:34:34
iconovm_pcs_priklad.zipPokročilé číslicové systémy - lab. cvičení - OVM prostředí3,77 KB2013-01-04 23:51:42
iconOVM_PCS_zadani.zipPokročilé číslicové systémy - cvičení - OVM příklady129 KB2013-01-07 09:05:46
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With selected:
Keywords:functional verification, digital circuits
Annotation:
This project is aimed at creating additional study and demonstration materials for the course in Advanced Digital Systems (PCS). The produced materials will possibly be used in other courses dealing with the design of digital systems, such as Digital Systems Design (INC) and Hardware/software Codesign (HSC).
The set of materials will comprise a presentation containing a basic introduction to the area of functional verification and its use in the development process of digital systems with a high level of complexity. These materials will be supplemented with demonstration materials illustrating the creation, modification and application of verification environments and working with modern simulation tools used in practice.

Following projects

2013Application of methods and techniques of formal verification in the design of advanced digital circuits, FRVŠ MŠMT, FR1086/2013/G1, 2013, running
Research leader: Šimková Marcela
Team leaders: Kajan Michal, Kotásek Zdeněk

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