Department of Computer Systems

Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification

Czech title:Metodiky pro návrh systémů odolných proti poruchám do rekonfigurovatelných architektur - vývoj, implementace a verifikace
Reseach leader:Kotásek Zdeněk
Team leaders:Čekan Ondřej, Kaštil Jan, Mičulka Lukáš, Podivínský Jakub, Straka Martin, Strnadel Josef, Zachariášová Marcela
Team members:Krčma Martin, Szurman Karel
Agency:Ministry of Education, Youth and Sports Czech Republic
Code:LD12036
Start:2012-03-01
End:2015-11-30
Files: 
+Type Name Title Size +Last modified
iconVE_robot_controller.zipThe verification environment for the robot control unit350 KB2015-12-08 10:27:17
iconArchGen.zipArchGen: The tool enabling to develop fault tolerant architectures from VHDL description of the component470 KB2015-12-13 09:21:34
iconFT_Generator.zipThe tool enabling to develop fault tolerant architectures810 KB2015-12-13 09:23:26
iconGenerator_assembleru_pro_RISC_procesor.zipAssembler code generator for RISC processor535 KB2015-12-13 09:24:32
iconGPDRC.zipGPDRC: Generic partial dynamic reconfiguration controller93,8 KB2015-12-13 09:25:58
iconCheckGen.zipCkeckGen: The tool for generating checkers in VHDL VHDL225 KB2015-12-13 09:27:15
iconrobots_simulation.zipRobot simulation for searching its path in a maze311 KB2015-12-13 09:28:36
iconrobot_controller.zipRobot control unit231 KB2015-12-13 09:29:41
^ Select all
With selected:
Keywords:digital circuit, checker, fault tolerant system, SEU, simulation, generator, testing, verification, FPGA, reconfiguration, controller,
methodology
Annotation:

The project has these goals and steps of research:

1) Development and implementation of a new methodology for fault tolerant systems design into FPGA including error detection, faults localization, reconfiguration and synchronization after reconfiguration process.

2) Development and implementation of a new methodology for automated generation of diagnostic resources for on-line testing of FPGA based systems.

3) Development of techniques for the verification of fault tolerant systems quality together with SEU injector tool to be used for reconfigurable platforms.

4) Experimental evaluation of the methodology.

5) The analysis of project results.

Products

2015GPDRC: Generic partial dynamic reconfiguration controller, software, 2015
Authors: Straka Martin, Kaštil Jan
 Tools enabling to develop fault tolerant architectures and checkers from VHDL, software, 2015
Authors: Straka Martin
2012External SEU injector, software, 2012
Authors: Kaštil Jan

Publications

2015ČEKAN Ondřej. Principy generování verifikačních stimulů. In: Počítačové architektury a diagnostika PAD 2015. Zlín: Faculty of Applied Informatics, Tomas Bata University in Zlín, 2015, pp. 13-18. ISBN 978-80-7454-522-1.
 ČEKAN Ondřej, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Software Fault Tolerance: the Evaluation by Functional Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, pp. 284-287. ISBN 978-1-4673-8035-5.
 ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Universal Pseudo-random Generation of Assembler Codes for Processors. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, pp. 70-73.
 KRČMA Martin. FPNN - neuronové sítě v FPGA. In: Počítačové architektury a diagnostika PAD 2015. Zlín: Tomas Bata University in Zlín, 2015, pp. 81-86. ISBN 978-80-7454-522-1.
 KRČMA Martin, KOTÁSEK Zdeněk and KAŠTIL Jan. Fault Tolerant Field Programmable Neural Networks. In: 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015, pp. 1-4. ISBN 978-1-4673-6575-8.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2015, vol. 39, no. 8, pp. 1215-1230. ISSN 0141-9331.
 PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, pp. 13-16.
 PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela, ČEKAN Ondřej and KOTÁSEK Zdeněk. FPGA Prototyping and Accelerated Verification of ASIPs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, pp. 145-148. ISBN 978-1-4799-6779-7.
 ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Automation and Optimization of Coverage-driven Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, pp. 87-94. ISBN 978-1-4673-8035-5.
2014ČEKAN Ondřej. Universal Generation of Test Vectors for Functional Verification. In: Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014, pp. 44-49. ISBN 978-80-7494-027-9.
 KOTÁSEK Zdeněk and MIČULKA Lukáš. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 171-174. ISBN 978-0-7695-5074-9.
 MATUŠOVÁ Lucie, KAŠTIL Jan and KOTÁSEK Zdeněk. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, pp. 326-332. ISBN 978-0-7695-5074-9.
 PODIVÍNSKÝ Jakub. Testing Fault-Tolerance Properties in FPGA based Electro-mechanical Applications. In: Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014, pp. 13-18. ISBN 978-80-7494-027-9.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, pp. 312-319. ISBN 978-1-4799-5793-4.
 PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Complex Control System for Testing Fault-Tolerance Methodologies. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014, pp. 24-27. ISBN 978-2-11-129175-1.
 STRNADEL Josef and POKORNÝ Martin. Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. In: Proceedings of the 2014 17th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2014, pp. 333-340. ISBN 978-1-4799-5793-4.
 STRNADEL Josef and SLIMAŘÍK František. Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Computing and Informatics. Bratislava: Slovak Academic Press, 2014, vol. 33, no. 4, pp. 757-782. ISSN 1335-9150.
 SZURMAN Karel. Synchronization Methodology for Fault Tolerant System Recovery After Its Failure. In: Počítačové architektury & diagnostika 2014. Malá Skála: Liberec University of Technology, 2014, pp. 111-116. ISBN 978-80-7494-027-9.
 SZURMAN Karel, MIČULKA Lukáš and KOTÁSEK Zdeněk. State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, pp. 704-707. ISBN 978-0-7695-5074-9.
 SZURMAN Karel, MIČULKA Lukáš and KOTÁSEK Zdeněk. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. In: 9th IEEE International Conference on Computer Engineering and Systems. Káhira: IEEE Computer Society, 2014, pp. 231-236. ISBN 978-1-4799-6593-9.
 ZACHARIÁŠOVÁ Marcela. Application of Evolutionary Computing for Optimization of Functional Verification. In: Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014, pp. 135-140. ISBN 978-80-7494-027-9.
2013MIČULKA Lukáš and KOTÁSEK Zdeněk. Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA. In: The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2013). Avignon: Politecnico di Milano, 2013, pp. 53-56. ISBN 978-2-11-129175-1.
 MIČULKA Lukáš. Metoda návrhu systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. In: Počítačové architektury & diagnostika 2013. Plzeň: University of West Bohemia in Pilsen, 2013, pp. 63-68. ISBN 978-80-261-0270-0.
 MIČULKA Lukáš, STRAKA Martin and KOTÁSEK Zdeněk. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. In: 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013, pp. 227-234. ISBN 978-0-7695-5074-9.
 STRAKA Martin, KAŠTIL Jan, KOTÁSEK Zdeněk and MIČULKA Lukáš. Fault Tolerant System Design and SEU Injection based Testing. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2013, vol. 2013, no. 37, pp. 155-173. ISSN 0141-9331.
 STRNADEL Josef. Plánování úloh v systémech RT - V: zvyšování provozuschopnosti systémů. Automa. 2013, vol. 19, no. 2, pp. 46-49. ISSN 1210-9592.
 SZURMAN Karel. Fault Tolerant CAN Bus Control System Implemented into FPGA and its synchronization after failure and recovery. In: Počítačové architektury & diagnostika 2013. Plzeň: University of West Bohemia in Pilsen, 2013, pp. 21-26. ISBN 978-80-261-0270-0.
 SZURMAN Karel, KAŠTIL Jan, STRAKA Martin and KOTÁSEK Zdeněk. Fault Tolerant CAN Bus Control System Implemented into FPGA. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Karlovy Vary: IEEE Computer Society, 2013, pp. 289-292. ISBN 978-1-4673-1185-4.
 ZACHARIÁŠOVÁ Marcela. New Methods for Increasing Efficiency and Speed of Functional Verification. In: Počítačové architektury a diagnostika PAD 2013. Plzeň: University of West Bohemia in Pilsen, 2013, pp. 111-116. ISBN 978-80-261-0270-0.
 ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana and KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013, pp. 275-278. ISBN 978-1-4673-6133-0.
 ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana and KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013, pp. 35-38. ISBN 978-2-11-129175-1.
2012KAŠTIL Jan, STRAKA Martin and KOTÁSEK Zdeněk. Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, pp. 1-4.
 KAŠTIL Jan, STRAKA Martin, MIČULKA Lukáš and KOTÁSEK Zdeněk. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, pp. 250-257. ISBN 978-0-7695-4798-5.
 MIČULKA Lukáš and KOTÁSEK Zdeněk. Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, pp. 20-21. ISBN 978-3-902457-33-2.
 MIČULKA Lukáš. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. In: Počítačové architektury & diagnostika 2012. Praha: Faculty of Information Technology, Czech Technical University, 2012, pp. 109-115. ISBN 978-80-01-05106-1.
 STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems. In: CSE'2012 International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2012, pp. 146-153. ISBN 978-80-8143-049-7.
 STRAKA Martin, MIČULKA Lukáš, KAŠTIL Jan and KOTÁSEK Zdeněk. Test Platform for Fault Tolerant Systems Design Qualities Verification. In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012, pp. 336-341. ISBN 978-1-4673-1185-4.
 STRNADEL Josef and SLIMAŘÍK František. On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. In: Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Pistacaway: IEEE Computer Society, 2012, pp. 272-279. ISBN 978-0-7695-4798-5.
 ZACHARIÁŠOVÁ Marcela and LENGÁL Ondřej. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. Lecture Notes in Computer Science. 2012, vol. 2013, no. 7857, pp. 266-273. ISSN 0302-9743.
 ZACHARIÁŠOVÁ Marcela and LENGÁL Ondřej. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. FIT-TR-2012-03, Brno: Faculty of Information Technology BUT, 2012.
 ZACHARIÁŠOVÁ Marcela. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. In: Počítačové architektury a diagnostika. Praha: Czech Technical University, 2012, pp. 73-78. ISBN 978-80-01-05106-1.
 ZACHARIÁŠOVÁ Marcela, KAŠTIL Jan and KOTÁSEK Zdeněk. Verification of Fault-tolerant methodologies for FPGA Systems. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, pp. 55-58.

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