Department of Computer Systems

Verification and Optimization of Computer Systems
Reseach leader:Vojnar Tomáš
Team leaders:Češka Milan, Dudka Kamil, Fiedor Jan, Fučík Otto, Korček Pavol, Křena Bohuslav, Lengál Ondřej, Letko Zdeněk, Minárik Michal, Peringer Petr, Petrlík Jiří, Rogalewicz Adam, Sekanina Lukáš, Šimáček Jiří, Vašíček Zdeněk
Agency:VUT v Brně
Code:FIT-S-12-1
Start:2012
End:2014
Keywords:formal verification, testing and dynamic verification, optimization, computer systems
Annotation:
The project targets verification and optimization of computer-based systems.

Products

2012A Framework for Analysing Multi-threaded C/C++ Programs on the Binary Level, software, 2012
Authors: Fiedor Jan, Vojnar Tomáš
 VATA: A Library for Efficient Manipulation of Non-Deterministic Tree Automata, software, 2012
Authors: Lengál Ondřej, Šimáček Jiří, Vojnar Tomáš

Publications

2013Dudka Kamil, Müller Petr, Peringer Petr, Vojnar Tomáš: Predator: A Tool for Verification of Low-Level List Manipulation (Competition Contribution), In: Tools and Algorithms for the Construction and Analysis of Systems, Berlin, DE, Springer, 2013, p. 627-629, ISBN 978-3-642-36742-7, ISSN 0302-9743
 Dudka Kamil, Peringer Petr, Vojnar Tomáš: Byte-Precise Verification of Low-Level List Manipulation, In: 20th Static Analysis Symposium, Berlin, DE, Springer, 2013, p. 215-237, ISBN 978-3-642-33124-4, ISSN 0302-9743
 Dudka Kamil, Peringer Petr, Vojnar Tomáš: Byte-Precise Verification of Low-Level List Manipulation, FIT-TR-2012-04, Brno, CZ, FIT VUT, 2013, p. 48
 Holík Lukáš, Lengál Ondřej, Rogalewicz Adam, Šimáček Jiří, Vojnar Tomáš: Fully Automated Shape Analysis Based on Forest Automata, In: Proceedings of CAV'13, Heidelberg, DE, Springer, 2013, p. 1-16
 Charvát Lukáš, Smrčka Aleš, Vojnar Tomáš: An Abstraction of Multi-Port Memories with Arbitrary Addressable Units, In: Proceedings of the 14th Computer Aided Systems Theory, Las Palmas de Grand Canaria, ES, IUCTC, 2013, p. 254-255, ISBN 978-84-695-6971-9
 Charvát Lukáš, Smrčka Aleš, Vojnar Tomáš: An Abstraction of Multi-Port Memories with Arbitrary Addressable Units, In: Proceedings of the 14th Computer Aided Systems Theory??, Las Palmas de Grand Canaria, ES, 2013, p. 1-9
 Křena Bohuslav, Vojnar Tomáš: Automated formal analysis and verification: an overview, In: International Journal of General Systems, Vol. 2013, No. 42, Abingdon, GB, p. 335-365, ISSN 0308-1079
2012Bidlo Michal, Vašíček Zdeněk: Evolution of Cellular Automata Using Instruction-Based Approach, In: 2012 IEEE World Congress on Computational Intelligence, CA, US, IEEE, 2012, p. 1060-1067, ISBN 978-1-4673-1508-1
 Fiedor Jan, Vojnar Tomáš: ANaConDA: A Framework for Analysing Multi-threaded C/C++ Programs on the Binary Level, In: Lecture Notes in Computer Science, Vol. 2012, No. 7687, DE, p. 35-41, ISSN 0302-9743
 Fiedor Jan, Vojnar Tomáš: Noise-Based Testing and Analysis of Multi-threaded C/C++ Programs on the Binary Level, In: PADTAD '12, New York, US, ACM, 2012, p. 36-46, ISBN 978-1-4503-1456-5
 Habermehl Peter, Holík Lukáš, Rogalewicz Adam, Šimáček Jiří, Vojnar Tomáš: Forest Automata for Verification of Heap Manipulation, In: Formal Methods in System Design, Vol. 2012, No. 41, Berlin, DE, p. 83-106, ISSN 0925-9856
 Hrubá Vendula, Křena Bohuslav, Letko Zdeněk, Ur Shmuel, Vojnar Tomáš: Testing of Concurrent Programs with Genetic Algorithms, In: Lecture Notes in Computer Science, Vol. 2012, No. 7515, DE, p. 152-167, ISSN 0302-9743
 Hrubá Vendula, Křena Bohuslav, Letko Zdeněk, Vojnar Tomáš: Testing of Concurrent Programs Using Genetic Algorithms, FIT-TR-2012-01, Brno, CZ, 2012, p. 31
 Charvát Lukáš, Smrčka Aleš, Vojnar Tomáš: Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description, In: Proceedings of the 13th International Workshop on Microprocessor Test and Verification (MTV 2012), Austin, TX, US, 2012, p. 42-47
 Iosif Radu, Hojjat Hossein, Konečný Filip, Kuncak Viktor, Rummer Philipp: Accelerating Interpolants, In: Lecture Notes in Computer Science, Vol. 2012, No. 7561, DE, p. 187-202, ISSN 0302-9743
 Konečný Filip, Hojjat Hossein, Iosif Radu, Kuncak Viktor, Rummer Philipp, Garnier Florent: A Verification Toolkit for Numerical Transition Systems, In: Lecture Notes in Computer Science, Vol. 2012, No. 7436, DE, p. 247-251, ISSN 0302-9743
 Korček Pavol, Sekanina Lukáš, Fučík Otto: Calibrating Traffic Simulation Model using Vehicle Travel Times, In: Lecture Notes in Computer Science, Vol. 2012, No. 7495, DE, p. 807-816, ISSN 0302-9743
 Korček Pavol, Sekanina Lukáš, Fučík Otto: Evolutionary approach to calibration of cellular automaton based traffic simulation model, In: Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems, Anchorage, US, IEEE ITSS, 2012, p. 122-129, ISBN 978-1-4673-3062-6
 Korček Pavol, Žádník Martin: Lightweight benchmarking of platforms for network traffic processing, In: Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Tallin, EE, IEEE CS, 2012, p. 278-283, ISBN 978-1-4673-1185-4
 Kořenek Jan, Korček Pavol, Košař Vlastimil, Žádník Martin, Viktorin Jan: A New Embedded Platform for Rapid Development of Networking Applications, In: Proceedings of the 2012 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2012), Austin, US, IEEE CS, 2012, p. 81-82, ISBN 978-1-4503-1684-2
 Křena Bohuslav, Letko Zdeněk, Vojnar Tomáš: Analysis and Testing of Concurrent Programs, Brno, CZ, FIT VUT, 2012, p. 136, ISBN 978-80-214-4464-5
 Lengál Ondřej: An Efficient Finite Tree Automata Library: The Design of BDD-based Semi-symbolic Algorithms for Nondeterministic Finite Tree Automata, Saarbrücken, DE, LAP, 2012, p. 64, ISBN 978-3-659-27069-7
 Petrlík Jiří, Korček Pavol, Fučík Otto, Beszédeš Marián, Sekanina Lukáš: Estimation of traffic density map using evolutionary algorithm, In: Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems, Anchorage, US, IEEE ITSS, 2012, p. 632-637, ISBN 978-1-4673-3062-6
 Šimková Marcela, Lengál Ondřej: Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures, FIT-TR-2012-03, Brno, CZ, FIT VUT, 2012, p. 14

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