Department of Computer Systems

Conference paper

MRÁZEK Vojtěch. Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu. In: Počítačové architektury a diagnostika PAD 2016. Bořetice: Faculty of Information Technology BUT, 2016, pp. 61-64. ISBN 978-80-214-5376-0.
Publication language:czech
Original title:Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu
Title (en):Evolutionary reduction of power consumption: From transistor-level circuits till neural networks on the chip
Proceedings:Počítačové architektury a diagnostika PAD 2016
Conference:Počítačové architektury a diagnostika 2016
Place:Bořetice, CZ
Publisher:Faculty of Information Technology BUT
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With selected:
power consumption
evolutionary design
neural networks
median filter
sorting networks
The decreasing of power consumption becomes to be very important. The aim of this work is to utilise evolutionary algorithms in order to optimisation of the power consumption of digital circuits. It focus on the application of the algorithms in the real-world problems. Four applications were selected to show the ability of the proposed algorithms to decrease the power. New modules described on the transistor-level were designed, the power consumption of median filters were reduced, the new methods of approximate sorting were shown and the new approach for approximation in neural networks was introduced.  
   author = {Vojt{\v{e}}ch Mr{\'{a}}zek},
   title = {Evolu{\v{c}}n{\'{i}} sni{\v{z}}ov{\'{a}}n{\'{i}}
	p{\v{r}}{\'{i}}konu: Od obvod{\r{u}} na {\'{u}}rovni
	tranzistor{\r{u}} po neuronov{\'{e}} s{\'{i}}t{\v{e}} na
   pages = {61--64},
   booktitle = {Po{\v{c}}{\'{i}}ta{\v{c}}ov{\'{e}} architektury a
	diagnostika PAD 2016},
   year = {2016},
   location = {Bo{\v{r}}etice, CZ},
   publisher = {Faculty of Information Technology BUT},
   ISBN = {978-80-214-5376-0},
   language = {czech},
   url = {}

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