Department of Computer Systems

Abstract

ČEKAN Ondřej and KOTÁSEK Zdeněk. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016. ISBN 978-80-01-05984-5.
Publication language:english
Original title:Software-implemented Fault-Tolerant Program Generation
Title (cs):Generování softwarově implementované odolnosti proti poruchám
Pages:13-13
Book:Proceedings of the 4th Prague Embedded Systems Workshop
Conference:The 4th Prague Embedded Systems Workshop
Place:Roztoky u Prahy, CZ
Year:2016
ISBN:978-80-01-05984-5
Annotation
In our research, we are focusing on transient faults caused by Single Event Upset (SEUs). Transient faults are errors that occur unpredictably due to charged particles or electro-magnetic interferences. We did not solve these problems classically by additional hardware (hardware redundancy), but we used techniques that ensure correct behavior by the software (time or information redundancy). One of the possible ways that can be used in order to deal with such errors is Software-implemented Fault Tolerance (SFT). It is sometimes used as extra protection of the software. SFT is a commonly used technique which ensures the continuous availability of service while maintaining the desired performance and safety of the software in case of faults. Fault Tolerance (FT) is generally very important in safety-critical applications.
The idea is based on information redundancy which is added into the assembly instruction level (program). In our previous work [1], our approach of universal stimuli generation that we use in this work in a convenient way was presented. Our stimuli generator is used for the purpose of generating fault-tolerant assembly programs which are immune against SEU errors. We use a modification of the technique of instruction duplication which is based on triplication of instructions. Although Triple Modular Redundancy (TMR) is used predominantly in hardware, we used principles of TMR in software. We have implemented software Triple Instructional Redundancy (TIR) which is an analogy of TMR in the hardware. Verifying fault-tolerance effectiveness of programs is performed by an injector for simulation of SEU errors which modifies data using suitably positioned instructions.

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