Department of Computer Systems

Journal article

MRÁZEK Vojtěch, SEKANINA Lukáš, DOBAI Roland, SÝS Marek and ŠVENDA Petr. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019, vol. 99, no. 99, pp. 1-11. ISSN 1063-8210.
Publication language:english
Original title:Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques
Title (cs):Efektivní na čipu implementované ověřování náhodnosti dat využívající technik strojového učení
Journal:IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 99, No. 99, US
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randomness testing, evolvable hardware, FPGA
Randomness testing is an important procedure that bit streams, produced by critical cryptographic primitives such as encryption functions and hash functions, have to undergo. In this paper, a new hardware platform for randomness testing is proposed. The platform exploits the principles of genetic programming, which is a machine learning technique developed for automated program and circuit design. The platform is capable of evolving efficient randomness distinguishers directly on a chip. Each distinguisher is represented as a Boolean polynomial in the Algebraic Normal Form. Randomness testing is conducted for bit streams that are either stored in an on-chip memory or generated by a circuit placed on the chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System on Chip which integrates a field programmable gate array with on-chip ARM processors. The platform is evaluated in terms of the quality of randomness testing, performance and resources utilization. With power budget less than 3 W, the platform provides comparable randomness testing capabilities with the standard testing batteries running on a personal computer.
   author = {Vojt{\v{e}}ch Mr{\'{a}}zek and Luk{\'{a}}{\v{s}}
	Sekanina and Roland Dobai and Marek S{\'{y}}s and
	Petr {\v{S}}venda},
   title = {Efficient On-Chip Randomness Testing Utilizing
	Machine Learning Techniques},
   pages = {1--11},
   journal = {IEEE Transactions on Very Large Scale Integration (VLSI)
   volume = 99,
 number = 99,
   year = 2019,
   ISSN = {1063-8210},
   doi = {10.1109/TVLSI.2019.2923848},
   language = {english},
   url = {}

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