Department of Computer Systems

Journal article

PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub, ZACHARIÁŠOVÁ Marcela, KRČMA Martin and KOTÁSEK Zdeněk. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2017, vol. 52, no. 5, pp. 145-159. ISSN 0141-9331. Available from: http://www.sciencedirect.com/science/article/pii/S0141933117300200
Publication language:english
Original title:Functional Verification Based Platform for Evaluating Fault Tolerance Properties
Title (cs):Platforma pro ověřování odolnosti proti poruchám založena na funkční verifikaci
Pages:145-159
Place:NL
Year:2017
URL:http://www.sciencedirect.com/science/article/pii/S0141933117300200
Journal:Microprocessors and Microsystems, Vol. 52, No. 5, Amsterdam, NL
ISSN:0141-9331
Keywords
Functional verification, Robot controller, Electro-mechanical systems, Fault tolerance, Maze generation
Annotation
The fundamental topic of this article is the interconnection of simulation-based functional verification, which is standardly used for removing design errors from simulated hardware systems, with fault-tolerant mechanisms that serve for hardening electro-mechanical FPGA SRAM-based systems against faults. For this purpose, an evaluation platform that connects these two approaches was designed and tested for one particular casestudy: a robot that moves through a maze (its electronic part is the robot controller and the mechanical part is the robot itself). However, in order to make the evaluation platform generally applicable for various electro-mechanical systems, several subtopics and sub-problems need to solved. For example, the electronic controller can have several representations (hard-coded, processor based, neural-network based) and for each option, extendability of verification environment must be possible. Furthermore, in order to check complex behavior of verified systems, different verification scenarios must be prepared and this is the role of random generators or effective regression tests scenarios. Also, despite the transfer of the controller to the SRAM-based FPGA which was solved together with an injection of artificial faults, many more experiments must be done in order to create a sufficient fault-tolerant methodology that indicates how a general electronic controller can be hardened against faults by different fault-tolerant mechanisms in order to make it reliable enough in the real environment. All these additional topics are presented in this article together with some side experiments that led to their integration into the evaluation platform.
BibTeX:
@ARTICLE{
   author = {Jakub Podiv{\'{i}}nsk{\'{y}} and Ond{\v{r}}ej {\v{C}}ekan
	and Jakub Lojda and Marcela Zachari{\'{a}}{\v{s}}ov{\'{a}}
	and Martin Kr{\v{c}}ma and Zden{\v{e}}k Kot{\'{a}}sek},
   title = {Functional Verification Based Platform for Evaluating Fault
	Tolerance Properties},
   pages = {145--159},
   journal = {Microprocessors and Microsystems},
   volume = {52},
   number = {5},
   year = {2017},
   ISSN = {0141-9331},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=11318}
}

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