Department of Computer Systems

Publications

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2019LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, pp. 93-96. ISBN 978-1-72811-755-3.
 MRÁZEK Vojtěch, HANIF Muhammad A., VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology from Elementary Approximate Components. In: The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas, 2019, pp. 1-6. ISBN 978-1-4503-6725-7.
 PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, pp. 97-100. ISBN 978-1-72811-755-3.
 REK Petr and SEKANINA Lukáš. TypeCNN: CNN Development Framework With Flexible Data Types. In: Design, Automation and Test in Europe Conference. TBD, 2019, pp. 1-4.
 STRNADEL Josef. Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates (in press, not published yet). In: Design, Automation and Test in Europe Conference. (publishing details will be updated after publishing), 2019, pp. 1-4.
 VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Circuit Approximation Method Driven by Data Distribution. In: Design, Automation and Test in Europe Conference. TBA, 2019, pp. 1-6.
2018BORDOVSKÝ Gabriel. Challenges In the Computer Photoacoustic Tomograpy Using the k-Wave Toolbox. In: Počítačové architektúry & diagnostika PAD 2018. Plzeň: University of West Bohemia in Pilsen, 2018, pp. 49-52. ISBN 978-80-261-0814-6.
 CABAL Jakub, BENÁČEK Pavel, KEKELY Lukáš, KEKELY Michal, PUŠ Viktor and KOŘENEK Jan. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018, pp. 249-258. ISBN 978-1-4503-5614-5.
 CRHA Adam, ŠIMEK Václav and RŮŽIČKA Richard. Towards novel format for representation of polymorphic circuits. In: 13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Taormina: IEEE Circuits and Systems Society, 2018, pp. 1-2. ISBN 978-1-5386-5290-9.
 FIŠER Petr and ŠIMEK Václav. Optimum Polymorphic Circuits Synthesis Method. In: 13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Taormina: IEEE Circuits and Systems Society, 2018, pp. 1-6. ISBN 978-1-5386-5290-9.
 GROCHOL David and SEKANINA Lukáš. Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. In: Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018, pp. 257-263. ISBN 978-1-5386-7753-7.
 GROCHOL David and SEKANINA Lukáš. Multi-Objective Evolution of Ultra-Fast General-Purpose Hash Functions. In: European Conference on Genetic Programming. Berlin: Springer International Publishing, 2018, pp. 187-202. ISBN 978-3-319-77553-1.
 HUSA Jakub and KALKREUTH Roman. A Comparative Study on Crossover in Cartesian Genetic Programming. In: Genetic Programming 21st European Conference, EuroGP 2018, Proceedings. Cham: Springer International Publishing, 2018, pp. 203-219. ISBN 978-3-319-77553-1.
 JAROŠ Marta. Scientific Workflows Management. In: Počítačové architektúry & diagnostika PAD 2018. Plzeň: University of West Bohemia in Pilsen, 2018, pp. 25-28. ISBN 978-80-261-0814-6.
 KADLUBIAK Kristián, JAROŠ Jiří and TREEBY Bradley E. GPU-accelerated Simulation of Elastic Wave Propagation. In: 2018 International Conference on High Performance Computing & Simulation (HPCS). Orleans: IEEE Computer Society, 2018, pp. 188-195. ISBN 978-1-5386-7879-4.
 KUČERA Jan, KEKELY Lukáš, PIECEK Adam and KOŘENEK Jan. General IDS Acceleration for High-Speed Networks. In: Proceedings of the 36th IEEE International Conference on Computer Design, ICCD 2018. Orlando: Institute of Electrical and Electronics Engineers, 2018, pp. 366-373. ISBN 978-1-5386-8477-1.
 KUČERA Jan, KEKELY Lukáš, PUŠ Viktor, PIECEK Adam and KOŘENEK Jan. Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks. In: Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018, pp. 177-178. ISBN 978-1-4503-5902-3.
 LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. In: Počítačové architektury & diagnostika 2018. Stachy: University of West Bohemia in Pilsen, 2018, pp. 5-8. ISBN 978-80-261-0814-6.
 LOJDA Jakub and KOTÁSEK Zdeněk. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2018, pp. 31-32. ISBN 978-80-01-06456-6.
 LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 80-86. ISBN 978-1-5386-5709-6.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk and KRČMA Martin. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In: 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018, pp. 1-4. ISBN 978-1-5386-7311-9.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 244-251. ISBN 978-1-5386-7376-8.
 MATOUŠEK Denis, KUBIŠ Juraj, MATOUŠEK Jiří and KOŘENEK Jan. Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks. In: Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018, pp. 104-110. ISBN 978-1-4503-5902-3.
 MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In: Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 294-295. ISBN 978-1-4503-5764-7.
 MRÁZEK Vojtěch, SÝS Marek, VAŠÍČEK Zdeněk, SEKANINA Lukáš and MATYÁŠ Václav. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In: Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 1302-1309. ISBN 978-1-4503-5618-3.
 MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In: Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018, pp. 264-271. ISBN 978-1-5386-7753-7.
 MUSIL Miloš, MARTÍNEK Tomáš and ZENDULKA Jaroslav. FireProt: web server for automated design of thermostable proteins. In: DAZ & WIKT 2018 Proceedings. Brno, 2018, pp. 1-4.
 NEVORAL Jan and RŮŽIČKA Richard. Efficient Implementation of Bi-functional RTL Components - Case Study. In: 2018 New Generation of CAS (NGCAS). Valletta: IEEE Circuits and Systems Society, 2018, pp. 25-28. ISBN 978-1-5386-7680-6.
 NEVORAL Jan, RŮŽIČKA Richard and ŠIMEK Václav. CMOS Gates with Second Function. In: 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Hong Kong: IEEE Computer Society, 2018, pp. 82-87. ISBN 978-1-5386-7099-6.
 NEVORAL Jan, RŮŽIČKA Richard and ŠIMEK Václav. From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs. In: 2018 21st Euromicro Conference on Digital System Design. Praha: Institute of Electrical and Electronics Engineers, 2018, pp. 657-664. ISBN 978-1-5386-7376-8.
 NIKL Vojtěch, ŘÍHA Lubomír, VYSOCKÝ Ondřej and ZAPLETAL Jan. Optimal Hardware Parameters Prediction for Best Energy-to-Solution of Sparse Matrix Operations Using Machine Learning Techniques. In: INFOCOMP 2018. Barcelona: International Academy, Research, and Industry Association, 2018, pp. 43-48. ISBN 978-1-61208-655-2.
 PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2018, pp. 33-34. ISBN 978-80-01-06456-6.
 PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 63-69. ISBN 978-1-5386-5709-6.
 PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, pp. 9-12.
 PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej and KOTÁSEK Zdeněk. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 229-236. ISBN 978-1-5386-7376-8.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin, BURGET Radek, HRUŠKA Tomáš and KOTÁSEK Zdeněk. A Framework for Optimizing a Processor to Selected Application. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 564-574. ISBN 978-1-5386-5709-6.
 PUTEROVÁ Janka and MARTÍNEK Tomáš. digIS: automated pipeline for detecting distant, novel insertion sequence elements in prokaryotes. In: Data & Knowledge 2018. Brno: Brno University of Technology, 2018, pp. 1-5. ISBN 978-80-214-5679-2.
 PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Communications Society, 2018, pp. 129-134. ISBN 978-1-5386-5709-6.
 PÁNEK Richard. Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám. In: Počítačové architektury & diagnostika 2018. Stachy: University of West Bohemia in Pilsen, 2018, pp. 21-24. ISBN 978-80-261-0814-6.
 SEKANINA Lukáš, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In: 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018, pp. 377-380. ISBN 978-1-5386-9562-3.
 STRNADEL Josef. Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. In: Proceedings of 8th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA). Cham: Springer International Publishing, 2018, pp. 414-429. ISSN 0302-9743.
 SUOMI Visa, TREEBY Bradley E., JAROŠ Jiří, SAUNAVAARA Jani, KIVINIEMI Aida and BLANCO Roberto. The Effect of Tissue Physiological Variablity on Transurethral Ultrasound Therapy of the Prostate. In: Proceedings of 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). Honolulu, HI: Institute of Electrical and Electronics Engineers, 2018, pp. 5701-5704. ISBN 978-1-5386-3646-6.
 WIGLASZ Michal and SEKANINA Lukáš. Cooperative Coevolutionary Approximation in HOG-based Human Detection Embedded System. In: 2018 IEEE Symposium Series on Computational Intelligence (SSCI 2018). Bengaluru: Institute of Electrical and Electronics Engineers, 2018, pp. 1313-1320. ISBN 978-1-5386-9275-2.
 ČEKAN Ondřej and KOTÁSEK Zdeněk. Random Test Generation Through a Probabilistic Constrained Grammar. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, pp. 5-8.
 ČEKAN Ondřej, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Program Generation Through a Probabilistic Constrained Grammar. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 214-220. ISBN 978-1-5386-7376-8.
 ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Input and Output Generation for the Verification of ALU: a Use Case. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 331-336. ISBN 978-1-5386-5709-6.
 ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. ADAC: Automated Design of Approximate Circuits. In: Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018, pp. 612-620. ISBN 978-3-319-96145-3.
 ČUDOVÁ Marta, TREEBY Bradley E. and JAROŠ Jiří. Design of HIFU Treatment Plans using Evolutionary Strategy. In: GECCO'18 Companion: Genetic and Evolutionary Computation Conference Companion. Kyoto: Association for Computing Machinery, 2018, pp. 1568-1575. ISBN 978-1-4503-5764-7.
2017CRHA Adam, ŠIMEK Václav and RŮŽIČKA Richard. Synthesis tool for design of complex polymorphic circuits. In: 2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Palma de Mallorca: IEEE Circuits and Systems Society, 2017, pp. 149-154. ISBN 978-1-5090-6376-5.
 FAJČÍK Martin, ZACHARIÁŠOVÁ Marcela and SMRŽ Pavel. Automation of Processor Verification Using Recurrent Neural Networks. In: 2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV). Austin, Texas: Institute of Electrical and Electronics Engineers, 2017, pp. 15-20. ISBN 978-1-5386-3351-9.
 GROCHOL David and SEKANINA Lukáš. Comparison of Parallel Linear Genetic Programming Implementations. In: Recent Advances in Soft Computing: Proceedings of the 22nd International Conference on Soft Computing (MENDEL 2016) held in Brno, Czech Republic, at June 8-10, 2016. Cham: Springer International Publishing, 2017, pp. 64-76. ISBN 978-3-319-58088-3.
 GROCHOL David and SEKANINA Lukáš. Multiobjective Evolution of Hash Functions for High Speed Networks. In: Proceedings of the 2017 IEEE Congress on Evolutionary Computation. San Sebastian: IEEE Computer Society, 2017, pp. 1533-1540. ISBN 978-1-5090-4600-3.
 HUSA Jakub and DOBAI Roland. Designing Bent Boolean Functions With Parallelized Linear Genetic Programming. In: GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference. Berlín: Association for Computing Machinery, 2017, pp. 1825-1832. ISBN 978-1-4503-4939-0.
 KEKELY Michal and KOŘENEK Jan. Packet Classification with Limited Memory Resources. In: In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017, pp. 179-183. ISBN 978-1-5386-2145-5.
 KEŠNER Filip, SEKANINA Lukáš and BRÁZDIL Milan. Modular Framework for Detection of Inter-ictal Spikes in iEEG. In: The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'17). Los Alamos: Institute of Electrical and Electronics Engineers, 2017, pp. 418-421. ISBN 978-1-5090-2809-2.
 KIDOŇ Marek and DOBAI Roland. Evolutionary design of hash functions for IP address hashing using genetic programming. In: 2017 IEEE Congress on Evolutionary Computation (CEC). San Sebastian: Institute of Electrical and Electronics Engineers, 2017, pp. 1720-1727. ISBN 978-1-5090-4601-0.
 KLEPÁRNÍK Petr, ZEMČÍK Pavel and JAROŠ Jiří. Efficient Lossy Compression of Ultrasound Data. In: 2017 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT). Bilbao: Institute of Electrical and Electronics Engineers, 2017, pp. 232-237. ISBN 978-1-5386-4662-5.
 KOŘENEK Jan and KEKELY Michal. Mapping of P4 Match Action Tables to FPGA. In: Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017, pp. 1-2. ISBN 978-90-90-30428-1.
 KRČMA Martin and KOTÁSEK Zdeněk. Approximation accuracy of different FPNN types. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 81-82. ISBN 978-80-01-06178-7.
 KRČMA Martin, KOTÁSEK Zdeněk and LOJDA Jakub. Comparison of FPNNs Models Approximation Capabilities and FPGA Resources Utilization. In: Proceedings of IEEE 13th International Conference on Intelligent Computer Communication and Processing. Cluj-Nappoca: IEEE Computer Society, 2017, pp. 125-132. ISBN 978-1-5386-3367-0.
 KRČMA Martin, LOJDA Jakub and KOTÁSEK Zdeněk. Triple Modular Redundancy Used in Field Programmable Neural Networks. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-3298-7.
 LOJDA Jakub and KOTÁSEK Zdeněk. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 79-80. ISBN 978-80-01-06178-7.
 LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 59-62. ISBN 978-80-972784-0-3.
 LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 359-364. ISBN 978-1-5386-3298-7.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk and KRČMA Martin. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 273-278. ISBN 978-1-5386-3298-7.
 MATOUŠEK Jiří, ANTICHI Gianni, LUČANSKÝ Adam, MOORE Andrew W. and KOŘENEK Jan. ClassBench-ng: Recasting ClassBench After a Decade of Network Evolution. In: 2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Beijing: IEEE Computer Society, 2017, pp. 204-216. ISBN 978-1-5090-6386-4.
 MINAŘÍK Miloš and SEKANINA Lukáš. On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. In: 20th European Conference on Genetic Programming, EuroGP 2017. Berlin: Springer International Publishing, 2017, pp. 343-358. ISBN 978-3-319-55696-3.
 MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming. In: GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference. Berlin: Association for Computing Machinery, 2017, pp. 1849-1856. ISBN 978-1-4503-4939-0.
 MRÁZEK Vojtěch, HRBÁČEK Radek, VAŠÍČEK Zdeněk and SEKANINA Lukáš. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 258-261. ISBN 978-3-9815370-9-3.
 NEVORAL Jan, ŠIMEK Václav and RŮŽIČKA Richard. Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors. In: 2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Palma de Mallorca: IEEE Circuits and Systems Society, 2017, pp. 155-160. ISBN 978-1-5090-6376-5.
 NIKL Vojtěch, HRADECKÝ Michal, JAROŠ Jiří and KELEČÉNI Jakub. The investigation of the ARMv7 and Intel Haswell architectures suitability for performance and energy-aware computing. In: High Performance Computing. Cham: Springer International Publishing, 2017, pp. 377-393. ISBN 978-3-319-58667-0.
 PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 81-82. ISBN 978-80-01-06178-7.
 PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Reliability Analysis and Improvement of FPGA-based Robot Controller. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017, pp. 337-344. ISBN 978-1-5386-2146-2.
 PÁNEK Richard. Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 24-27. ISBN 978-80-972784-0-3.
 SHAFIQUE Muhammad, HAFIZ Rehan, JAVED Muhammad Usama, ABBAS Sarmad, SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In: 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017, pp. 627-632. ISBN 978-1-5090-6762-6.
 STRNADEL Josef. On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2017, pp. 352-355. ISBN 978-1-5386-2146-2.
 SZURMAN Karel and KOTÁSEK Zdeněk. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. In: Počítačové architektúry & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 51-54. ISBN 978-80-972784-0-3.
 VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Towards Low Power Approximate DCT Architecture for HEVC Standard. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 1576-1581. ISBN 978-3-9815370-9-3.
 VAŠÍČEK Zdeněk. Relaxed equivalence checking: a new challenge in logic synthesis. In: Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-0472-4.
 VYSOCKÝ Ondřej, BESEDA Martin, ŘÍHA Lubomír, ZAPLETAL Jan, NIKL Vojtěch, LYSAGHT Michael and KANNAN Venkatesh. Evaluation of the HPC Applications Dynamic Behavior in Terms of Energy Consumption. In: PROCEEDINGS OF THE FIFTH INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, GRID AND CLOUD COMPUTING FOR ENGINEERING. Stirlingshire: Civil-Comp Press, 2017, pp. 30-49. ISBN 978-1-905088-66-9.
 WIGLASZ Michal and SEKANINA Lukáš. Evolutionary Approximation of Gradient Orientation Module in HOG-based Human Detection System. In: 2017 IEEE Global Conference on Signal and Information Processing GlobalSIP 2017. Montreal: IEEE Signal Processing Society, 2017, pp. 1300-1304. ISBN 978-1-5090-5989-8.
 ČEKAN Ondřej and KOTÁSEK Zdeněk. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In: Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: TU Vienna, 2017, pp. 356-359. ISBN 978-1-5386-2146-2.
 ČEKAN Ondřej and KOTÁSEK Zdeněk. Random Test Stimuli Generation Based on a Probabilistic Grammar. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 43-44. ISBN 978-80-01-06178-7.
 ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017, pp. 416-423. ISBN 978-1-5386-3093-8.
 ČUDOVÁ Marta. Framework for Planning, Running and Monitoring Cooperating Computations. In: Počítačové architektúry & diagnostika PAD 2017. Bratislava: Slovak University of Technology in Bratislava, 2017, pp. 20-23. ISBN 978-80-972784-0-3.

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