Department of Computer Systems

Conference paper

NEVORAL Jan, ŠIMEK Václav and RŮŽIČKA Richard. Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors. In: 2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Palma de Mallorca: IEEE Circuits and Systems Society, 2017, pp. 155-160. ISBN 978-1-5090-6376-5.
Publication language:english
Original title:Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors
Title (cs):Kompaktní knihovna efektivních polymorfních hradel na bázi ambipolárních tranzistorů
Pages:155-160
Proceedings:2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Conference:12th International Conference on Design and Technology of Integrated Systems in Nanoscale Era
Place:Palma de Mallorca, ES
Year:2017
ISBN:978-1-5090-6376-5
Publisher:IEEE Circuits and Systems Society
Keywords
Polymorphic gate, ambipolar transistor, digital circuit, Polymorphic electronics, HSPICE simulation.
Annotation
Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or p- channel operating mode of the transistor structures which is controlled by means of switching the voltage level at a dedicated control electrode.

The gates were developed by an evolution approach using Cartesian genetic programming. Various discrete switch-level ambipolar transistor models extended by taking into account the threshold voltage drop degradation effect were used. A diverse range of polymorphic gates were designed, which clearly shows significant transistor savings compared to the conventional approaches. Finally, the individual components that belong to the library also suggest the opportunity how to considerably reduce the target size of complex polymorphic circuits.
BibTeX:
@INPROCEEDINGS{
   author = {Jan Nevoral and V{\'{a}}clav {\v{S}}imek and Richard
	R{\r{u}}{\v{z}}i{\v{c}}ka},
   title = {Compact Library of Efficient Polymorphic Gates based on
	Ambipolar Transistors},
   pages = {155--160},
   booktitle = {2017 12th International Conference on Design \&
	Technology of Integrated Systems in Nanoscale Era (DTIS)},
   year = {2017},
   location = {Palma de Mallorca, ES},
   publisher = {IEEE Circuits and Systems Society},
   ISBN = {978-1-5090-6376-5},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=11327}
}

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