Publications and citations of Roland Dobai

Full list of publications and citations

1. R. Dobai, J. Korenek, L. Sekanina: Evolutionary design of hash function pairs for network filters, In: Applied Soft Computing, vol. 56, no. 7, 173-181, 2017.
   1. A. Abdulhassan, M. Ahmadi: Many-field packet classification using AMQ-R-tree, In: Journal of High Speed Networks, vol. 24, no. 3, 219-241, 2018.
2. J. Husa, R. Dobai: Designing bent boolean functions with parallelized linear genetic programming, In: GECCO 2017 - Proceedings of the Genetic and Evolutionary Computation Conference Companion, 1825-1832, 2017.
3. M. Kidon, R. Dobai: Evolutionary design of hash functions for IP address hashing using genetic programming, In: 2017 IEEE Congress on Evolutionary Computation (CEC), 1720-1727, 2017.
4. R. Dobai, J. Korenek, L. Sekanina: Adaptive Development of Hash Functions in FPGA-Based Network Routers, In: IEEE Symposium Series on Computational Intelligence, 1-8, 2016.
5. R. Dobai, L. Sekanina: Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware, In: ACM Transactions on Reconfigurable Technology and Systems, vol. 8, no. 3, article no. 20, 2015.
   1. P.K.S. Kumari, S.V. Kumar: Design and simulation of evolvable hardware for image processing, In: International Conference on Micro-Electronics and Telecommunication Engineering, 331-336, 2017.
   2. R. Salvador: Evolvable Hardware in FPGAs: Embedded tutorial, In: 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Art. no. 7483877, 2016.
   3. J. Mora, E. de la Torre: Accelerating the evolution of a systolic array-based evolvable hardware system, In: Microprocessors and Microsystems, vol. 56, no. 1, 144-156, 2018.
   4. R. Yao, P. Zhu, J. Du, M. Wang, Z. Zhou: A general low-cost fast hybrid reconfiguration architecture for FPGA-based self-adaptive system, In: IEICE Transactions on Information and Systems, vol. E101D, no. 3, 616-626, 2018.
   5. J. Mora, R. Salvador, E. de la Torre: On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming, In: Genetic Programming and Evolvable Machines, article in press, 2018.
6. R. Dobai, J. Korenek: Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications, In: 2015 IEEE Symposium Series on Computational Intelligence, 1214-1219, 2015.
   1. N. McVicar, C.-C. Lin, S. Hauck: K-mer counting using bloom filters with an FPGA-attached HMC, In: IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, 203-210, 2017.
   2. A. Fairouz, M. Abusultan, S. P. Khatri: Circuit level design of a hardware hash unit for use in modern microprocessors, In: Proceedings of the ACM Great Lakes Symposium on VLSI, 101-106, 2017.
   3. A. Fairouz, M. Abusultan, S. P. Khatri: A novel hardware hash unit design for modern microprocessors, In: 34th IEEE International Conference on Computer Design, 412-415, 2016.
   4. A. Fairouz, S. P. Khatri: An FPGA-based coprocessor for hash unit acceleration, In: 35th IEEE International Conference on Computer Design, ICCD 2017, 301-304, 2017.
7. R. Dobai, K. Glette, J. Torresen, L. Sekanina: Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays, In: 2014 IEEE International Conference on Evolvable Systems, 85-92, 2014.
   1. J. Mora, A. Otero, E. d. l. Torre, T. Riesgo: Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs, In: 2015 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 1-7, 2015.
   2. J. Mora, E. de la Torre: Accelerating the evolution of a systolic array-based evolvable hardware system, In: Microprocessors and Microsystems, vol. 56, no. 1, 144-156, 2018.
   3. J. Mora, R. Salvador, E. de la Torre: On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming, In: Genetic Programming and Evolvable Machines, article in press, 2018.
8. R. Dobai: Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems, In: 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 1-6, 2014.
9. R. Dobai, M. Balaz: Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations, In: Computing and Informatics, vol. 32, no. 2, 251-272, 2013.
   1. L. Nagy, V. Stopjakova, J. Brenkus: Current sensing completion detection in single-rail asynchronous systems, In: Computing and Informatics, vol. 33, no. 5, 1116-1138, 2014.
10. R. Dobai, M. Balaz: SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults, In: Microprocessors and Microsystems, vol. 37, no. 2, 196-205, 2013.
    1. J. Balcarek, P. Fiser, J. Schmidt: PBO-Based Test Compression, In: 17th Euromicro Conference on Digital System Design (DSD), 679-682, 2014.
    2. J. Balcarek, P. Fiser, J. Schmidt: Techniques for SAT-Based Constrained Test Pattern Generation, In: Microprocessors and Microsystems, vol. 37, no. 2, 185-195, 2013.
11. R. Dobai, M. Balaz, P. Trebaticky, P. Malik, E. Gramatova: A Low-Overhead BIST Architecture for Digital Data Processing Circuits, In: Emerging Trends in Computing, Informatics, Systems Sciences, and Engineering; Lecture Notes in Electrical Engineering, vol. 151, 647-659, 2013.
12. R. Dobai, L. Sekanina: Image Filter Evolution on the Xilinx Zynq Platform, In: 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 164-171, 2013.
    1. R. Salvador: Evolvable Hardware in FPGAs: Embedded tutorial, In: 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Art. no. 7483877, 2016.
    2. T. Kryjak, M. Komorkiewicz, M. Gorgon: Hardware-software implementation of vehicle detection and counting using virtual detection lines, In: 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), 1-8, 2015.
    3. H. M. Abdelgawad, M. Safar, A. M. Wahba: High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform, In: International Journal of Computer, Control, Quantum and Information Engineering, vol. 9, no. 1, 2015.
    4. S. D. Carlo, G. Gambardella, P. Prinetto, D. Rolfo, P. Trotta: SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 10, 2198-2208, 2015.
    5. A. Gallego: Dynamically Scalable Evolvable Hardware Processing Array, In: Master Thesis, Universidad Politecnica de Madrid, Spain, 93 pages, 2014.
    6. T. Kryjak, M. Komorkiewicz, M. Gorgon: Real-time hardware–software embedded vision system for ITS smart camera implemented in Zynq SoC, In: Journal of Real-Time Image Processing, 1-37, 2016.
    7. A. A. S. Ali, A. Amira, F. Bensaali, M. Benammar, M. A. Akbar, M. Hassan, A. Bermak: Design and implementation of a gas identification system on Zynq SoC platform, In: ARPN Journal of Engineering and Applied Sciences, vol. 10, no. 20, 9758-9764, 2015.
    8. P. B. Campos: Variability-Aware Circuit Performance Optimisation Through Digital Reconfiguration, In: PhD Thesis, University of York, United Kingdom, 200 pages, 2015.
    9. T. K. H. Nguyen: Conception faible consommation d'un systčme de détection de chute (in French), In: PhD Thesis, Van Tuan Électronique Nice, France, 2015.
    10. P. Burian: Implementation of Selected Bio-Inspired Techniques by Programmable Logic Devices, In: PhD Thesis, University of West Bohemia, Czech Republic, 147 pages, 2014.
    11. S. Picek, B. Yang, V. Rozic, J. Vliegen, J. Winderickx, T. de Cnudde, N. Mentens: PRNGs for masking applications and their mapping to evolvable hardware, In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 10146, 209-227, 2017.
    12. M. Göbel, A. Elhossini, C.C. Chi, M. Alvarez-Mesa, B. Juurlink: A quantitative analysis of the memory architecture of FPGA-SoCs, In: 13th International Symposium on Applied Reconfigurable Computing, 241-252, 2017.
    13. A. Anitha, M.M. Latha: Partial dynamic reconfiguration framework for FPGAS through remote access, In: International Journal of High Performance Systems Architecture, vol. 7, no. 2, 98-104, 2017.
    14. Y. Wang, Y. Zhou, W. Li, G. Wang, L. Ren, R. Huang: Design of a cooperative vehicular platoon system based on Zynq/SoC architecture, In: Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, LNICST, 335-344, 2018.
    15. R. Yao, P. Zhu, J. Du, M. Wang, Z. Zhou: A general low-cost fast hybrid reconfiguration architecture for FPGA-based self-adaptive system, In: IEICE Transactions on Information and Systems, vol. E101D, no. 3, 616-626, 2018.
    16. Z. Yu, S. Yang, I. Sillitoe, K. Buckley: Towards a scalable hardware/software co-design platform for real-time pedestrian tracking based on a ZYNQ-7000 device, In: 2017 IEEE International Conference on Consumer Electronics-Asia, 127-132, 2018.
    17. J. Mora, R. Salvador, E. de la Torre: On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming, In: Genetic Programming and Evolvable Machines, article in press, 2018.
13. R. Dobai, L. Sekanina: Towards Evolvable Systems Based on the Xilinx Zynq Platform, In: 2013 IEEE International Conference on Evolvable Systems (ICES), 89-95, 2013.
    1. Z.-G. Bao, J.-L. Wan, X.-F. Ma: Optimization design of fault-tolerant image filter based on genetic algorithm, In: Journal of Shanghai Jiaotong University, vol. 49, no. 8, 1181-1185, 2015.
    2. F. Smith, A. E. v. d. Berg: Hardware genetic algorithm optimisation by critical path analysis using a custom VLSI architecture, In: South African Computer Journal, vol. 56, 120-135, 2015.
    3. M. A. Trefzer, A. M. Tyrrell: Devices and architectures for evolutionary hardware, In: Natural Computing Series, vol. 49, 27-87, 2015.
    4. J. Sawma, F. Khatounian, E. Monmasson, R. Ghosn, L. Idkhajine: Evaluation of the new generation of system-on-chip platforms for controlling electrical systems, In: Proceedings of the IEEE International Conference on Industrial Technology, 1570-1575, 2015.
    5. N. Ho, P. Kaufmann, M. Platzner: Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure, In: 2014 IEEE International Conference on Evolvable Systems, 31-37, 2014.
    6. O. E. Elnokity, I. I. Mahmoud, M. K. Refai, H. M. Farahat: Hardware Implementation of Virtual Reconfigurable Circuit for Fault Tolerant Evolvable Hardware System on FPGA, In: International Journal of Emerging Science and Engineering, vol. 2, no. 12, 29-32, 2014.
    7. S. Pan, S. Guo, L. Shi, Y. He, Z. Wang, Q. Huang: A spherical robot based on all programmable SoC and 3-D printing, In: 2014 IEEE International Conference on Mechatronics and Automation, 150-155, 2014.
    8. H. Calderon: Next Generation of Smart Machines: a survey of enabling technologies, In: Ciencia y Cultura, no. 32, 89-119, 2014.
    9. P. Sabouri, H. G. Hosseini, J. Collins: Border Detection of Melanoma Skin Lesions on a Single System on Chip (SoC), In: Journal of Computers, vol. 25, no. 1, 28-34, 2014.
    10. K. Glette, P. Kaufmann: Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System, In: IEEE Congress on Evolutionary Computation, 1706-1713, 2014.
    11. J. van de Belt, P. D. Sutton, L. E. Doyle: Accelerating software radio: Iris on the Zynq SoC, In: 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 294-295, 2013.
    12. E. Magdaleno, M. Rodriguez, F. Perez, D. Hernandez, E. Garcia: A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks, In: Sensors, vol. 14, no. 1, 416-430, 2014.
    13. J. R. R. Kimmitt: A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance, In: PhD. Thesis, Anglia Ruskin University, United Kingdom, 180 pages, 2015.
    14. T. T. Reddy, B. K. Madhavi, K. L. Kishore: Improved block based processing with dual partial reconfiguration memory approach, In: International Conference on Communication and Signal Processing, Art. no. 7322899, 2015.
    15. P. Govindan, B. Wang, P. Ravi, J. Saniie: Hardware and software architectures for computationally efficient three-dimensional ultrasonic data compression, In: IET Circuits Devices Systems, vol. 10, no. 1, 54-61, 2016.
    16. M. L. Crespo, A. Cicuttin, J. D. D. Gazzano, F. R. Calle: Reconfigurable Virtual Instrumentation Based on FPGA for Science and High-Education, In: Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation, IGI Global, 25 pages, 2016.
    17. W. Zhiming, G. Jie: Story Similarity Detection In Broadcast Domain Based On Multimodal Feature Fusion, In: American Journal of Engineering and Technology Research, vol. 15, no. 1, 176-182, 2015.
    18. R. R. le Roux: Bitstream specialisation for dynamic reconfiguration of real-time applications, In: PhD. Thesis, North-West University, South Africa, 145 pages, 2015.
    19. H. J. Butt: Hardware acceleration of an evolutionary algorithm on Xilinx Zynq-7000, In: Master Thesis, University of Oslo, Norway, 77 pages, 2015.
    20. T. Makryniotis, M. Dasygenis: Rapid implementation of embedded systems using Xilinx Zynq platform, In: ACM South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference, 6-10, 2016.
    21. S.-W. Pan, X.-Q Li, J. Han: Zynq-7000 SoC-based portable uncooled infrared imaging system, In: Journal of Beijing Institute of Technology (English Edition), vol. 25, no. 3, 435-440, 2016.
    22. Y.-T. Yang, S.-T. Zhang , Z.-C. Li, M.-D. Zhang, G.-C. Cao: Design and Implementation for High Speed Data Transfer Interface of PCI Express Based on Zynq Platform, In: Dianzi Keji Daxue Xuebao/Journal of the University of Electronic Science and Technology of China, vol. 46, no. 3, 522-528, 2017.
    23. S. Garg, N. Agrawal, S.J. Darak, P. Sikka: Spectral coexistence of candidate waveforms and DME in air-to-ground communications: Analysis via hardware software co-design on Zynq SoC, In: AIAA/IEEE Digital Avionics Systems Conference, art. no. 8102024, 2017.
    24. B.C. Maheshwari, J. Burns, M. Blott, G. Gambardella: Implementation of a scalable real time canny edge detector on programmable SOC, In: 2017 International Conference on Electrical and Computing Technologies and Applications, 1-5, 2017.
    25. V. V. Skvortsov, M. I. Zvyagina, A. A. Skitev: Sharing resources in heterogeneous multitasking computer systems based on FPGA with the use of partial reconfiguration, In: Proceedings of the 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, 370-373, 2018.
    26. A. Jones, J. Straub: Self-replicating 3D printed satellites, In: Proceedings of the International Astronautical Congress, 8264-8271, 2017.
    27. J. Annapurneshwari, C. Kanagasabapathi, S.S. Yellampalli: Study and analysis of communication logic between FPGA and the server, In: IEEE International Conference on Power, Control, Signals and Instrumentation Engineering, 1372-1375, 2017.
14. R. Dobai, M. Balaz, M. Fischerova: Automated Generation of Built-in Self-Repair Architectures for Random Logic SoC Cores, In: 15th Euromicro Conference on Digital System Design, DSD 2012, 73-78, 2012.
15. R. Dobai, M. Balaz: Genetic Method for Compressed Skewed-Load Delay Test Generation, In: 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012, 242-247, 2012.
    1. M. Hilbrich: Jobzentrisches Monitoring in Verteilten Heterogenen Umgebungen mit Hilfe Innovativer Skalierbarer Methoden (in German; English title: Job-Centric Monitoring in Distributed Heterogeneous Environments Using Innovative Scalable Methods), In: PhD Thesis, Technischen Universität Dresden, 237 pages, 2014.
    2. M. Hilbrich, M. Frank: Analysis of series of measurements from job-centric monitoring by statistical functions, In: Computer Science, vol. 18, no. 1, 3-19, 2017.
    3. M. Hilbrich, M. Weber, R. Tschuter: Automatic Analysis of Large Data Sets: A Walk-Through on Methods from Different Perspectives, In: International Conference on Cloud Computing and Big Data, 373-380, 2013.
16. R. Dobai, E. Gramatova: A Novel Automatic Test Pattern Generator for Asynchronous Sequential Digital Circuits, In: Microelectronics Journal, vol. 42, no. 3, 501-508, 2011.
    1. J. Xu, X. Tu: Study on Test Generation of Combinational Circuits Based on Improved Genetic Algorithm, In: Research and Exploration in Laboratory, vol. 31, no. 7, 2012.
17. R. Dobai: Test Generation For Asynchronous Sequential Digital Circuits, In: Information Sciences and Technologies: Bulletin of the ACM Slovakia, vol. 3, no. 1, 73-83, 2011.
18. M. Balaz, R. Dobai, E. Gramatova: Delay Faults Testing, In: Design and Test Technology for Dependable Systems-on-Chip, 377-394, 2011.
    1. M. Siebert: Methods of critical paths delay faults testing in digital systems, In: Information Sciences and Technologies Bulletin of the ACM Slovakia, vol. 8, no. 1, 1-6, 2016.
    2. J. Balcarek, P. Fiser, J. Schmidt: Techniques for SAT-Based Constrained Test Pattern Generation, In: Microprocessors and Microsystems, vol. 37, no. 2, 185-195, 2013.
19. R. Dobai, M. Balaz: SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults, In: 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 191-196, 2011.
    1. R. Hulle, P. Fiser, J. Schmidt: ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction, In: Microprocessors and Microsystems, vol. 61, no. 6, 43-57, 2018.
    2. J. Balcarek, P. Fiser, J. Schmidt: Techniques for SAT-Based Constrained Test Pattern Generation, In: Microprocessors and Microsystems, vol. 37, no. 2, 185-195, 2013.
20. R. Dobai, E. Gramatova: Deductive Fault Simulation Technique for Asynchronous Circuits, In: Computing and Informatics, vol. 29, no. 6, 1025-1043, 2010.
    1. L. Nagy, V. Stopjakova, J. Brenkus: Current sensing completion detection in single-rail asynchronous systems, In: Computing and Informatics, vol. 33, no. 5, 1116-1138, 2014.
21. R. Dobai: Automaticky Generator Testovacich Vektorov pre Asynchronne Obvody (in Slovak; English title: Automatic Test Pattern Generator for Asynchronous Circuits), In: Pocitacove architektury a diagnostika: PAD 2010, 147-152, 2010.
22. R. Dobai, E. Gramatova: Test Pattern Generation for the Combinational Representation of Asynchronous Circuits, In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 323-328, 2010.
    1. A. R. Khatri, A. Hayek, J. Börcsök: ATPG method with a hybrid compaction technique for combinational digital systems, In: 2016 SAI Computing Conference, art. no. 7556091, 2016.
    2. A. R. Khatri, A. Hayek, J. Börcsök: Validation of selecting SP-values for fault models under proposed RASP-FIT tool, In: 2017 1st International Conference on Latest Trends in Electrical Engineering and Computing Technologies, 1-7, 2018.
23. R. Dobai, E. Gramatova: Deductive Fault Simulation for Asynchronous Sequential Circuits, In: MEMICS 2009: Fifth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 229, 2009.
24. R. Dobai, E. Gramatova: Deductive Fault Simulation for Asynchronous Sequential Circuits, In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools: DSD 2009, 459-464, 2009.
    1. A. N. Nagamani, V. K. Agrawal, S. J. Bhat, J. Vandana, V. Vidya: On the design of hazard free reversible asynchronous circuits, In: 2014 International Conference on Advances in Electronics, Computers and Communications, article no. 7002414, 2014.
25. R. Dobai: Test Generation for Asynchronous Circuits, In: IIT.SRC 2009: Student Research Conference, 284-291, 2009.
26. R. Dobai: Testing of Delay Faults in Asynchronous Circuits, In: 14th IEEE European Test Symposium: ETS'09, CD, 2009.
27. R. Dobai: Testovanie Asynchronnych Digitalnych Obvodov (in Slovak; English title: Testing of Asynchronous Digital Circuits), In: Pocitacove architektury a diagnostika 2009 PAD: cesko-slovensky seminar pro studenty doktorskeho studia, 57-62, 2009.
28. R. Dobai: Design for Delay Testability of Asynchronous Digital Circuits, In: Pocitacove architektury a diagnostika 2008, 11-16, 2008.

Citations in ISI Web of Knowledge

• R. Dobai, M. Balaz: Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations, In: Computing and Informatics, vol. 32, no. 2, 251-272, 2013.
  1. L. Nagy, V. Stopjakova, J. Brenkus: Current sensing completion detection in single-rail asynchronous systems, In: Computing and Informatics, vol. 33, no. 5, 1116-1138, 2014.
• R. Dobai, M. Balaz: SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults, In: Microprocessors and Microsystems, vol. 37, no. 2, 196-205, 2013.
  1. J. Balcarek, P. Fiser, J. Schmidt: PBO-Based Test Compression, In: 17th Euromicro Conference on Digital System Design (DSD), 679-682, 2014.
• R. Dobai, L. Sekanina: Image Filter Evolution on the Xilinx Zynq Platform, In: 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 164-171, 2013.
  1. S. D. Carlo, G. Gambardella, P. Prinetto, D. Rolfo, P. Trotta: SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 10, 2198-2208, 2015.
• R. Dobai, L. Sekanina: Towards Evolvable Systems Based on the Xilinx Zynq Platform, In: 2013 IEEE International Conference on Evolvable Systems (ICES), 89-95, 2013.
  1. J. Sawma, F. Khatounian, E. Monmasson, R. Ghosn, L. Idkhajine: Evaluation of the new generation of system-on-chip platforms for controlling electrical systems, In: Proceedings of the IEEE International Conference on Industrial Technology, 1570-1575, 2015.
  2. N. Ho, P. Kaufmann, M. Platzner: Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure, In: 2014 IEEE International Conference on Evolvable Systems, 31-37, 2014.
  3. S. Pan, S. Guo, L. Shi, Y. He, Z. Wang, Q. Huang: A spherical robot based on all programmable SoC and 3-D printing, In: 2014 IEEE International Conference on Mechatronics and Automation, 150-155, 2014.
  4. K. Glette, P. Kaufmann: Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System, In: IEEE Congress on Evolutionary Computation, 1706-1713, 2014.
  5. E. Magdaleno, M. Rodriguez, F. Perez, D. Hernandez, E. Garcia: A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks, In: Sensors, vol. 14, no. 1, 416-430, 2014.
  6. P. Govindan, B. Wang, P. Ravi, J. Saniie: Hardware and software architectures for computationally efficient three-dimensional ultrasonic data compression, In: IET Circuits Devices Systems, vol. 10, no. 1, 54-61, 2016.
• R. Dobai, M. Balaz: Genetic Method for Compressed Skewed-Load Delay Test Generation, In: 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012, 242-247, 2012.
  1. M. Hilbrich, M. Weber, R. Tschuter: Automatic Analysis of Large Data Sets: A Walk-Through on Methods from Different Perspectives, In: International Conference on Cloud Computing and Big Data, 373-380, 2013.
• R. Dobai, E. Gramatova: Deductive Fault Simulation Technique for Asynchronous Circuits, In: Computing and Informatics, vol. 29, no. 6, 1025-1043, 2010.
  1. L. Nagy, V. Stopjakova, J. Brenkus: Current sensing completion detection in single-rail asynchronous systems, In: Computing and Informatics, vol. 33, no. 5, 1116-1138, 2014.

Citations in Scopus

• R. Dobai, J. Korenek, L. Sekanina: Evolutionary design of hash function pairs for network filters, In: Applied Soft Computing, vol. 56, no. 7, 173-181, 2017.
  1. A. Abdulhassan, M. Ahmadi: Many-field packet classification using AMQ-R-tree, In: Journal of High Speed Networks, vol. 24, no. 3, 219-241, 2018.
• R. Dobai, L. Sekanina: Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware, In: ACM Transactions on Reconfigurable Technology and Systems, vol. 8, no. 3, article no. 20, 2015.
  1. P.K.S. Kumari, S.V. Kumar: Design and simulation of evolvable hardware for image processing, In: International Conference on Micro-Electronics and Telecommunication Engineering, 331-336, 2017.
  2. R. Salvador: Evolvable Hardware in FPGAs: Embedded tutorial, In: 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Art. no. 7483877, 2016.
  3. J. Mora, E. de la Torre: Accelerating the evolution of a systolic array-based evolvable hardware system, In: Microprocessors and Microsystems, vol. 56, no. 1, 144-156, 2018.
  4. R. Yao, P. Zhu, J. Du, M. Wang, Z. Zhou: A general low-cost fast hybrid reconfiguration architecture for FPGA-based self-adaptive system, In: IEICE Transactions on Information and Systems, vol. E101D, no. 3, 616-626, 2018.
  5. J. Mora, R. Salvador, E. de la Torre: On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming, In: Genetic Programming and Evolvable Machines, article in press, 2018.
• R. Dobai, J. Korenek: Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications, In: 2015 IEEE Symposium Series on Computational Intelligence, 1214-1219, 2015.
  1. N. McVicar, C.-C. Lin, S. Hauck: K-mer counting using bloom filters with an FPGA-attached HMC, In: IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, 203-210, 2017.
  2. A. Fairouz, M. Abusultan, S. P. Khatri: Circuit level design of a hardware hash unit for use in modern microprocessors, In: Proceedings of the ACM Great Lakes Symposium on VLSI, 101-106, 2017.
  3. A. Fairouz, M. Abusultan, S. P. Khatri: A novel hardware hash unit design for modern microprocessors, In: 34th IEEE International Conference on Computer Design, 412-415, 2016.
  4. A. Fairouz, S. P. Khatri: An FPGA-based coprocessor for hash unit acceleration, In: 35th IEEE International Conference on Computer Design, ICCD 2017, 301-304, 2017.
• R. Dobai, K. Glette, J. Torresen, L. Sekanina: Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays, In: 2014 IEEE International Conference on Evolvable Systems, 85-92, 2014.
  1. J. Mora, E. de la Torre: Accelerating the evolution of a systolic array-based evolvable hardware system, In: Microprocessors and Microsystems, vol. 56, no. 1, 144-156, 2018.
  2. J. Mora, R. Salvador, E. de la Torre: On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming, In: Genetic Programming and Evolvable Machines, article in press, 2018.
• R. Dobai, M. Balaz: Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations, In: Computing and Informatics, vol. 32, no. 2, 251-272, 2013.
  1. L. Nagy, V. Stopjakova, J. Brenkus: Current sensing completion detection in single-rail asynchronous systems, In: Computing and Informatics, vol. 33, no. 5, 1116-1138, 2014.
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• R. Dobai, L. Sekanina: Image Filter Evolution on the Xilinx Zynq Platform, In: 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 164-171, 2013.
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• R. Dobai, M. Balaz: Genetic Method for Compressed Skewed-Load Delay Test Generation, In: 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012, 242-247, 2012.
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Citations in other databases

• R. Dobai, K. Glette, J. Torresen, L. Sekanina: Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays, In: 2014 IEEE International Conference on Evolvable Systems, 85-92, 2014.
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• R. Dobai, L. Sekanina: Image Filter Evolution on the Xilinx Zynq Platform, In: 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 164-171, 2013.
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• R. Dobai, L. Sekanina: Towards Evolvable Systems Based on the Xilinx Zynq Platform, In: 2013 IEEE International Conference on Evolvable Systems (ICES), 89-95, 2013.
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• R. Dobai, M. Balaz: Genetic Method for Compressed Skewed-Load Delay Test Generation, In: 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012, 242-247, 2012.
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