Project Details

Metodika a prostředky pro analýzu testovatelnosti digitálních obvodů

Project Period: 1. 1. 1998 - 31. 3. 2006

Project Type: grant

Code: GA102/98/1463

Agency: Czech Science Foundation

Program:

English title
Methodology and tools for digital circuits testability analysis
Type
grant
Keywords

digital circuit diagnostics-testability analysis

Abstract

The goal of the research activities is to develop and implement testability analysis methodology such that the concepts and algorithms could be used in any design environment, to offer an alternative to the full scan approach. It is supposed that the structure of the circuit under analysis will be transformed into a database representing the diagnostic features of the circuit. The applicability will be verified on circuits described in VHDL language and on ISCAS benchmark circuits.

Team members
Kotásek Zdeněk, Doc. Ing., CSc. (UIVT-VVS FEI VUT) , research leader
Drábek Vladimír, doc. Ing., CSc. (UIVT FEI VUT) , team leader
Fučík Otto, Dr. Ing. (UIVT FEI VUT) , team leader
Zbořil František, Doc. Ing., CSc. (UIVT FEI VUT) , team leader
Publications

2000

  • KOTÁSEK Zdeněk and RŮŽIČKA Richard. Behavioral Analysis for Testability on VHDL Source File. In: Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshopsborník konference IEEE DDECS. Bratislava: Slovak Academy of Science, 2000, pp. 209-212. ISBN 80-968320-3. Detail
  • RŮŽIČKA Richard. Data Dependent I Path and their Utilisation in DFT. In: Sborník prací studentů a doktorandů FEI VUT. Brno: Akademické nakladatelství CERM, 2000, pp. 228-230. ISBN 80-7204-155-X. Detail
  • SEKANINA Lukáš and RŮŽIČKA Richard. Design of the Special Fast Reconfigurable Chip Using Common FPGA. In: Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000, pp. 161-168. ISBN 80-968320-3-4. Detail
  • SEKANINA Lukáš and DRÁBEK Vladimír. Fault Tolerance and Reconfiguration in Cellular Systems. In: Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000, pp. 134-137. ISBN 80-968320-3-4. Detail
  • HLAVIČKA Jan, KOTÁSEK Zdeněk and RŮŽIČKA Richard. Formal Approach to RTL Testability Analysis. In: sborník konference IEEE LATW 2000. Rio de Janeiro: unknown, 2000, pp. 98-103. Detail
  • KOTÁSEK Zdeněk and RŮŽIČKA Richard. Partial Scan Methodologies - a Survey. In: sborník konference PDS2000. Ostrava: Elsevier Science, 2000, pp. 133-137. ISBN 0-08-043620-X. Detail
  • SEKANINA Lukáš and DRÁBEK Vladimír. Relation Between Fault Tolerance and Reconfiguration in Cellular Systems. In: 6th IEEE Int. On-Line Testing Workshop. Palma de Mallorca, Spain: IEEE Computer Society Press, 2000, pp. 25-30. ISBN 0-7695-0646-1. Detail
  • SLLAME Azeddien M. and SEKANINA Lukáš. Simulation and Modeling of Evolvable Hardware Based Systems. In: MS2000 International Conference on Modeling and Simulation. Las Palmas de Gran Canaria: unknown, 2000, pp. 485-492. ISBN 84-95286-59-9. Detail
  • KOTÁSEK Zdeněk and RŮŽIČKA Richard. Testability Analysis Based on Discrete Mathematics Concepts. In: Proc. of the 9-th International Colloquium on Numerical Analysis and Computer Science with Applications. Plovdiv: unknown, 2000, p. 113. Detail
  • KOTÁSEK Zdeněk and RŮŽIČKA Richard. The Implementation of RTL Testability Analysis Algorithms trough the Discrete Mathematics Concepts. In: Proc. of the Fourth International Scientific Conference on Electronic Computers and Informatics. Košice-Herľany: unknown, 2000, pp. 177-182. ISBN 80-88922-25-9. Detail
  • ZBOŘIL František. VHDL RT Level Parser/Analyser of a Source Code. In: Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2000, pp. 150-155. ISBN 80-88922-25-9. Detail

1999

  • KOTÁSEK Zdeněk. Partial Scan Methodologies - a Survey. In: sborník konference The Eighth International Colloquium on Numerical Analysis and Computer Science with Applications. Plovdiv: unknown, 1999, p. 110. Detail
  • HLAVIČKA Jan, KOTÁSEK Zdeněk and ZBOŘIL František. Partial Scan Methodology for RTL Designs. In: Compendium of Papers ETW'99. Constance: unknown, 1999, p. 2. ISBN 0-7695-0390-X. Detail
  • KOTÁSEK Zdeněk, RŮŽIČKA Richard and ZBOŘIL František. Partial Scan Methodology in VHDL Environment. In: CEI'99. Herľany: unknown, 1999, pp. 146-151. ISBN 80-88922-05-4. Detail
  • DRÁBEK Vladimír. The Economic Analysis of Design for Testability. In: I&IT'99, Sci. Conf. Banska Bystrica, Slovakia. Banska Bystrica: unknown, 1999, pp. 10-12. Detail
  • DRÁBEK Vladimír. The Unified Approach to Processor Testing. In: CE&I, Sci. Conf., Košice-Herlany, Slovakia. Košice-Herlany: unknown, 1999, pp. 192-195. ISBN 80-88922-05-4. Detail

1998

  • KOTÁSEK Zdeněk and ZBOŘIL František. Boundary Scan of PCBs with Xilinx FPGAs. In: Sborník konference ECI98. Herlany: unknown, 1998, pp. 70-74. ISBN 80-88786-94-0. Detail
  • KOTÁSEK Zdeněk and ZBOŘIL František. Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory. In: Proceedings of the ECI'98. Herlany: Slovak Academy of Science, 1998, pp. 75-80. ISBN 80-88786-94-0. Detail
  • KOTÁSEK Zdeněk, TOMÍŠEK Petr and ZBOŘIL František. Testing PCBs Based on Boundary Scan and EDIF Data Analysis. In: Proceedings of the DDECS'98. Szczyrk: unknown, 1998, pp. 95-101. ISBN 83-908409-6-0. Detail
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