Ing. Václav Bartoš

Education:

  • 2011 - Ing., Computer and Embedded Systems, FIT, VUT Brno
  • 2009 - Bc., Information Technology, FIT, VUT Brno

Professional career:

  • Research and developement in the area of netwrok traffic analysis at CESNET, z.s.p.o.
  • (formerly) HW designer (VHDL) at CESNET, z.s.p.o.

Research interests:

  • Network anomaly detection
  • (formerly) Hardware design (FPGA)

My favorite links:

Research group - Accelerated Network Technologies (ANT@FIT)
Liberouter project

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