Ing. David Grochol

GROCHOL David, SEKANINA Lukáš, KOŘENEK Jan, ŽÁDNÍK Martin and KOŠAŘ Vlastimil. Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols. Applied Soft Computing. Amsterdam: Elsevier Science, 2016, vol. 38, no. 1, pp. 933-941. ISSN 1568-4946.
Publication language:english
Original title:Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols
Title (cs):Evoluční návrh obvodů pro rychlou klasifikaci aplikačních protokolů v FPGA
Journal:Applied Soft Computing, Vol. 38, No. 1, Amsterdam, NL
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Application protocol, Classifier, Cartesian genetic programming, Field programmable gate array
The evolutionary design can produce fast and efficient implementations of digital circuits. It is shown in this paper how evolved circuits, optimized for the latency and area, can increase the throughput of a manually designed classifier of application protocols. The classifier is intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array (FPGA). The classification is performed using the first packet carrying the application payload. The improvements in latency (and area) obtained by Cartesian genetic programming are validated using a professional FPGA design tool. The quality of classification is evaluated by means of real network data. All results are compared with commonly used classifiers based on regular expressions describing application protocols.
   author = {David Grochol and Luk{\'{a}}{\v{s}} Sekanina and
	Jan Ko{\v{r}}enek and Martin
	{\v{Z}}{\'{a}}dn{\'{i}}k and Vlastimil
   title = {Evolutionary Circuit Design for Fast FPGA-Based
	Classification of Network Application Protocols},
   pages = {933--941},
   journal = {Applied Soft Computing},
   volume = 38,
 number = 1,
   year = 2016,
   ISSN = {1568-4946},
   doi = {10.1016/j.asoc.2015.09.046},
   language = {english},
   url = {}

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