Ing.

Lukáš Kekely

Ph.D.

Assistant professor

+420 54114 1357
ikekely@fit.vut.cz
L310 Office
120086/BUT personal ID

Publications

  • 2021

    FUKAČ Tomáš, MATOUŠEK Jiří, KOŘENEK Jan and KEKELY Lukáš. Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. In: 2021 International Conference on Field-Programmable Technology, ICFPT 2021. Auckland: Institute of Electrical and Electronics Engineers, 2021, pp. 185-193. ISBN 978-1-6654-2010-5.
    Detail

  • 2020

    KOŘENEK Jan, KORČEK Pavol and KEKELY Lukáš. Akcelerace analýzy síťového provozu. DSM Data Security Management, vol. 24, no. 4, 2020, pp. 30-34. ISSN 1211-8737.
    Detail

    KEKELY Michal, KEKELY Lukáš and KOŘENEK Jan. General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocessors and Microsystems, vol. 73, no. 3, 2020, pp. 1-12. ISSN 0141-9331.
    Detail

    KEKELY Lukáš, CABAL Jakub, PUŠ Viktor and KOŘENEK Jan. Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. In: Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: IEEE Computer Society, 2020, pp. 49-56. ISBN 978-1-7281-9535-3.
    Detail

  • 2019

    KEKELY Lukáš, CABAL Jakub and KOŘENEK Jan. Effective FPGA Architecture for General CRC. In: Architecture of Computing Systems - ARCS 2019. Neuvedeno: Springer International Publishing, 2019, pp. 211-223. ISBN 978-3-030-18655-5.
    Detail

    KUČERA Jan, KEKELY Lukáš, PIECEK Adam and KOŘENEK Jan. General IDS Acceleration for High-Speed Networks. In: Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Orlando: Institute of Electrical and Electronics Engineers, 2019, pp. 366-373. ISBN 978-1-5386-8477-1.
    Detail

  • 2018

    CABAL Jakub, BENÁČEK Pavel, KEKELY Lukáš, KEKELY Michal, PUŠ Viktor and KOŘENEK Jan. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018, pp. 249-258. ISBN 978-1-4503-5614-5.
    Detail

    KUČERA Jan, KEKELY Lukáš, PUŠ Viktor, PIECEK Adam and KOŘENEK Jan. Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks. In: Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018, pp. 177-178. ISBN 978-1-4503-5902-3.
    Detail

    KEKELY Lukáš, CABAL Jakub and KOŘENEK Jan. High-Speed Computation of CRC Codes for FPGAs. In: Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT 2018). Naha: IEEE Computer Society, 2018, pp. 237-240. ISBN 978-1-7281-0214-6.
    Detail

    KEKELY Michal, KEKELY Lukáš and KOŘENEK Jan. Memory Aware Packet Matching Architecture for High-Speed Networks. In: Proceedings of the 21st Euromicro Conference on Digital Systems Design. Praha: IEEE Computer Society, 2018, pp. 1-8. ISBN 978-1-5386-7376-8.
    Detail

  • 2015

    ŽÁDNÍK Martin, KEKELY Lukáš, VRÁNA Roman, HOLKOVIČ Martin and FRANKOVÁ Barbora. Dokumentace pro sestavení a zprovoznění prototypu hardwarově akcelerované sondy pro legální odposlechy. Brno: Faculty of Information Technology BUT, 2015.
    Detail

    KEKELY Lukáš, VRÁNA Roman and ŽÁDNÍK Martin. Report z testování prototypu 100Gb/s sondy pro zákonné odposlechy. FIT-TR-2015-001, Brno: Faculty of Information Technology BUT, 2015.
    Detail

    KEKELY Lukáš, KUČERA Jan, PUŠ Viktor, KOŘENEK Jan and VASILAKOS Athanasios. Software Defined Monitoring of Application Protocols. IEEE Transactions on Computers, vol. 65, no. 2, 2015, pp. 615-626. ISSN 0018-9340.
    Detail

  • 2014

    ZÁVODNÍK Tomáš, KEKELY Lukáš and PUŠ Viktor. CRC based hashing in FPGA using DSP blocks. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 179-182. ISBN 978-1-4799-4558-0.
    Detail

    PUŠ Viktor, KEKELY Lukáš and KOŘENEK Jan. Design Methodology of Configurable High Performance Packet Parser for FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 189-194. ISBN 978-1-4799-4558-0.
    Detail

    KEKELY Lukáš, ŽÁDNÍK Martin, MATOUŠEK Jiří and KOŘENEK Jan. Fast Lookup for Dynamic Packet Filtering in FPGA. In: Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Warszawa: IEEE Computer Society, 2014, pp. 219-222. ISBN 978-1-4799-4558-0.
    Detail

    KEKELY Lukáš, PUŠ Viktor and KOŘENEK Jan. Software Defined Monitoring of Application Protocols. In: Proceedings of IEEE INFOCOM 2014 - IEEE Conference on Computer Communications. Toronto: IEEE Computer Society, 2014, pp. 1725-1733. ISBN 978-1-4799-3360-0.
    Detail

    KEKELY Lukáš. Software Defined Monitoring: Nový prístup k monitorovaniu vysokorýchlostných počítačových sietí. In: Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014, pp. 74-79. ISBN 978-80-7494-027-9.
    Detail

    KEKELY Lukáš, PUŠ Viktor, BENÁČEK Pavel and KOŘENEK Jan. Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring. In: 2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014). Munich: IEEE Circuits and Systems Society, 2014, pp. 264-267. ISBN 978-3-00-044645-0.
    Detail

  • 2012

    KEKELY Lukáš and ŽÁDNÍK Martin. Hardwarově akcelerovaná sonda pro legální odposlechy. FIT-TR-2012-005, Brno: Faculty of Information Technology BUT, 2012.
    Detail

    KEKELY Lukáš, PUŠ Viktor and KOŘENEK Jan. Low-Latency Modular Packet Header Parser for FPGA. In: ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Austin: Association for Computing Machinery, 2012, pp. 77-78. ISBN 978-1-4503-1685-9.
    Detail

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