Ing.

Michal Kekely

Ph.D. student

+420 54114 1352
ikekelym@fit.vut.cz
L323 Office
143602/BUT personal ID

Publications

  • 2023

    KEKELY Michal and KOŘENEK Jan. Optimizing Packet Classification on FPGA. In: PROCEEDINGS 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallinn: Institute of Electrical and Electronics Engineers, 2023, pp. 7-12. ISBN 979-8-3503-3277-3. ISSN 2334-3133.
    Detail

  • 2020

    KEKELY Michal, KEKELY Lukáš and KOŘENEK Jan. General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocessors and Microsystems, vol. 73, no. 3, 2020, pp. 1-12. ISSN 0141-9331.
    Detail

    KEKELY Michal, HYNEK Karel and ČEJKA Tomáš. Pipelined ALU for effective external memory access in FPGA. In: 2020 23RD EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2020). Kranj: Institute of Electrical and Electronics Engineers, 2020, pp. 97-100. ISBN 978-1-7281-9535-3.
    Detail

  • 2018

    MARTINÁSEK Zdeněk, HAJNÝ Jan, SMÉKAL David, MALINA Lukáš, MATOUŠEK Denis and KEKELY Michal et al. 200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards. In: Proceedings of the ACM Conference on Computer and Communications Security. Association for Computing Machinery, 2018, pp. 11-17. ISBN 978-1-4503-5996-2.
    Detail

    CABAL Jakub, BENÁČEK Pavel, KEKELY Lukáš, KEKELY Michal, PUŠ Viktor and KOŘENEK Jan. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018, pp. 249-258. ISBN 978-1-4503-5614-5.
    Detail

    KEKELY Michal, KEKELY Lukáš and KOŘENEK Jan. Memory Aware Packet Matching Architecture for High-Speed Networks. In: Proceedings of the 21st Euromicro Conference on Digital Systems Design. Praha: IEEE Computer Society, 2018, pp. 1-8. ISBN 978-1-5386-7376-8.
    Detail

  • 2017

    KEKELY Michal and KOŘENEK Jan. Mapping of P4 Match Action Tables to FPGA. In: Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017, pp. 1-2. ISBN 978-90-90-30428-1.
    Detail

    KEKELY Michal and KOŘENEK Jan. Packet Classification with Limited Memory Resources. In: In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017, pp. 179-183. ISBN 978-1-5386-2145-5.
    Detail

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