Ing. Jan Kučera
- 2016 - Ing. (MSc), Computer and Embedded Systems, FIT, Brno University of Technology, Czech Republic.
- 2014 - Bc. (BSc), Information Technology, FIT, Brno University of Technology, Czech Republic.
- 2011 - Gymnasium Uherské Hradiště, Czech Republic.
- since 2012 - VHDL developer, CESNET z.s.p.o.
- Hardware acceleration of algorithms using FPGA.
- High-speed network security and monitoring.
- Packet classification in high-speed networks.