Ing. Jiří Matoušek

Education:

  • Ing., Mathematical Methods in Information Technology, FIT BUT, Brno, 2011
  • Bc., Information Technology, FIT BUT, Brno, 2009

Professional career:

  • 2011 - now, VHDL developer, CESNET z.s.p.o.
  • 2007 - 2010, VHDL developer, Liberouter project

Research interests:

  • hardware acceleration of processing network data using FPGA
  • partial dynamic reconfiguration of FPGA

Other interests:

  • scouting
  • otdoor activities

My favorite links:

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