Ing. Vojtěch Mrázek

ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk a VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA. To appear in IEEE, 2017, s. 1-8. ISBN 978-1-5386-3093-8.
Jazyk publikace:angličtina
Název publikace:Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished
Strany:1-8
Sborník:Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD)
Konference:2017 IEEE / ACM International Conference On Computer Aided Design
Místo vydání:Irvine, CA. To appear in IEEE, US
Rok:2017
ISBN:978-1-5386-3093-8
BibTeX:
@INPROCEEDINGS{
   author = {Milan {\v{C}}e{\v{s}}ka and Ji{\v{r}}{\'{i}}
	Maty{\'{a}}{\v{s}} and Vojt{\v{e}}ch Mr{\'{a}}zek and
	Luk{\'{a}}{\v{s}} Sekanina and Zden{\v{e}}k
	Va{\v{s}}{\'{i}}{\v{c}}ek and Tom{\'{a}}{\v{s}} Vojnar},
   title = {Approximating Complex Arithmetic Circuits with Formal Error
	Guarantees: 32-bit Multipliers Accomplished},
   pages = {1--8},
   booktitle = {Proceedings of 36th IEEE/ACM International Conference On
	Computer Aided Design (ICCAD)},
   year = {2017},
   location = {Irvine, CA. To appear in IEEE, US},
   ISBN = {978-1-5386-3093-8},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.cs?id=11420}
}

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