Ing. Vojtěch Mrázek

MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. In: Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. Porto: Institute of Electrical and Electronics Engineers, 2015, pp. 106-113. ISBN 978-1-4673-8299-1. Available from: http://dx.doi.org/10.1109/EUC.2015.20
Publication language:english
Original title:Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers
Title (cs):Automatický návrh integrovaných obvodů s nízkým příkonem: přesné a aproximační násobičky
Pages:106-113
Proceedings:Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing
Conference:13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing
Place:Porto, PT
Year:2015
URL:http://dx.doi.org/10.1109/EUC.2015.20
ISBN:978-1-4673-8299-1
Publisher:Institute of Electrical and Electronics Engineers
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Keywords
Evolutionary optimization, transistor level, low power, approximate computing, multiplier
Annotation
In order to satisfy a constant need of reducing energy consumption of electronic devices, the approximate computing paradigm has been introduced in recent years. This paradigm is based on the fact that there are applications that are inherently capable of absorbing some errors in computation. Multimedia signal processing represents a typical example that allows for quality to be traded off for power. Typically, the approximate circuits are designed at gate level. This paper introduces an automatic design method that is able to operate directly at transistor level which offers a great potential for discovering novel implementations of approximate circuits. The method combines a stochastic search algorithm with transistor-level circuit simulator and is able to handle the circuits consisting of hundreds of transistors. The goal of the search strategy is to improve the power consumption. To estimate power consumption, an algorithm based on transistor switching activity is proposed. A design of 4-bit multiplier was chosen as a case study. Two scenarios were considered. Firstly, the proposed method is applied to improve the power consumption of a common 4-bit multiplier and a 4-bit multiplier consisting of manually designed 2-bit multipliers. In both cases, approx. 3% power reduction was achieved. Then, it is demonstrated that a noticeable improvement can be obtained when the multipliers are designed using a hybrid approach operating at transistor as well as gate level. We discovered a novel implementation of an approximate 4-bit multiplier which has approximately by 40% better powerdelay product and exhibits 14% lower worst-case error compared to the best known 4-bit multiplier consisting of 2-bit manually optimized approximate multipliers
BibTeX:
@INPROCEEDINGS{
   author = {Vojt{\v{e}}ch Mr{\'{a}}zek and Zden{\v{e}}k
	Va{\v{s}}{\'{i}}{\v{c}}ek},
   title = {Automatic Design of Low-Power VLSI Circuits: Accurate and
	Approximate Multipliers},
   pages = {106--113},
   booktitle = {Proceedings of 13th IEEE/IFIP International Conference on
	Embedded and Ubiquitous Computing},
   year = {2015},
   location = {Porto, PT},
   publisher = {Institute of Electrical and Electronics Engineers},
   ISBN = {978-1-4673-8299-1},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=10831}
}

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