Ing. Viktor Puš

Puš, V., Kořenek, J.: Fast and scalable packet classification using perfect hash functions, In: Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, New York, US, ACM, 2009, p. 229-236, ISBN 978-1-60558-410-2

Publication language:

english

Original title:

Fast and scalable packet classification using perfect hash functions

Title (cs):

Rychlá a škálovatelná klasifikace paketů s využitím perfektních hashovacích funkcí

Pages:

229-236

Proceedings:

Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays

Conference:

Seventeenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Series:

Association for Computing Machinery

Place:

New York, US

Year:

2009

ISBN:

978-1-60558-410-2

Publisher:

Association for Computing Machinery

Files:

Keywords

classification, FPGA, perfect hash function

Annotation

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips.

BibTeX:

@INPROCEEDINGS{
   author = {Viktor Puš and Jan Kořenek},
   title = {Fast and scalable packet classification using perfect hash
	functions},
   pages = {229--236},
   booktitle = {Proceeding of the ACM/SIGDA international symposium on Field
	programmable gate arrays},
   series = {Association for Computing Machinery},
   year = {2009},
   location = {New York, US},
   publisher = {Association for Computing Machinery},
   ISBN = {978-1-60558-410-2},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8952}
}

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Ing. Viktor Puš