Experiments with HGEN unit

Second set of experiments was performed on hash generator (HGEN) unit which computes the hash value of input data using Bob Jenkin's Lookup2 hash algorithm. This unit uses FrameLink protocol as the main communication protocol. In order to fully exploit the capabilities of the accelerated version of HAVEN it is necessary to verify a complex system. For this purpose we also built systems with 2, 4, 8, and 16 parallelly working HGEN units.

Table 1 and Table 2 contains measured times needed for the verification runs for different number of transactions. Column NAV contains times for non-accelerated version, column AV times for accelerated version and last column Acc expresses achieved acceleration ratio. Second table differs from the first one in the time included for transaction generation.

Table 1.Acceleration of verification including the time of transaction generation.
TransactionsHGEN
NAV [s]AV [s]Acc [-]
10,000357.54.67
50,000176374.75
100,000353744.77
200,0007061494.74
500,0001,7603804.63
Table 2. Acceleration of verification without the time needed for transaction generation
TransactionsHGEN
NAV [s]AV [s]Acc [-]
10,00028.61.126.00
50,000144528.8
100,0002891028.9
200,0005782127.52
500,0001,4406024.00

Table 3 summarises the number of Virtex-5 slices used by the verification core of the accelerated version with the verified component (column Slices) and the total number of occupied slices of the FPGA together with NetCOPE (column Total slices). Total number of slices available (Xilinx Virtex-5 XC5VLX155T) is 24,320. Column Build time gives the time it took to generate the firmware for the FPGA. It can be observed that this time increases significantly as the total resource consuptiom approaches the capacity of the FPGA.

Table 3. Properties of verified HGEN component.
Component Slices Total slices Build time [s] B-E transactions
HGEN947 (3.9 %)9,787 (40.2 %)1,724622,000
HGEN 2x2,152 (8.8 %)11,315 (46.5 %)1,895-
HGEN 4x3,762 (15.4 %)12,938 (53.2 %)2,340-
HGEN 8x7,448 (30.6 %)16,304 (67.0 %)3,390-
HGEN 16x15,778 (64.9 %)22,096 (90.9 %)7,909-

The computed break-even number of transactions, which is, loosely speaking, the number of transactions for whito be beneļ¬cial, is further given in column B-E Transactions. Formally, this number is defined as the number transbe such that

break-even transactions equation

where build_time is the build time of the firmware (in seconds) and trans_per_sec(AV) and trans_per_sec(NAV) are the average number of transactions processed in a second by the accelerated and the non-accelerated version, respectively.

Also in this case, all experiments were performed using COMBOv2 LXT155 equipped with Xilinx Virtex-5 FPGA acceleration card, attached to a two Intel Xeon quad-core E5420@2.50 GHz processor based server with 10 GiB of RAM. As the SystemVerilog interpreter a Mentor Graphic's ModelSim SE-64 6.6a was used.