Ing. Michal Wiglasz

Relaxed equivalence checking for approximate computing

Czech title:Přibližná ekvivalence pro aproximativní počítání
Reseach leader:Vojnar Tomáš
Team members:Holík Lukáš, Lengál Ondřej, Rogalewicz Adam, Sekanina Lukáš, Vašíček Zdeněk
Agency:Czech Science Foundation
Code:GA16-17538S
Start:2016-01-01
End:2018-12-31
Keywords:approximate computing; genetic programming; evolvable hardware; relaxed equivalence checking; automata; logic
Annotation:
Approximate computing is a promising approach to obtain energy-efficient computer systems. It exploits the fact that many applications are error resilient, i.e., do not require a perfect output to be produced. An open problem is how to effectively obtain approximations that are good compromises between the error ratio, power consumption, and performance. Using evolutionary algorithms for the approximation has led to promising results, but it suffers from scalability problems in evaluating candidate solutions. For that, we propose a novel way: using advanced methods of formal verification redesigned to quickly calculate distances between candidate approximations and the reference implementation, which we call relaxed equivalence checking. The project seeks the following original contributions: (1) efficient algorithms for relaxed equivalence checking of combinational (stateless) and sequential (stateful) systems, (2) approximation algorithms based on genetic programming using the proposed relaxed equivalence checking, (3) experimental evaluation of the proposed approximation methods.

Products

2017Gaston - Symbolic WS1S Solver, software, 2017
Authors: Fiedor Tomáš, Holík Lukáš, Janků Petr, Lengál Ondřej, Vojnar Tomáš

Publications

2017CALINESCU Radu, ČEŠKA Milan, GERASIMOU Simos, KWIATKOWSKA Marta and PAOLETTI Nicola. Recent Advances in Designing Robust Probabilistic Systems. 2nd International Workshop on Design and Analysis of Robust Systems (Extended Abstract). Berlin, 2017.
 CALINESCU Radu, ČEŠKA Milan, GERASIMOU Simos, KWIATKOWSKA Marta and PAOLETTI Nicola. Designing Robust Software Systems through Parametric Markov Chain Synthesis. In: Proceedings of 14th IEEE International Conference On Software Architecture. To appear in IEEE: IEEE Computer Society, 2017, pp. 131-140. ISBN 978-1-5090-5729-0.
 CALINESCU Radu, ČEŠKA Milan, GERASIMOU Simos, KWIATKOWSKA Marta and PAOLETTI Nicola. RODES: A Robust-Design Synthesis Tool for Probabilistic Systems. In: 14th International Conference on Quantitative Evaluation of SysTems. To appear in LNCS: Springer Verlag, 2017, pp. 1-4.
 CARDELLI Luca, ČEŠKA Milan, FRANZLE Martin, KWIATKOWSKA Marta, LAURENTI Luca, PAOLETTI Nicola and WHITBY Max. Syntax-Guided Optimal Synthesis for Chemical Reaction Networks. In: Proceedings of the 29th International Conference on Computer Aided Verification. To appear in LNCS, 2017, pp. 1-20.
 ENEA Constantin, LENGÁL Ondřej, SIGHIREANU Mihaela and VOJNAR Tomáš. Compositional Entailment Checking for a Fragment of Separation Logic. Formal Methods in System Design. Berlin: Springer Verlag, 2017, vol. 2017, no. 1, pp. 1-33. ISSN 0925-9856.
 FIEDOR Tomáš, HOLÍK Lukáš, JANKŮ Petr, LENGÁL Ondřej and VOJNAR Tomáš. Lazy Automata Techniques for WS1S. arXiv:1701.06282, 2017.
 FIEDOR Tomáš, HOLÍK Lukáš, JANKŮ Petr, LENGÁL Ondřej and VOJNAR Tomáš. Lazy Automata Techniques for WS1S. In: Proceedings of TACAS'17. Heidelberg: Springer Verlag, 2017, pp. 407-425. ISBN 978-3-662-54576-8.
 MINAŘÍK Miloš and SEKANINA Lukáš. On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. In: 20th European Conference on Genetic Programming, EuroGP 2017. Berlin: Springer International Publishing, 2017, pp. 343-358. ISBN 978-3-319-55696-3.
 MRÁZEK Vojtěch, HRBÁČEK Radek, VAŠÍČEK Zdeněk and SEKANINA Lukáš. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 258-261. ISBN 978-3-9815370-9-3.
 SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering. 2017, vol. 26, no. 3, pp. 623-632. ISSN 1210-2512.
 VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Towards Low Power Approximate DCT Architecture for HEVC Standard. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 1576-1581. ISBN 978-3-9815370-9-3.
 VAŠÍČEK Zdeněk. Relaxed equivalence checking: a new challenge in logic synthesis. In: Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-0472-4.
 ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA. To appear in IEEE, 2017, pp. 1-8. ISBN 978-1-5386-3093-8.
2016ABATE Alessandro, ČEŠKA Milan and KWIATKOWSKA Marta. Approximate Policy Iteration for Markov Decision Processes via Quantitative Adaptive Aggregations. In: Proceedings of 14th International Symposium on Automated Technology for Verification and Analysis. Heidelberg: Springer Verlag, 2016, pp. 1-16. ISBN 978-3-319-46519-7.
 CHEN Yu-Fang, HSIEH Chiao, LENGÁL Ondřej, LII Tsung-Ju, TSAI Ming-Hsien, WANG Bow-Yaw and WANG Farn. PAC Learning-Based Verification and Model Synthesis. In: Proceedings of the 38th International Conference on Software Engineering. Austin, TX: Association for Computing Machinery, 2016, pp. 714-724. ISBN 978-1-4503-3900-1.
 DVOŘÁČEK Petr and SEKANINA Lukáš. Evolutionary Approximation of Edge Detection Circuits. In: 19th European Conference on Genetic programming. Berlin: Springer International Publishing, 2016, pp. 19-34. ISBN 978-3-319-30667-4.
 HOLÍK Lukáš, LENGÁL Ondřej, ROGALEWICZ Adam, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology. In: 2nd Workshop on Approximate Computing (WAPCO 2016). Prague, 2016, pp. 1-6.
 HRBÁČEK Radek, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Approximate Circuits by Means of Multi-Objective Evolutionary Algorithms. In: Proceedings of the 11th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Istanbul: Istanbul Sehir University, 2016, pp. 239-244. ISBN 978-1-5090-0335-8.
 MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee. In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on. Bremen: Institute of Electrical and Electronics Engineers, 2016, pp. 221-228. ISBN 978-1-5090-0733-2.
 SEKANINA Lukáš and KAPUSTA Vlastimil. Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. In: GECCO'16 Companion. New York: Association for Computing Machinery, 2016, pp. 1411-1418. ISBN 978-1-4503-4323-7.
 VAVERKA Filip, HRBÁČEK Radek and SEKANINA Lukáš. Evolving Component Library for Approximate High Level Synthesis. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.
 VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.

Your IPv4 address: 54.166.245.10
Switch to IPv6 connection

DNSSEC [dnssec]