Doc. Ing. Jiří Jaroš, Ph.D.

JAROŠ Jiří and DVOŘÁK Václav. Speeding-up OAS and AAS Communication in Networking System on Chips. In: Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Sopron: University of West Hungary, 2005, p. 4. ISBN 9639364487.
Publication language:english
Original title:Speeding-up OAS and AAS Communication in Networking System on Chips
Title (cs):Speeding-up OAS and AAS Communication in Networking System on Chips
Pages:4
Proceedings:Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems
Conference:The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Place:Sopron, HU
Year:2005
ISBN:9639364487
Publisher:University of West Hungary
Keywords
BOA algorithm, communication patterns, multiprocessor topology, hypercube, AMP
Annotation
As chip multiprocessors are quickly penetrating new application areas in network and media processing, their interconnection architectures become a subject of optimization. Group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology using WH (Wormhole) switching.
BibTeX:
@INPROCEEDINGS{
   author = {Ji{\v{r}}{\'{i}} Jaro{\v{s}} and V{\'{a}}clav
	Dvo{\v{r}}{\'{a}}k},
   title = {Speeding-up OAS and AAS Communication in
	Networking System on Chips},
   pages = {4},
   booktitle = {Proc. of 8th IEEE Workshop on Design and Diagnostic of
	Electronic Circuits and Systems},
   year = {2005},
   location = {Sopron, HU},
   publisher = {University of West Hungary},
   ISBN = {9639364487},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en?id=7750}
}

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