Ing. Jan Kořenek, Ph.D.

FPGA-Based Platform for Traffic Filtration in 100 Gbps Networks

Authors:Matoušek Jiří, Kekely Lukáš, Kořenek Jan
Type:specimen
Created:2014
Licence:required
Files: 
+Type Name Title Size Last modified
 ..Uplevel directory
iconakceleracni_karta.jpgAcceleration card COMBO 100G utilizing FPGA Virtex-7287 KB2015-01-07 16:03:22
iconakceleracni_karta_test.jpgAcceleration card in a test environment345 KB2015-01-07 16:03:14
iconplatforma_vivado.jpgFirmware part of the platform in the Vivado Design Suite110 KB2015-01-07 16:03:35
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Keywords:100 Gbps networks, FPGA platform, network traffic filtration, cuckoo hash
Description:
This platform targets network traffic filtration in 100 Gbps networks. The platform is based on a PCIe acceleration card called COMBO that utilizes 100G network interface, Virtex-7 HT FPGA and three QDR memory modules with aggregated throughput of 100 Gbps. Thanks to efficient utilization of the cuckoo hash algorithm, the platform is able to filter nework traffic in 100 Gbps networks. Moreover, a unique architecture of the filter allows to specify thousands of filtration rules in a form of either IP addresses or network flow 5-tuples. Therefore, the platform can be used in the area of network security as well as lawful interception. Efficient use of the Vivado Design Suite also makes the platform easily extensible with the help of Vivado IP cores methodology.
Location:
http://www.fit.vutbr.cz/research/view_product.php.en?id=419
Research groups:
Departments:

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