Ing. Jan Kořenek, Ph.D.

VIKTORIN Jan, KORČEK Pavol, KOŠAŘ Vlastimil and KOŘENEK Jan. Framework for Fast Prototyping of Applications running on Reconfigurable Systems on Chip. In: Proceedings of the 2013 Conference on Design & Architectures for Signal & Image Processing. Cagliari: European Electronic Chips & Systems design Initiative, 2013, pp. 355-356. ISBN 979-10-92279-01-6.
Publication language:english
Original title:Framework for Fast Prototyping of Applications running on Reconfigurable Systems on Chip
Title (cs):Framework pro rychlé prototypování aplikací běžících v rekonfigurovatelných architekturách System-on-Chip
Pages:355-356
Proceedings:Proceedings of the 2013 Conference on Design & Architectures for Signal & Image Processing
Conference:Conference on Design and Architectures for Signal and Image Processing
Place:Cagliari, IT
Year:2013
ISBN:979-10-92279-01-6
Publisher:European Electronic Chips & Systems design Initiative
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Keywords
FPGA, ARM, SoC, framework, Linux
Annotation
Recently introduced chips with ARM based processors and programmable logic provide huge potential for digital signal processing, networking and other applications. Many IP cores and operating systems have been prepared for these chips to simplify the development process. Nevertheless, the integration of IP cores and operating system is not covered by any development tool yet. Developers have to design, implement and debug the communication between hardware and software part of the application. Therefore we propose Reconfigurable System on Chip (RSoC) Framework to support rapid prototyping of applications running on FPGA chips with a processor. The framework consists of FPGA logic and OS drivers to support communication between application core in the FPGA and application software on the host processor. Moreover, the framework allows to configure automatically address space of components in the FPGA and supports dynamic loading of drivers according to the FPGA configuration. The developer can focus only on the application software and accelerating core. For demonstration purposes, the framework is exploited in the example of a video processing application, where an image filter is running in the software and than is accelerated in the FPGA.
BibTeX:
@INPROCEEDINGS{
   author = {Jan Viktorin and Pavol Kor{\v{c}}ek and Vlastimil
	Ko{\v{s}}a{\v{r}} and Jan Ko{\v{r}}enek},
   title = {Framework for Fast Prototyping of Applications running on
	Reconfigurable Systems on Chip},
   pages = {355--356},
   booktitle = {Proceedings of the 2013 Conference on Design \&
	Architectures for Signal \& Image Processing},
   year = {2013},
   location = {Cagliari, IT},
   publisher = {European Electronic Chips \& Systems design Initiative},
   ISBN = {979-10-92279-01-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=10393}
}

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