Ing. Jan Kořenek, Ph.D.

KOŘENEK Jan and PUŠ Viktor. Memory Optimization for Packet Classification Algorithms in FPGA. In: Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vídeň: IEEE Computer Society, 2010, pp. 297-300. ISBN 978-1-4244-6610-8.
Publication language:english
Original title:Memory Optimization for Packet Classification Algorithms in FPGA
Title (cs):Paměťová optimalizace algoritmů klasifikace paketů v FPGA
Pages:297-300
Proceedings:Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference:IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2010
Place:Vídeň, AT
Year:2010
ISBN:978-1-4244-6610-8
Publisher:IEEE Computer Society
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Keywords
packet classification, sram, fpga, tcam
Annotation
Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.
Abstract
Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.
BibTeX:
@INPROCEEDINGS{
   author = {Jan Ko{\v{r}}enek and Viktor Pu{\v{s}}},
   title = {Memory Optimization for Packet Classification Algorithms in
	FPGA},
   pages = {297--300},
   booktitle = {Proceedings of the 13th IEEE Symposium on Design and
	Diagnostics of Electronic Circuits and Systems},
   year = {2010},
   location = {V{\'{i}}de{\v{n}}, AT},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-6610-8},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9198}
}

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