Doc. Ing. Zdeněk Kotásek, CSc.
Methods of polymorphic digital circuit design |
| Reseach leader: | Sekanina Lukáš |
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| Team leaders: | Bidlo Michal, Drábek Vladimír, Gajda Zbyšek, Kotásek Zdeněk, Musil Vladislav, Prokop Roman, Růžička Richard, Stareček Lukáš, Vašíček Zdeněk |
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| Agency: | GAČR |
| Code: | GA102/06/0599 |
| Start: | 2006 |
| End: | 2008 |
| Keywords: | computer science; digital circuit design; evolutionary algorithm |
| Annotation: |
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| This is a multidisciplinary project of artificial intelligence and microelectronics in a new area of research called polymorphic electronics. Polymorphic circuits are circuits that are able to implement various useful functions in various environments (e.g. to implement addition at a given temperature and multiplication at another temperature). However, no functional switch is used; they are multifunctional in principle. The objective of this project is to propose methods for routine designing of nontrivial polymorphic digital circuits and to utilize polymorphic circuits in real-world applications whose implementation is impossible or difficult by means of conventional methods. Polymorphic gates will be considered as basic building blocks for implementation of polymorphic circuits. New evolutionary-based design methods will be developed operating at the polymorphic gate level. We will design and implement an integrated circuit consisting of polymorphic gates. This project was formulated on the basis of our long-term experience in evolutionary electronics and digital circuit design. |
Products
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Publications
| 2009 | Gajda Zbyšek, Sekanina Lukáš: Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming, In: Proc. of 2009 IEEE Congress on Evolutionary Computation, NA, US, IEEE CIS, 2009, p. 1599-1604, ISBN 978-1-4244-2958-5 |
| | Sekanina Lukáš, Růžička Richard, Vašíček Zdeněk, Prokop Roman, Fujcik Lukáš: REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware, In: Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware, Nashville, US, IEEE CIS, 2009, p. 39-46, ISBN 978-1-4244-2755-0 |
| | Sekanina Lukáš, Vašíček Zdeněk, Růžička Richard, Bidlo Michal, Jaroš Jiří, Švenda Petr: Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům, Praha, CZ, Academia, 2009, p. 328, ISBN 978-80-200-1729-1 |
| 2008 | Bidlo Michal, Vašíček Zdeněk: Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2008, p. 106-117, ISBN 978-3-540-85856-0 |
| | Gajda Zbyšek: Návrh polymorfních obvodů, In: Počítačové architektury a diagnostika 2008, Liberec, CZ, TUL, 2008, p. 17-23, ISBN 978-80-7372-378-1 |
| | Gajda Zbyšek: Polymorphic Circuit Design, MEMICS 2008 - Fourth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2008, p. 256-256, ISBN 978-80-7355-082-0 |
| | Růžička Richard, Prokop Roman: Bifunctional NAND/NOR Gates as Building Blocks for Polytronics, In: Proceedings of CSE 2008, Stará Lesná, SK, TU v Košiciach, 2008, p. 200-207, ISBN 978-80-8086-092-9 |
| | Růžička Richard, Sekanina Lukáš, Prokop Roman: Physical Demonstration of Polymorphic Self-checking Circuits, In: Proc. of the 14th IEEE Int. On-Line Testing Symposium, Los Alamitos, US, IEEE CS, 2008, p. 31-36, ISBN 978-0-7695-3264-6 |
| | Růžička Richard: On Bifunctional Polymorphic Gates Controlled by a Special Signal, In: WSEAS Transactions on Circuits, Vol. 7, No. 3, 2008, Athens, GR, p. 96-101, ISSN 1109-2734 |
| | Sekanina Lukáš, Mikušek Petr: Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures, In: Applications of Evolutionary Computing, Berlin, DE, Springer, 2008, p. 144-153, ISBN 978-3-540-78760-0 |
| | Sekanina Lukáš, Stareček Lukáš, Kotásek Zdeněk, Gajda Zbyšek: Polymorphic Gates in Design and Test of Digital Circuits, In: International Journal of Unconventional Computing, Vol. 4, No. 2, 2008, Philadelphia, US, p. 125-142, ISSN 1548-7199 |
| | Stareček Lukáš, Sekanina Lukáš, Kotásek Zdeněk: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration, In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Bratislava, SK, IEEE CS, 2008, p. 255-258, ISBN 978-1-4244-2276-0 |
| | Vašíček Zdeněk, Čapka Ladislav, Sekanina Lukáš: Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit, In: Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2008, p. 3-10, ISBN 978-0-7695-3166-3 |
| | Žaloudek Luděk, Sekanina Lukáš: Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2008, p. 320-331, ISBN 978-3-540-85856-0 |
| 2007 | Bidlo Michal: Evolutionary Development of Generic Multipliers: Initial Results, In: Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2007, p. 405-412, ISBN 0-7695-2866-X |
| | Bryan Luděk, Fučík Otto, Drábek Vladimír: HW-Based Object Detection Method for Traffic Monitoring, In: 6th Electronic Circuits and Systems Conference (ECS 2007), Bratislava, SK, FEI STUBA, 2007, p. 93-96, ISBN 978-80-227-2697-9 |
| | Drábek Vladimír: Hardware Unit for Motion Estimation, In: Electronic Devices and Systems, Brno, CZ, FEKT VUT, 2007, p. 17-21, ISBN 978-80-214-3470-7 |
| | Drábek Vladimír: The Evolution of Graphical Processors, In: 6th Electronic Circuits and Systems Conference (ECS 2007), Bratislava, SK, FIIT STU, 2007, p. 97-102, ISBN 978-80-227-2697-9 |
| | Gajda Zbyšek, Sekanina Lukáš: Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design, In: 2007 Genetic and Evolutionary Computation Conference, New York, US, ACM, 2007, p. 245-252, ISBN 9781595936974 |
| | Gajda Zbyšek: Metody návrhu polymorfních obvodů, In: Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia, Plzeň, CZ, ZČU v Plzni, 2007, p. 19-25, ISBN 978-80-7043-605-9 |
| | Růžička Richard, Stareček Lukáš: Development of Building Blocks for Polymorphic Digital Circuits, In: Proceedings of the Work in Progress Session of 10th Euromicro DSD 2007, Linz, AT, JKUL, 2007, p. 33-34, ISBN 978-3-902457-16-5 |
| | Růžička Richard: New Polymorphic NAND/XOR Gate, In: Proceedings of 7th WSEAS International Conference on Applied Computer Science, Venice, IT, WSEAS, 2007, p. 192-196, ISBN 978-960-6766-15-2, ISSN 1790-5117 |
| | Sekanina Lukáš: Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates, In: 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Gliwice, PL, IEEE CS, 2007, p. 243-246, ISBN 1424411610 |
| | Sekanina Lukáš: Evolution of Polymorphic Self-Checking Circuits, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2007, p. 186-197, ISBN 978-3-540-74625-6 |
| | Sekanina Lukáš: Evolutionary Functional Recovery in Virtual Reconfigurable Circuits, In: ACM Journal on Emerging Technologies in Computing Systems, Vol. 3, No. 2, 2007, US, p. 1-22, ISSN 1550-4832 |
| | Sekanina Lukáš: Evolvable hardware: Tutorial, In: 2007 Genetic and Evolutionary Computational Conference, New York, US, ACM, 2007, p. 3627-3644, ISBN 9781595936981 |
| | Stareček Lukáš, Sekanina Lukáš, Gajda Zbyšek, Kotásek Zdeněk, Prokop Roman, Musil Vladislav: On Properties and Utilization of Some Polymorphic Gates, In: 6th Electronic Circuits and Systems Conference (ECS 2007), Bratislava, SK, FIIT STU, 2007, p. 77-81, ISBN 978-80-227-2697-9 |
| | Stareček Lukáš: Polymorfní hradla pro optimalizaci testu obvodu, In: Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia, Plzeň, CZ, ZČU v Plzni, 2007, p. 41-46, ISBN 978-80-7043-605-9 |
| 2006 | Bidlo Michal, Bidlo Radek, Sekanina Lukáš: Designing a Novel General Sorting Network Constructor Using Artificial Evolution, In: TRANSACTIONS ON ENGINEERING, COMPUTING AND TECHNOLOGY, Vol. 15, No. 10, 2006, Barcelona, ES, p. 85-90, ISBN 975-00803-4-3, ISSN 1305-5313 |
| | Gajda Zbyšek: A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 238-240, ISBN 1424401844 |
| | Gajda Zbyšek: Návrh polymorfních obvodů, In: Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia, Bratislava, SK, UI SAV, 2006, p. 55-60, ISBN 80-969202-2-7 |
| | Očenášek Jiří, Cantú-Paz Erick, Pelikán Martin, Schwarz Josef: Design of Parallel Estimation of Distribution Algorithms, Scalable Optimization via Probabilistic Modeling, Berlin, DE, Springer, 2006, p. 187-201, ISBN 978-3-540-34953-2 |
| | Růžička Richard, Sekanina Lukáš: Evolutionary Circuit Design in REPOMO - Reconfigurable Polymorphic Module, In: Proceedings of the Second IASTED International Conference on Computational Intelligence, Anaheim, US, ACTA Press, 2006, p. 237-241, ISBN 0-88986-602-3 |
| | Sekanina Lukáš, Martínek Tomáš, Gajda Zbyšek: Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules, In: 2006 IEEE World Congress on Computational Intelligence, CA, US, IEEE CIS, 2006, p. 9676-9683, ISBN 0-7803-9489-5 |
| | Sekanina Lukáš, Stareček Lukáš, Gajda Zbyšek, Kotásek Zdeněk: Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage, In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, Piscataway, US, IEEE CS, 2006, p. 186-193, ISBN 0-7695-2614-4 |
| | Sekanina Lukáš, Stareček Lukáš, Kotásek Zdeněk: Novel Logic Circuits Controlled by Vdd, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 85-86, ISBN 1424401844 |
| | Sekanina Lukáš: Evolutionary Approach to the Implementation Problem, Brno, CZ, FIT VUT, 2006, p. 127 |
| | Sekanina Lukáš: On Dependability of FPGA-Based Evolvable Hardware Systems That Utilize Virtual Reconfigurable Circuits, In: Computing Frontiers 2006 Conference, New York, US, ACM, 2006, p. 221-228, ISBN 1595933026 |
| | Schwarz Josef, Hlavinka Michal, Zelinka Ivan, Kobliha Miloš: SODOMA: Self-Organizing Migrating Algorithm in Dynamic Environment, In: 12th International Conference on Soft Computing, Brno, CZ, FSI VUT, 2006, p. 163-169, ISBN 80-214-3195-4 |
| | Stareček Lukáš: Modelování polymorfních hradel a obvodů, In: Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia, Bratislava, SK, SAV, 2006, p. 67-72, ISBN 80-969202-2-7 |
| | Šimek Václav, Pokorný Petr: Communication of sensor modules, In: Proceedings of the 12th konference Student EEICT 2006, Brno, CZ, FEKT VUT, 2006, p. 56-58, ISBN 80-214-3161-X |
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Faculty of Information Technology
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