Doc. Ing. Zdeněk Kotásek, CSc.

Methods of polymorphic digital circuit design

Reseach leader:Sekanina Lukáš
Team leaders:Bidlo Michal, Drábek Vladimír, Gajda Zbyšek, Kotásek Zdeněk, Musil Vladislav (UMEL FEKT VUT), Prokop Roman (UMEL FEKT VUT), Růžička Richard, Stareček Lukáš, Vašíček Zdeněk
Agency:GAČR
Code:GA102/06/0599
Start:2006
End:2008
Keywords:

computer science; digital circuit design; evolutionary algorithm

Annotation:
This is a multidisciplinary project of artificial intelligence and microelectronics in a new area of research called polymorphic electronics. Polymorphic circuits are circuits that are able to implement various useful functions in various environments (e.g. to implement addition at a given temperature and multiplication at another temperature). However, no functional switch is used; they are multifunctional in principle. The objective of this project is to propose methods for routine designing of nontrivial polymorphic digital circuits and to utilize polymorphic circuits in real-world applications whose implementation is impossible or difficult by means of conventional methods. Polymorphic gates will be considered as basic building blocks for implementation of polymorphic circuits. New evolutionary-based design methods will be developed operating at the polymorphic gate level. We will design and implement an integrated circuit consisting of polymorphic gates. This project was formulated on the basis of our long-term experience in evolutionary electronics and digital circuit design.

Products

2008REPOMO32 - Reconfigurable polymorphic integrated circuit, specimen, 2008
Authors: Sekanina Lukáš, Růžička Richard, Vašíček Zdeněk, Prokop Roman, Fujcik Lukáš

Publications

2009GAJDA Zbyšek and SEKANINA Lukáš. Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming. In: Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009, pp. 1599-1604. ISBN 978-1-4244-2958-5.
 SEKANINA Lukáš, RŮŽIČKA Richard, VAŠÍČEK Zdeněk, PROKOP Roman and FUJCIK Lukáš. REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. In: Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware. Nashville: IEEE Computational Intelligence Society, 2009, pp. 39-46. ISBN 978-1-4244-2755-0.
 SEKANINA Lukáš, VAŠÍČEK Zdeněk, RŮŽIČKA Richard, BIDLO Michal, JAROŠ Jiří and ŠVENDA Petr. Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Praha: Academia, 2009. ISBN 978-80-200-1729-1.
2008BIDLO Michal and VAŠÍČEK Zdeněk. Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. In: Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2008, pp. 106-117. ISBN 978-3-540-85856-0.
 GAJDA Zbyšek. Polymorphic Circuit Design. MEMICS 2008 - Fourth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2008. ISBN 978-80-7355-082-0.
 GAJDA Zbyšek. Návrh polymorfních obvodů. In: Počítačové architektury a diagnostika 2008. Liberec: Liberec University of Technology, 2008, pp. 17-23. ISBN 978-80-7372-378-1.
 RŮŽIČKA Richard and PROKOP Roman. Bifunctional NAND/NOR Gates as Building Blocks for Polytronics. In: Proceedings of CSE 2008. Stará Lesná: The University of Technology Košice, 2008, pp. 200-207. ISBN 978-80-8086-092-9.
 RŮŽIČKA Richard, SEKANINA Lukáš and PROKOP Roman. Physical Demonstration of Polymorphic Self-checking Circuits. In: Proc. of the 14th IEEE Int. On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2008, pp. 31-36. ISBN 978-0-7695-3264-6.
 RŮŽIČKA Richard. On Bifunctional Polymorphic Gates Controlled by a Special Signal. WSEAS Transactions on Circuits. Athens: World Scientific and Engineering Academy, 2008, vol. 7, no. 3, pp. 96-101. ISSN 1109-2734.
 SEKANINA Lukáš and MIKUŠEK Petr. Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. In: Applications of Evolutionary Computing. Berlin: Springer Verlag, 2008, pp. 144-153. ISBN 978-3-540-78760-0.
 SEKANINA Lukáš, STAREČEK Lukáš, KOTÁSEK Zdeněk and GAJDA Zbyšek. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing. Philadelphia: Old City Publishing, Inc., 2008, vol. 4, no. 2, pp. 125-142. ISSN 1548-7199.
 STAREČEK Lukáš, SEKANINA Lukáš and KOTÁSEK Zdeněk. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008, pp. 255-258. ISBN 978-1-4244-2276-0.
 VAŠÍČEK Zdeněk, ČAPKA Ladislav and SEKANINA Lukáš. Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. In: Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2008, pp. 3-10. ISBN 978-0-7695-3166-3.
 ŽALOUDEK Luděk and SEKANINA Lukáš. Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator. In: Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2008, pp. 320-331. ISBN 978-3-540-85856-0.
2007BIDLO Michal. Evolutionary Development of Generic Multipliers: Initial Results. In: Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2007, pp. 405-412. ISBN 0-7695-2866-X.
 BRYAN Luděk, FUČÍK Otto and DRÁBEK Vladimír. HW-Based Object Detection Method for Traffic Monitoring. In: 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava, 2007, pp. 93-96. ISBN 978-80-227-2697-9.
 DRÁBEK Vladimír. Hardware Unit for Motion Estimation. In: Electronic Devices and Systems. Brno: Faculty of Electrical Engineering and Communication BUT, 2007, pp. 17-21. ISBN 978-80-214-3470-7.
 DRÁBEK Vladimír. The Evolution of Graphical Processors. In: 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology STU, 2007, pp. 97-102. ISBN 978-80-227-2697-9.
 GAJDA Zbyšek and SEKANINA Lukáš. Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design. In: 2007 Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2007, pp. 245-252. ISBN 9781595936974.
 GAJDA Zbyšek. Metody návrhu polymorfních obvodů. In: Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia. Plzeň: University of West Bohemia in Pilsen, 2007, pp. 19-25. ISBN 978-80-7043-605-9.
 RŮŽIČKA Richard and STAREČEK Lukáš. Development of Building Blocks for Polymorphic Digital Circuits. In: Proceedings of the Work in Progress Session of 10th Euromicro DSD 2007. Linz: Johannes Kepler University Linz, 2007, pp. 33-34. ISBN 978-3-902457-16-5.
 RŮŽIČKA Richard. New Polymorphic NAND/XOR Gate. In: Proceedings of 7th WSEAS International Conference on Applied Computer Science. Venice: World Scientific and Engineering Academy, 2007, pp. 192-196. ISBN 978-960-6766-15-2. ISSN 1790-5117.
 SEKANINA Lukáš. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. In: 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007, pp. 243-246. ISBN 1424411610.
 SEKANINA Lukáš. Evolution of Polymorphic Self-Checking Circuits. In: Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2007, pp. 186-197. ISBN 978-3-540-74625-6.
 SEKANINA Lukáš. Evolutionary Functional Recovery in Virtual Reconfigurable Circuits. ACM Journal on Emerging Technologies in Computing Systems. 2007, vol. 3, no. 2, pp. 1-22. ISSN 1550-4832.
 SEKANINA Lukáš. Evolvable hardware: Tutorial. In: 2007 Genetic and Evolutionary Computational Conference. New York: Association for Computing Machinery, 2007, pp. 3627-3644. ISBN 9781595936981.
 STAREČEK Lukáš, SEKANINA Lukáš, GAJDA Zbyšek, KOTÁSEK Zdeněk, PROKOP Roman and MUSIL Vladislav. On Properties and Utilization of Some Polymorphic Gates. In: 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology STU, 2007, pp. 77-81. ISBN 978-80-227-2697-9.
 STAREČEK Lukáš. Polymorfní hradla pro optimalizaci testu obvodu. In: Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia. Plzeň: University of West Bohemia in Pilsen, 2007, pp. 41-46. ISBN 978-80-7043-605-9.
2006BIDLO Michal, BIDLO Radek and SEKANINA Lukáš. Designing a Novel General Sorting Network Constructor Using Artificial Evolution. TRANSACTIONS ON ENGINEERING, COMPUTING AND TECHNOLOGY. Barcelona: World Enformatika Society, 2006, vol. 15, no. 10, pp. 85-90. ISBN 975-00803-4-3. ISSN 1305-5313.
 GAJDA Zbyšek. A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 238-240. ISBN 1424401844.
 GAJDA Zbyšek. Návrh polymorfních obvodů. In: Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Institute of Informatics, Slovak Academy of Sciences, 2006, pp. 55-60. ISBN 80-969202-2-7.
 OČENÁŠEK Jiří, CANTÚ-PAZ Erick, PELIKÁN Martin and SCHWARZ Josef. Design of Parallel Estimation of Distribution Algorithms. Scalable Optimization via Probabilistic Modeling. Berlin: Springer Verlag, 2006, pp. 187-201. ISBN 978-3-540-34953-2.
 RŮŽIČKA Richard and SEKANINA Lukáš. Evolutionary Circuit Design in REPOMO - Reconfigurable Polymorphic Module. In: Proceedings of the Second IASTED International Conference on Computational Intelligence. Anaheim: ACTA Press, 2006, pp. 237-241. ISBN 0-88986-602-3.
 SCHWARZ Josef, HLAVINKA Michal, ZELINKA Ivan and KOBLIHA Miloš. SODOMA: Self-Organizing Migrating Algorithm in Dynamic Environment. In: 12th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2006, pp. 163-169. ISBN 80-214-3195-4.
 SEKANINA Lukáš, MARTÍNEK Tomáš and GAJDA Zbyšek. Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. In: 2006 IEEE World Congress on Computational Intelligence. CA: IEEE Computational Intelligence Society, 2006, pp. 9676-9683. ISBN 0-7803-9489-5.
 SEKANINA Lukáš, STAREČEK Lukáš and KOTÁSEK Zdeněk. Novel Logic Circuits Controlled by Vdd. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 85-86. ISBN 1424401844.
 SEKANINA Lukáš, STAREČEK Lukáš, GAJDA Zbyšek and KOTÁSEK Zdeněk. Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006, pp. 186-193. ISBN 0-7695-2614-4.
 SEKANINA Lukáš. Evolutionary Approach to the Implementation Problem. Brno: Faculty of Information Technology BUT, 2006.
 SEKANINA Lukáš. On Dependability of FPGA-Based Evolvable Hardware Systems That Utilize Virtual Reconfigurable Circuits. In: Computing Frontiers 2006 Conference. New York: Association for Computing Machinery, 2006, pp. 221-228. ISBN 1595933026.
 STAREČEK Lukáš. Modelování polymorfních hradel a obvodů. In: Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia. Bratislava: Slovak Academy of Science, 2006, pp. 67-72. ISBN 80-969202-2-7.
 ŠIMEK Václav and POKORNÝ Petr. Communication of sensor modules. In: Proceedings of the 12th konference Student EEICT 2006. Brno: Faculty of Electrical Engineering and Communication BUT, 2006, pp. 56-58. ISBN 80-214-3161-X.

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