Doc. Ing. Zdeněk Kotásek, CSc.

Publikace

2019LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, s. 93-96. ISBN 978-1-72811-755-3.
 PODIVÍNSKÝ Jakub, LOJDA Jakub a KOTÁSEK Zdeněk. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, s. 97-100. ISBN 978-1-72811-755-3.
 SZURMAN Karel a KOTÁSEK Zdeněk. Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy, 2019.
 SZURMAN Karel a KOTÁSEK Zdeněk. Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, s. 32-35. ISBN 978-1-72811-755-3.
 SZURMAN Karel a KOTÁSEK Zdeněk. Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430. In: 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). Cluj-Napoca: IEEE Computer Society, 2019, s. 136-140. ISBN 978-1-72810-072-2.
2018LOJDA Jakub a KOTÁSEK Zdeněk. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. In: Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018, s. 5-8. ISBN 978-80-261-0814-6.
 LOJDA Jakub a KOTÁSEK Zdeněk. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2018, s. 31-32. ISBN 978-80-01-06456-6.
 LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, s. 80-86. ISBN 978-1-5386-5709-6.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk a KRČMA Martin. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In: 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018, s. 1-4. ISBN 978-1-5386-7311-9.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, PÁNEK Richard a KOTÁSEK Zdeněk. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, s. 244-251. ISBN 978-1-5386-7376-8.
 PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: České vysoké učení technické, 2018, s. 33-34. ISBN 978-80-01-06456-6.
 PODIVÍNSKÝ Jakub, LOJDA Jakub a KOTÁSEK Zdeněk. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, s. 63-69. ISBN 978-1-5386-5709-6.
 PODIVÍNSKÝ Jakub, LOJDA Jakub a KOTÁSEK Zdeněk. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, s. 9-12.
 PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej a KOTÁSEK Zdeněk. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, s. 229-236. ISBN 978-1-5386-7376-8.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin, BURGET Radek, HRUŠKA Tomáš a KOTÁSEK Zdeněk. A Processor Optimization Framework for a Selected Application. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, s. 564-574. ISBN 978-1-5386-5709-6.
 PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018, s. 129-134. ISBN 978-1-5386-5709-6.
 ČEKAN Ondřej a KOTÁSEK Zdeněk. Random Test Generation Through a Probabilistic Constrained Grammar. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, s. 5-8.
 ČEKAN Ondřej, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Program Generation Through a Probabilistic Constrained Grammar. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, s. 214-220. ISBN 978-1-5386-7376-8.
 ČEKAN Ondřej, PÁNEK Richard a KOTÁSEK Zdeněk. Input and Output Generation for the Verification of ALU: a Use Case. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, s. 331-336. ISBN 978-1-5386-5709-6.
2017KRČMA Martin a KOTÁSEK Zdeněk. Approximation accuracy of different FPNN types. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 81-82. ISBN 978-80-01-06178-7.
 KRČMA Martin, KOTÁSEK Zdeněk a LOJDA Jakub. Comparison of FPNNs Models Approximation Capabilities and FPGA Resources Utilization. In: Proceedings of IEEE 13th International Conference on Intelligent Computer Communication and Processing. Cluj-Nappoca: IEEE Computer Society, 2017, s. 125-132. ISBN 978-1-5386-3367-0.
 KRČMA Martin, LOJDA Jakub a KOTÁSEK Zdeněk. Triple Modular Redundancy Used in Field Programmable Neural Networks. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, s. 1-6. ISBN 978-1-5386-3298-7.
 LOJDA Jakub a KOTÁSEK Zdeněk. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 79-80. ISBN 978-80-01-06178-7.
 LOJDA Jakub a KOTÁSEK Zdeněk. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017, s. 59-62. ISBN 978-80-972784-0-3.
 LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, s. 359-364. ISBN 978-1-5386-3298-7.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk a KRČMA Martin. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, s. 273-278. ISBN 978-1-5386-3298-7.
 PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 81-82. ISBN 978-80-01-06178-7.
 PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej, PÁNEK Richard a KOTÁSEK Zdeněk. Reliability Analysis and Improvement of FPGA-based Robot Controller. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017, s. 337-344. ISBN 978-1-5386-2146-2.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub, ZACHARIÁŠOVÁ Marcela, KRČMA Martin a KOTÁSEK Zdeněk. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2017, roč. 52, č. 5, s. 145-159. ISSN 0141-9331.
 SZURMAN Karel a KOTÁSEK Zdeněk. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. In: Počítačové architektúry & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017, s. 51-54. ISBN 978-80-972784-0-3.
 ČEKAN Ondřej a KOTÁSEK Zdeněk. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In: Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: Technische Universitaet Wien, 2017, s. 356-359. ISBN 978-1-5386-2146-2.
 ČEKAN Ondřej a KOTÁSEK Zdeněk. Random Test Stimuli Generation Based on a Probabilistic Grammar. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 43-44. ISBN 978-80-01-06178-7.
2016KOTÁSEK Zdeněk a PODIVÍNSKÝ Jakub. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
 KRČMA Martin a KOTÁSEK Zdeněk. Fault Tolerant Field Programmable Neural Networks. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
 KRČMA Martin, KOTÁSEK Zdeněk, LOJDA Jakub a KAŠTIL Jan. Comparison of FPNNs Approximation Capabilities. In: Proceedings of the Work in progress Session held in connection with DSD 2016. Limassol: Johannes Kepler University Linz, 2016, s. 1-2. ISBN 978-3-902457-46-2.
 LOJDA Jakub a KOTÁSEK Zdeněk. A Systematic Approach to the Description of Fault-tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, KRČMA Martin a KOTÁSEK Zdeněk. HLS-based Fault Tolerance Approach for SRAM-based FPGAs. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, s. 301-302. ISBN 978-1-5090-5602-6.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub a KOTÁSEK Zdeněk. Functional Verification as a Tool for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, s. 293-294. ISBN 978-1-5090-5602-6.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub a KOTÁSEK Zdeněk. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. In: Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016, s. 487-494. ISBN 978-1-5090-2817-7.
 SZURMAN Karel, MIČULKA Lukáš a KOTÁSEK Zdeněk. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
 ZACHARIÁŠOVÁ Marcela, BELEŠOVÁ Michaela a KOTÁSEK Zdeněk. Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis. In: Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol Cyprus: IEEE Computer Society, 2016, s. 380-387. ISBN 978-1-5090-2816-0.
 ČEKAN Ondřej a KOTÁSEK Zdeněk. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016. ISBN 978-80-01-05984-5.
 ČEKAN Ondřej, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Random Stimuli Generation Based on a Stochastic Context-Free Grammar. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, s. 295-296. ISBN 978-1-5090-5602-6.
2015KEKELYOVÁ Michaela, ZACHARIÁŠOVÁ Marcela, KOTÁSEK Zdeněk a HRUŠKA Tomáš. Application of Evolutionary Algorithms for Optimization of Regression Suites. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, s. 91-94. ISBN 978-1-4799-6779-7.
 KRČMA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Mapping trained neural networks to FPNNs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, s. 157-160. ISBN 978-1-4799-6779-7.
 KRČMA Martin, KOTÁSEK Zdeněk a KAŠTIL Jan. Fault Tolerant Field Programmable Neural Networks. In: 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015, s. 1-4. ISBN 978-1-4673-6575-8.
 PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, s. 13-16.
 PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela, ČEKAN Ondřej a KOTÁSEK Zdeněk. FPGA Prototyping and Accelerated Verification of ASIPs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, s. 145-148. ISBN 978-1-4799-6779-7.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2015, roč. 39, č. 8, s. 1215-1230. ISSN 0141-9331.
 ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Automation and Optimization of Coverage-driven Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, s. 87-94. ISBN 978-1-4673-8035-5.
 ČEKAN Ondřej, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Software Fault Tolerance: the Evaluation by Functional Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, s. 284-287. ISBN 978-1-4673-8035-5.
 ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Universal Pseudo-random Generation of Assembler Codes for Processors. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, s. 70-73.
2014KOTÁSEK Zdeněk a MIČULKA Lukáš. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, s. 171-174. ISBN 978-0-7695-5074-9.
 MATUŠOVÁ Lucie, KAŠTIL Jan a KOTÁSEK Zdeněk. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, s. 326-332. ISBN 978-0-7695-5074-9.
 PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Complex Control System for Testing Fault-Tolerance Methodologies. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014, s. 24-27. ISBN 978-2-11-129175-1.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, s. 312-319. ISBN 978-1-4799-5793-4.
 SZURMAN Karel, MIČULKA Lukáš a KOTÁSEK Zdeněk. State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, s. 704-707. ISBN 978-0-7695-5074-9.
 SZURMAN Karel, MIČULKA Lukáš a KOTÁSEK Zdeněk. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. In: 9th IEEE International Conference on Computer Engineering and Systems. Káhira: IEEE Computer Society, 2014, s. 231-236. ISBN 978-1-4799-6593-9.
2013MIČULKA Lukáš a KOTÁSEK Zdeněk. Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA. In: The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2013). Avignon: Politecnico di Milano, 2013, s. 53-56. ISBN 978-2-11-129175-1.
 MIČULKA Lukáš, STRAKA Martin a KOTÁSEK Zdeněk. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. In: 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013, s. 227-234. ISBN 978-0-7695-5074-9.
 STRAKA Martin, KAŠTIL Jan, KOTÁSEK Zdeněk a MIČULKA Lukáš. Fault Tolerant System Design and SEU Injection Based Testing. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2013, roč. 2013, č. 37, s. 155-173. ISSN 0141-9331.
 SZURMAN Karel, KAŠTIL Jan, STRAKA Martin a KOTÁSEK Zdeněk. Fault Tolerant CAN Bus Control System Implemented into FPGA. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Karlovy Vary: IEEE Computer Society, 2013, s. 289-292. ISBN 978-1-4673-1185-4.
 ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana a KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013, s. 275-278. ISBN 978-1-4673-6133-0.
 ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana a KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013, s. 35-38. ISBN 978-2-11-129175-1.
 ZACHARIÁŠOVÁ Marcela, PŘIKRYL Zdeněk, HRUŠKA Tomáš a KOTÁSEK Zdeněk. Automated Functional Verification of Application Specific Instruction-set Processors. IFIP Advances in Information and Communication Technology. Heidelberg: Springer Verlag, 2013, roč. 4, č. 403, s. 128-138. ISSN 1868-4238.
2012BARTOŠ Pavel a KOTÁSEK Zdeněk. Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires. In: Proceedings of CSE 2012 International Scientific Conference on Computer Science and Engineering. Košice: Fakulta elektrotechniky a informatiky, Technická univerzita v Košiciach, 2012, s. 162-169. ISBN 978-80-8143-049-7.
 KAŠTIL Jan, STRAKA Martin a KOTÁSEK Zdeněk. Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, s. 1-4.
 KAŠTIL Jan, STRAKA Martin, MIČULKA Lukáš a KOTÁSEK Zdeněk. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, s. 250-257. ISBN 978-0-7695-4798-5.
 KOTÁSEK Zdeněk a ŠKARVADA Jaroslav. Low Power Testing. Design and Test Technology foír Dependable Systems-on-Chip. Hershey: IGI Global, 2012, s. 395-412. ISBN 978-1-60960-212-3.
 KOTÁSEK Zdeněk, BOUDA Jan, ČERNÁ Ivana, SEKANINA Lukáš, VOJNAR Tomáš a ANTOŠ David, ed. Mathematical and Engineering Methods in Computer Science, 7th International Doctoral Workshop, Revised Selected Papers. Berlin: Springer Verlag, 2012. ISBN 978-3-642-25928-9.
 MIČULKA Lukáš a KOTÁSEK Zdeněk. Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, s. 20-21. ISBN 978-3-902457-33-2.
 STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. FPGA-based Fault Tolerant Architectures and Their Dependability Analysis. In: MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Fakulta informatiky MU, 2012, s. 1-1.
 STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems. In: CSE'2012 International Scientific Conference on Computer Science and Engineering. Košice: Technická univerzita v Košiciach, 2012, s. 146-153. ISBN 978-80-8143-049-7.
 STRAKA Martin, MIČULKA Lukáš, KAŠTIL Jan a KOTÁSEK Zdeněk. Test Platform for Fault Tolerant Systems Design Qualities Verification. In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012, s. 336-341. ISBN 978-1-4673-1185-4.
 ZACHARIÁŠOVÁ Marcela, KAŠTIL Jan a KOTÁSEK Zdeněk. Verification of Fault-tolerant Methodologies for FPGA Systems. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, s. 55-58.
2011BARTOŠ Pavel, KOTÁSEK Zdeněk a DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, s. 371-374. ISBN 978-1-4244-9753-9.
 STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. In: 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011, s. 223-230. ISBN 978-0-7695-4494-6.
 STRAKA Martin, KAŠTIL Jan, NOVOTNÝ Jaroslav a KOTÁSEK Zdeněk. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, s. 397-398. ISBN 978-1-4244-9753-9.
2010KOTÁSEK Zdeněk, BIDLO Michal a JAROŠ Jiří, ed. Počítačové architektury a diagnostika. Brno: Fakulta informačních technologií VUT v Brně, 2010. ISBN 978-80-214-4140-8.
 KOTÁSEK Zdeněk, ŠKARVADA Jaroslav a STRNADEL Josef. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, s. 364-369. ISBN 978-1-4244-6610-8.
 KOTÁSEK Zdeněk, ŠKARVADA Jaroslav a STRNADEL Josef. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010, s. 644-651. ISBN 978-0-7695-4171-6.
 STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. In: 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010, s. 365-372. ISBN 978-0-7695-4171-6.
 STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. In: NORCHIP 2010. Tampere: IEEE Computer Society, 2010, s. 1-4. ISBN 978-1-4244-8971-8.
 STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Methodology for Design of Highly Dependable Systems in FPGA. In: International Scientific Conference on Computer Science and Engineering. Košice: Technická univerzita v Košiciach, 2010, s. 186-193. ISBN 978-80-8086-164-3.
 STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010, s. 173-176. ISBN 978-1-4244-6610-8.
 ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a STRNADEL Josef. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Fakulta informačních technologií VUT v Brně, 2010. ISBN 978-80-214-4209-2.
 ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a STRNADEL Josef. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. In: Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2010, s. 181-192. ISBN 978-3-642-15322-8. ISSN 0302-9743.
2009KOTÁSEK Zdeněk a STRAKA Martin. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica. 2009, roč. 2009, č. 3, s. 8-15. ISSN 1335-8243.
 STRAKA Martin a KOTÁSEK Zdeněk. High Availability Fault Tolerant Architectures Implemented into FPGAs. In: 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009, s. 108-116. ISBN 978-0-7695-3782-5.
 STRAKA Martin a KOTÁSEK Zdeněk. Reliability Models for Fault Tolerant Architectures Based on FPGA. In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Fakulta informatiky MU, 2009, s. 239-239. ISBN 978-80-87342-04-6.
2008ANTOŠ David, ČEŠKA Milan, KOTÁSEK Zdeněk, KŘETÍNSKÝ Mojmír, MATYSKA Luděk a VOJNAR Tomáš, ed. Proceedings of 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Fakulta informatiky MU, 2008. ISBN 978-80-7355-082-0.
 PEČENKA Tomáš, SEKANINA Lukáš a KOTÁSEK Zdeněk. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM Transactions on Design Automation of Electronic Systems. 2008, roč. 13, č. 3, s. 1-21. ISSN 1084-4309.
 SEKANINA Lukáš, STAREČEK Lukáš, KOTÁSEK Zdeněk a GAJDA Zbyšek. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing. Philadelphia: Old City Publishing, Inc., 2008, roč. 4, č. 2, s. 125-142. ISSN 1548-7199.
 STAREČEK Lukáš, SEKANINA Lukáš a KOTÁSEK Zdeněk. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008, s. 255-258. ISBN 978-1-4244-2276-0.
 STRAKA Martin a KOTÁSEK Zdeněk. Design of FPGA-Based Dependable Systems. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masarykova universita, 2008, s. 240-247. ISBN 978-80-7355-082-0.
 STRAKA Martin, KOTÁSEK Zdeněk a WINTER Jan. Digital Systems Architectures Based on On-line Checkers. In: 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008, s. 81-87. ISBN 978-0-7695-3277-6.
 STRAKA Martin, KOTÁSEK Zdeněk a WINTER Jan. The Design of Hardware Checkers for Verification and Diagnostic Purposes. In: CSE'2008 International Scientific Conference on Computer Science and Engineering. High Tatras - Stará Lesná: Technická univerzita v Košiciach, 2008, s. 320-327. ISBN 978-80-8086-092-9.
 STRNADEL Josef, PEČENKA Tomáš a KOTÁSEK Zdeněk. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics. Bratislava: Slovak Academic Press, 2008, roč. 27, č. 6, s. 913-930. ISSN 1335-9150.
 ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a HERRMAN Tomáš. Power Conscious RTL Test Scheduling. In: Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008, s. 721-728. ISBN 978-0-7695-3277-6.
 ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a HERRMAN Tomáš. Power Conscious RTL Test Scheduling. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masarykova universita, 2008, s. 265-265. ISBN 978-80-7355-082-0.
 ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a HERRMAN Tomáš. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2008, roč. 32, č. 5, s. 296-302. ISSN 0141-9331.
2007KOTÁSEK Zdeněk a KUBEK Ján. Finite State Machine Localisation Based on IP Softcores Analysis. In: 6th Electronic Circuits and Systems Conference. Bratislava: Slovenská technická univerzita v Bratislavě, 2007, s. 137-142. ISBN 978-80-227-2697-9.
 STAREČEK Lukáš, SEKANINA Lukáš, GAJDA Zbyšek, KOTÁSEK Zdeněk, PROKOP Roman a MUSIL Vladislav. On Properties and Utilization of Some Polymorphic Gates. In: 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Fakulta informatiky a informačních technologií Slovenská technická univerzita v Bratislavě, 2007, s. 77-81. ISBN 978-80-227-2697-9.
 STRAKA Martin a KOTÁSEK Zdeněk. Checker for Communication Protocol between IP Cores Based on FPGA. In: 3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Fakulta informatiky MU, 2007, s. 193-200. ISBN 978-80-7355-077-6.
 STRAKA Martin, TOBOLA Jiří a KOTÁSEK Zdeněk. Checker Design for On-line Testing of Xilinx FPGA Communication. In: The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007, s. 152-160. ISBN 0-7695-2885-6.
 TOBOLA Jiří, KOTÁSEK Zdeněk, KOŘENEK Jan, MARTÍNEK Tomáš a STRAKA Martin. Online Protocol Testing for FPGA Based Fault Tolerant Systems. In: 10th EUROMICRO Conference on Digital System Design DSD 2007. Lubeck, Germany: IEEE Computer Society, 2007, s. 676-679. ISBN 0-7695-2978-X.
 ŠKARVADA Jaroslav, HERRMAN Tomáš a KOTÁSEK Zdeněk. RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool. In: IEEE 8th Workshop on RTL and High Level Testing. Beijing: Institute of Computing Technology, Chinese Academy of Sciences, 2007, s. 175-181.
 ŠKARVADA Jaroslav, HERRMAN Tomáš a KOTÁSEK Zdeněk. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. In: 10th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007). Lübeck: IEEE Computer Society, 2007, s. 611-618. ISBN 0-7695-2978-X.
2006KOTÁSEK Zdeněk a STRNADEL Josef. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, s. 497-498. ISBN 0-7695-2546-6.
 PEČENKA Tomáš a KOTÁSEK Zdeněk. I-path Scheduling Algorithm for RT Level Circuits. In: MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov, 2006, s. 174-181. ISBN 80-214-3287-X.
 PEČENKA Tomáš, KOTÁSEK Zdeněk a SEKANINA Lukáš. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, s. 285-289. ISBN 1424401844.
 PEČENKA Tomáš, STRNADEL Josef, KOTÁSEK Zdeněk a SEKANINA Lukáš. Testability Estimation Based on Controllability and Observability Parameters. In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). Cavtat: IEEE Computer Society, 2006, s. 504-514. ISBN 0-7695-2609-8.
 SEKANINA Lukáš, STAREČEK Lukáš a KOTÁSEK Zdeněk. Novel Logic Circuits Controlled by Vdd. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, s. 85-86. ISBN 1424401844.
 SEKANINA Lukáš, STAREČEK Lukáš, GAJDA Zbyšek a KOTÁSEK Zdeněk. Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006, s. 186-193. ISBN 0-7695-2614-4.
 ŠKARVADA Jaroslav a KOTÁSEK Zdeněk. Systém pro podporu vzdělávání v oblasti plánování testu vestavěných systémů. In: Pedagogický software 2006. České Budějovice: Scientifik Pedagogical Publishing, 2006, s. 319-321. ISBN 80-85645-56-4.
 ČERNÝ Stanislav, STRUŽKA Petr, KOŘENEK Jan, MARTÍNEK Tomáš a KOTÁSEK Zdeněk. FPGA Components in Simulink. In: Proceedings of XXVIIIth International Autumn Colloquium ASIS 2006. Ostrava: MARQ, 2006, s. 158-163. ISBN 80-86840-26-3.
2005DRÁBEK Vladimír a KOTÁSEK Zdeněk. Handbook of Testing Electronic Systems. Handbook of Testing Electronic Systems. Praha: Vydavatelství ČVUT, 2005, s. 235-243. ISBN 80-01-03318-X.
 KOTÁSEK Zdeněk a STRNADEL Josef a kol. Testing Tools for Training and Education. In: Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005, s. 671-676. ISBN 83-919289-9-3.
 KOTÁSEK Zdeněk, STRNADEL Josef a PEČENKA Tomáš. Methodology of Selecting Scan-Based Testability Improving Technique. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, s. 186-189. ISBN 963-9364-48-7.
 PEČENKA Tomáš, KOTÁSEK Zdeněk, SEKANINA Lukáš a STRNADEL Josef. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005, s. 51-58. ISBN 0-7695-2399-4.
 STRNADEL Josef a KOTÁSEK Zdeněk. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. In: Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005, s. 420-427. ISBN 0-7695-2433-8.
2004KOTÁSEK Zdeněk a TUPEC Pavel. New approach to the FPGA testing based on the Boundary Scan. In: Proceedings of 38th International Conference MOSIS'04. Ostrava: MARQ, 2004, s. 120-123. ISBN 80-85988-98-4.
 KOTÁSEK Zdeněk, MIKA Daniel a STRNADEL Josef. The Identification of Registers in RTL Structures. In: Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004. Nicosia: Department of Computer Science of University of Cyprus, 2004, s. 317-320. ISBN 3-540-41613.
 KOTÁSEK Zdeněk, PEČENKA Tomáš a STRNADEL Josef. Improving Testability Parameters of Pipelined Circuits Through the Identification of Testable Cores. In: Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovenská akademie věd, 2004, s. 99-104. ISBN 80-969117-9-1.
 KOTÁSEK Zdeněk, PEČENKA Tomáš, SEKANINA Lukáš a STRNADEL Josef. Evolutionary Design of Synthetic RTL Benchmark Circuits. In: Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004, s. 107-108. ISBN 000000000.
 KOTÁSEK Zdeněk, PEČENKA Tomáš, STRNADEL Josef, MIKA Daniel a SEKANINA Lukáš. An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking. In: Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: Technická univerzita v Košiciach, 2004, s. 229-234. ISBN 80-8073-150-0.
 KOTÁSEK Zdeněk. Partial Scan Methodologoies. In: Research and Training Action for System on Chip Design, 5th FP Project. Bratislava: Slovenská akademie věd, 2004, s. 77.
2003KOTÁSEK Zdeněk a URBIŠ Hynek. USB-to-IDE Adapter Design and Implementation. In: 6th International Workshopn on Electronics, Control, Measurment and Signals. Liberec: Technická univerzita v Liberci, 2003, s. 315-319. ISBN 80-7083-708-X.
 KOTÁSEK Zdeněk, MIKA Daniel a STRNADEL Josef. Methodologies of RTL Partial Scan Analysis and Their Comparison. In: Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznaň: Publishing House of Poznan University of Technology, 2003, s. 233-238. ISBN 83-7143-557-6.
 KOTÁSEK Zdeněk, MIKA Daniel a STRNADEL Josef. Test scheduling for embedded systems. In: Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society Press, 2003, s. 463-467. ISBN 0-7695-2003-0.
 KOTÁSEK Zdeněk, RŮŽIČKA Richard a SEKANINA Lukáš, ed. Sborník pracovního semináře "Počítačové architektury a diagnostika" pro studenty doktorského studia. Brno: Ústav počítačových systémů FIT VUT v Brně, 2003. ISBN 80-214-2471-0.
 KOTÁSEK Zdeněk, TUPEC Pavel a URBIŠ Hynek. Testing PCBs Based on Boundary Scan. In: Proceedings of International Carpathian Control Conference. Košice: Technická univerzita v Košiciach, 2003, s. 119-122. ISBN 80-7099-509-2.
 MIKA Daniel a KOTÁSEK Zdeněk. Feedback loops detection for RT circuit test application purposes based on an algebraic method. In: Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Fakulta elektrotechniky a informatiky, VŠB-TU Ostrava, 2003, s. 447-452. ISBN 0-08-044130-0.
 MIKA Daniel a KOTÁSEK Zdeněk. The Test Controller Model Based on The Timed Automaton. In: Proceedings of 37th International Conference MOSIS´03 Modelling and Simulation of Systems. Ostrava: MARQ, 2003, s. 107-114. ISBN 80-85988-86-0.
2002HLAVIČKA Jan, KOTÁSEK Zdeněk, MARINISSEN Erik Jan, NOVÁK Ondřej, RŮŽIČKA Richard a STRAUBE Bernd, ed. Proceedings of 5th International Workshop IEEE Design and Diagnostics of Electronic Circuits and Systems. Brno: Fakulta informačních technologií VUT v Brně, 2002. ISBN 80-214-2094-4.
 MIKA Daniel, KOTÁSEK Zdeněk a STRNADEL Josef. Test Controller Design Based on VHDL Source File Analysis. In: Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. Letná 42, 040 01 TU Košice: Technická univerzita v Košiciach, 2002, s. 135-141. ISBN 80-7099-879-2.
 STRNADEL Josef a KOTÁSEK Zdeněk. Normalized Testability Measures at RT Level: Utilization and Reasons for Creation. In: Proceedings of 36th International Conference MOSIS`02 Modeling and Simulation of Systems. Ostrava: MARQ, 2002, s. 297-304. ISBN 80-85988-71-2.
 STRNADEL Josef a KOTÁSEK Zdeněk. Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm. In: Proceedings of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Brno: Vysoké učení technické v Brně, 2002, s. 44-51. ISBN 80-214-2094-4.
 STRNADEL Josef a KOTÁSEK Zdeněk. Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. In: Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002. Los Alamitos: IEEE Computer Society Press, 2002, s. 166-173. ISBN 0-7695-1790-0.
 ZBOŘIL František V., KOTÁSEK Zdeněk, MIKA Daniel a STRNADEL Josef. The Identification of Feedback Loops in RTL Structures. In: Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Košice: Technická univerzita v Košiciach, 2002, s. 142-147. ISBN 80-7099-879-2.
2001HLAVIČKA Jan, KOTÁSEK Zdeněk, RŮŽIČKA Richard a STRNADEL Josef. Interactive Tool for Behavioral Level Testability Analysis. In: Proceedings of the IEEE ETW 2001. Stockholm, 2001, s. 117-119.
 KOTÁSEK Zdeněk a STRNADEL Josef. Analytic Approach to RTL Testability Analysis. In: Proceedings of 7th Conference Student FEI 2001. Brno: Vysoké učení technické v Brně, 2001, s. 363-367. ISBN 80-214-1860-5.
 KOTÁSEK Zdeněk a STRNADEL Josef. RTL Testability Analysis Based on Genetic Algorithm Implementation. In: Proceedings of the Tenth ICNACSA. Plovdiv: neznámá agentura, 2001, s. 1.
 KOTÁSEK Zdeněk a STRNADEL Josef. RTL Testability Analysis Based on Genetic Algorithm Implementation. In: Proceedings of the IWCIT'01. Ostrava: Fakulta elektrotechniky a informatiky, VŠB-TU Ostrava, 2001, s. 83-88. ISBN 80-7078-907-7.
 KOTÁSEK Zdeněk, RŮŽIČKA Richard a STRNADEL Josef. Formal and Analytical Approaches to the Testability Analysis - the Comparison. In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2001. Gyor: SZIF-UNIVERSITAS spol. s r. o.., Hungary, 2001, s. 123-128. ISBN 963-7175-16-4.
 KOTÁSEK Zdeněk, RŮŽIČKA Richard, STRNADEL Josef a ZBOŘIL František. Two Level Testability System. In: Proceedings of the 35th Spring International Conference MOSIS'01. Ostrava: MARQ, 2001, s. 433-440. ISBN 80-85988-57-7.
2000HLAVIČKA Jan, KOTÁSEK Zdeněk a RŮŽIČKA Richard. Formal Approach to RTL Testability Analysis. In: sborník konference IEEE LATW 2000. Rio de Janeiro: neznámá, 2000, s. 98-103.
 KOTÁSEK Zdeněk a RŮŽIČKA Richard. Behavioral Analysis for Testability on VHDL Source File. In: Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshopsborník konference IEEE DDECS. Bratislava: Slovenská akademie věd, 2000, s. 209-212. ISBN 80-968320-3.
 KOTÁSEK Zdeněk a RŮŽIČKA Richard. Partial Scan Methodologies - a Survey. In: sborník konference PDS2000. Ostrava: Elsevier Science, 2000, s. 133-137. ISBN 0-08-043620-X.
 KOTÁSEK Zdeněk a RŮŽIČKA Richard. Testability Analysis Based on Discrete Mathematics Concepts. In: Proc. of the 9-th International Colloquium on Numerical Analysis and Computer Science with Applications. Plovdiv: neznámá, 2000, s. 113.
 KOTÁSEK Zdeněk a RŮŽIČKA Richard. The Implementation of RTL Testability Analysis Algorithms trough the Discrete Mathematics Concepts. In: Proc. of the Fourth International Scientific Conference on Electronic Computers and Informatics. Košice-Herľany: neznámá, 2000, s. 177-182. ISBN 80-88922-25-9.

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