Doc. Ing. Zdeněk Kotásek, CSc.

2012Kaštil, J., Straka, M., Kotásek, Z.: Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration, In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12), Annecy, FR, Polimi, 2012, p. 1-4
 Kaštil, J., Straka, M., Mičulka, L., Kotásek, Z.: Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA, In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Cesme-Izmir, TR, IEEE CS, 2012, p. 1-8
 Kotásek, Z., Bouda, J., Černá, I., Sekanina, L., Vojnar, T., Antoš, D. (editors): Mathematical and Engineering Methods in Computer Science, 7th International Doctoral Workshop, Revised Selected Papers, Berlin, DE, Springer, 2012, p. 215, ISBN 978-3-642-25928-9
 Straka, M., Kaštil, J., Kotásek, Z., Mičulka, L.: Fault Tolerant System Design and SEU Injection based Testing, In: Microprocessors and Microsystems, Vol. 2012, No. 01, Amsterdam, NL, p. 16, ISSN 0141-9331
 Straka, M., Mičulka, L., Kaštil, J., Kotásek, Z.: Test Platform for Fault Tolerant Systems Design Qualities Verification, In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Tallin, EE, IEEE CS, 2012, p. 336-341, ISBN 978-1-4673-1185-4
2011Bartoš, P., Kotásek, Z., Dohnal, J.: Decreasing Test Time by Scan Chain Reorganization, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, p. 371-374, ISBN 978-1-4244-9753-9
 Straka, M., Kaštil, J., Kotásek, Z.: SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems, In: 14th EUROMICRO Conference on Digital System Design, Oulu, FI, IEEE CS, 2011, p. 223-230, ISBN 978-0-7695-4494-6
 Straka, M., Kaštil, J., Novotný, J., Kotásek, Z.: Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, p. 397-398, ISBN 978-1-4244-9753-9
2010Kotásek, Z., Bidlo, M., Jaroš, J. (editors): Počítačové architektury a diagnostika, Brno, CZ, FIT VUT, 2010, p. 183, ISBN 978-80-214-4140-8
 Kotásek, Z., Škarvada, J., Strnadel, J.: Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences, In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, p. 364-369, ISBN 978-1-4244-6610-8
 Kotásek, Z., Škarvada, J., Strnadel, J.: The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption, In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools, Los Alamitos, US, IEEE CS, 2010, p. 644-651, ISBN 978-0-7695-4171-6
 Straka, M., Kaštil, J., Kotásek, Z.: Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration, In: 13th EUROMICRO Conference on Digital System Design, DSD'2010, Lille, FR, IEEE CS, 2010, p. 365-372, ISBN 978-0-7695-4171-6
 Straka, M., Kaštil, J., Kotásek, Z.: Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA, In: NORCHIP 2010, Tampere, FI, IEEE CS, 2010, p. 1-4, ISBN 978-1-4244-8971-8
 Straka, M., Kaštil, J., Kotásek, Z.: Methodology for Design of Highly Dependable Systems in FPGA, In: International Scientific Conference on Computer Science and Engineering, Košice, SK, TU v Košiciach, 2010, p. 186-193, ISBN 978-80-8086-164-3
 Straka, M., Kaštil, J., Kotásek, Z.: Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs, In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010, Wien, AT, IEEE CS, 2010, p. 173-176, ISBN 978-1-4244-6610-8
 Škarvada, J., Kotásek, Z., Strnadel, J.: Optimalizace aplikace testu číslicových systémů pro nízký příkon, Brno, CZ, FIT VUT, 2010, p. 142, ISBN 978-80-214-4209-2
 Škarvada, J., Kotásek, Z., Strnadel, J.: The Use of Genetic Algorithm to Reduce Power Consumption during Test Application, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2010, p. 181-192, ISBN 978-3-642-15322-8
2009Kotásek, Z., Straka, M.: The Design of On-line Checkers and Their Use in Verification and Testing, In: Acta Electrotechnica et Informatica, Vol. 2009, No. 3, SK, p. 8-15, ISSN 1335-8243
 Straka, M., Kotásek, Z.: High Availability Fault Tolerant Architectures Implemented into FPGAs, In: 12th EUROMICRO Conference on Digital System Design DSD 2009, Patras, GR, IEEE CS, 2009, p. 108-116, ISBN 978-0-7695-3782-5
 Straka, M., Kotásek, Z.: Reliability Models for Fault Tolerant Architectures Based on FPGA, In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, FI MUNI, 2009, p. 239-239, ISBN 978-80-87342-04-6
2008Antoš, D., Češka, M., Kotásek, Z., Křetínský, M., Matyska, L., Vojnar, T. (editors): Proceedings of 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, FI MUNI, 2008, p. 286, ISBN 978-80-7355-082-0
 Pečenka, T., Sekanina, L., Kotásek, Z.: Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability, In: ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 3, 2008, US, p. 1-21, ISSN 1084-4309
 Sekanina, L., Stareček, L., Kotásek, Z., Gajda, Z.: Polymorphic Gates in Design and Test of Digital Circuits, In: International Journal of Unconventional Computing, Vol. 4, No. 2, 2008, Philadelphia, US, p. 125-142, ISSN 1548-7199
 Stareček, L., Sekanina, L., Kotásek, Z.: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration, In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Bratislava, SK, IEEE CS, 2008, p. 255-258, ISBN 978-1-4244-2276-0
 Straka, M., Kotásek, Z., Winter, J.: Digital Systems Architectures Based on On-line Checkers, In: 11th EUROMICRO Conference on Digital System Design DSD 2008, Parma, IT, IEEE CS, 2008, p. 81-87, ISBN 978-0-7695-3277-6
 Straka, M., Kotásek, Z., Winter, J.: The Design of Hardware Checkers for Verification and Diagnostic Purposes, In: CSE'2008 International Scientific Conference on Computer Science and Engineering, High Tatras - Stará Lesná, SK, TU v Košiciach, 2008, p. 320-327, ISBN 978-80-8086-092-9
 Straka, M., Kotásek, Z.: Design of FPGA-Based Dependable Systems, In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2008, p. 240-247, ISBN 978-80-7355-082-0
 Strnadel, J., Pečenka, T., Kotásek, Z.: Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits, In: Computing and Informatics, Vol. 27, No. 6, 2008, Bratislava, SK, p. 913-930, ISSN 1335-9150
 Škarvada, J., Kotásek, Z., Herrman, T.: Power Conscious RTL Test Scheduling, In: Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools, Los Alamitos, US, IEEE CS, 2008, p. 721-728, ISBN 978-0-7695-3277-6
 Škarvada, J., Kotásek, Z., Herrman, T.: Power Conscious RTL Test Scheduling, In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2008, p. 265-265, ISBN 978-80-7355-082-0
 Škarvada, J., Kotásek, Z., Herrman, T.: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties, In: Microprocessors and Microsystems, Vol. 32, No. 5, 2008, Amsterdam, NL, p. 296-302, ISSN 0141-9331
2007Kotásek, Z., Kubek, J.: Finite State Machine Localisation Based on IP Softcores Analysis, In: 6th Electronic Circuits and Systems Conference, Bratislava, SK, STUBA, 2007, p. 137-142, ISBN 978-80-227-2697-9
 Stareček, L., Sekanina, L., Gajda, Z., Kotásek, Z., Prokop, R., Musil, V.: On Properties and Utilization of Some Polymorphic Gates, In: 6th Electronic Circuits and Systems Conference (ECS 2007), Bratislava, SK, FIIT STU, 2007, p. 77-81, ISBN 978-80-227-2697-9
 Straka, M., Kotásek, Z.: Checker for Communication Protocol between IP Cores Based on FPGA, In: 3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, FI MUNI, 2007, p. 193-200, ISBN 978-80-7355-077-6
 Straka, M., Tobola, J., Kotásek, Z.: Checker Design for On-line Testing of Xilinx FPGA Communication, In: The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Rome, IT, IEEE CS, 2007, p. 152-160, ISBN 0-7695-2885-6
 Škarvada, J., Herrman, T., Kotásek, Z.: RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool, In: IEEE 8th Workshop on RTL and High Level Testing, Beijing, CN, ICTAC, 2007, p. 175-181
 Škarvada, J., Herrman, T., Kotásek, Z.: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties, In: 10th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007), Lübeck, DE, IEEE CS, 2007, p. 611-618, ISBN 0-7695-2978-X
 Tobola, J., Kotásek, Z., Kořenek, J., Martínek, T., Straka, M.: Online Protocol Testing for FPGA Based Fault Tolerant Systems, In: 10th EUROMICRO Conference on Digital System Design DSD 2007, Lubeck, Germany, DE, IEEE CS, 2007, p. 676-679, ISBN 0-7695-2978-X
2006Černý, S., Stružka, P., Kořenek, J., Martínek, T., Kotásek, Z.: FPGA Components in Simulink, In: Proceedings of XXVIIIth International Autumn Colloquium ASIS 2006, Ostrava, CZ, MARQ, 2006, p. 158-163, ISBN 80-86840-26-3
 Kotásek, Z., Strnadel, J.: SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System, In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS), Los Alamitos, CA, US, IEEE CS, 2006, p. 497-498, ISBN 0-7695-2546-6
 Pečenka, T., Kotásek, Z., Sekanina, L.: FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 285-289, ISBN 1424401844
 Pečenka, T., Kotásek, Z.: I-path Scheduling Algorithm for RT Level Circuits, In: MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Mikulov, CZ, 2006, p. 174-181, ISBN 80-214-3287-X
 Pečenka, T., Strnadel, J., Kotásek, Z., Sekanina, L.: Testability Estimation Based on Controllability and Observability Parameters, In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06), Cavtat, HR, IEEE CS, 2006, p. 504-514, ISBN 0-7695-2609-8
 Sekanina, L., Stareček, L., Gajda, Z., Kotásek, Z.: Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage, In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, Piscataway, US, IEEE CS, 2006, p. 186-193, ISBN 0-7695-2614-4
 Sekanina, L., Stareček, L., Kotásek, Z.: Novel Logic Circuits Controlled by Vdd, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 85-86, ISBN 1424401844
 Škarvada, J., Kotásek, Z.: Systém pro podporu vzdělávání v oblasti plánování testu vestavěných systémů, In: Pedagogický software 2006, České Budějovice, CZ, spp, 2006, p. 319-321, ISBN 80-85645-56-4
2005Drábek, V., Kotásek, Z.: Handbook of Testing Electronic Systems, Handbook of Testing Electronic Systems, Praha, CZ, VCVUT, 2005, p. 235-243, ISBN 80-01-03318-X
 Kotásek, Z., Strnadel, J. et al: Testing Tools for Training and Education, In: Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems, Krakow, PL, DMCS-TUL, 2005, p. 671-676, ISBN 83-919289-9-3
 Kotásek, Z., Strnadel, J., Pečenka, T.: Methodology of Selecting Scan-Based Testability Improving Technique, In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop, Sopron, HU, UWH, 2005, p. 186-189, ISBN 963-9364-48-7
 Pečenka, T., Kotásek, Z., Sekanina, L., Strnadel, J.: Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties, In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, 2005, p. 51-58, ISBN 0-7695-2399-4
 Strnadel, J., Kotásek, Z.: Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies, In: Proceedings of 8th Euromicro Conference on Digital System Design, Los Alamitos, US, IEEE CS, 2005, p. 420-427, ISBN 0-7695-2433-8
2004Kotásek, Z., Mika, D., Strnadel, J.: The Identification of Registers in RTL Structures, In: Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004, Nicosia, CY, DCS UC, 2004, p. 317-320, ISBN 3-540-41613
 Kotásek, Z., Pečenka, T., Sekanina, L., Strnadel, J.: Evolutionary Design of Synthetic RTL Benchmark Circuits, In: Informal Digest of Papers, IEEE European Test Workshop 2004, Montpellier, FR, IEEE CS, 2004, p. 107-108, ISBN 000000000
 Kotásek, Z., Pečenka, T., Strnadel, J., Mika, D., Sekanina, L.: An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking, In: Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004, Košice, SK, TU v Košiciach, 2004, p. 229-234, ISBN 80-8073-150-0
 Kotásek, Z., Pečenka, T., Strnadel, J.: Improving Testability Parameters of Pipelined Circuits Through the Identification of Testable Cores, In: Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, SK, SAV, 2004, p. 99-104, ISBN 80-969117-9-1
 Kotásek, Z., Tupec, P.: New approach to the FPGA testing based on the Boundary Scan, In: Proceedings of 38th International Conference MOSIS'04, Ostrava, CZ, MARQ, 2004, p. 120-123, ISBN 80-85988-98-4
 Kotásek, Z.: Survey of Partial Scan Methodologies, In: Research and Training Action for System on Chip Design, 5th FP Project, Bratislava, SK, SAV, 2004, p. 77
 Strnadel, J., Kotásek, Z.: System ScanEduTool, didactic instrument for education of scan technique principles, Brno, CZ, FIT VUT, 2004

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