Publication Details

Partial Scan Methodology in VHDL Environment

KOTÁSEK Zdeněk, RŮŽIČKA Richard and ZBOŘIL František. Partial Scan Methodology in VHDL Environment. In: CEI'99. Herľany: unknown, 1999, pp. 146-151. ISBN 80-88922-05-4.
Czech title
Metodologie parciálního skenování v prostředí VHDL
Type
conference paper
Language
english
Authors
Keywords

Partial Scan Methodoly, VHDL

Abstract

The paper presents a partial scan design methodology suited for pipelined data paths described at the Register Transfer Level. The presented methodology can be used for the selection of registers into the partial scan chain.

Annotation

The paper presents a partial scan design methodology suited for pipelined data paths described at the Register Transfer Level. It is based on the structure analysis of the circuit under design and the classification of circuit elements. This consists in selecting a set of registers: a) from which the inputs of other registers can be controlled, or b) in which the outputs of other registers can be observed. The methodology can be used for the selection of registers into the partial scan chain.

Published
1999
Pages
146-151
Proceedings
CEI'99
Conference
Computer Engineering and Informatics CE&I'99, Kosice - Herľany, SK
ISBN
80-88922-05-4
Place
Herľany, SK
BibTeX
@INPROCEEDINGS{FITPUB6608,
   author = "Zden\v{e}k Kot\'{a}sek and Richard R\r{u}\v{z}i\v{c}ka and Franti\v{s}ek Zbo\v{r}il",
   title = "Partial Scan Methodology in VHDL Environment",
   pages = "146--151",
   booktitle = "CEI'99",
   year = 1999,
   location = "Her\'{l}any, SK",
   ISBN = "80-88922-05-4",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6608"
}
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