'CIRCUIT' testability results | |||
Port name | Con. | Obs. | Tst. |
REG_10.q | 0.874095 | 0.898268 | 0.886182 |
REG_10.clk | 1.000000 | 0.000000 | 0.500000 |
REG_10.d | 0.964463 | 0.806006 | 0.885235 |
REG_9.q | 0.882107 | 0.903688 | 0.892897 |
REG_9.clk | 1.000000 | 0.000000 | 0.500000 |
REG_9.d | 0.973285 | 0.810891 | 0.892088 |
REG_8.q | 0.778049 | 1.000000 | 0.889025 |
REG_8.clk | 1.000000 | 0.000000 | 0.500000 |
REG_8.d | 0.858479 | 0.906385 | 0.882432 |
REG_7.q | 0.775662 | 0.994048 | 0.884855 |
REG_7.clk | 1.000000 | 0.000000 | 0.500000 |
REG_7.d | 0.855854 | 0.900974 | 0.878414 |
REG_6.q | 0.879474 | 0.997024 | 0.938249 |
REG_6.clk | 1.000000 | 0.000000 | 0.500000 |
REG_6.d | 0.970380 | 0.903680 | 0.937030 |
REG_5.q | 0.778049 | 0.997024 | 0.887536 |
REG_5.clk | 1.000000 | 0.000000 | 0.500000 |
REG_5.d | 0.858479 | 0.903680 | 0.881079 |
REG_4.q | 0.773347 | 0.991071 | 0.882209 |
REG_4.clk | 1.000000 | 0.000000 | 0.500000 |
REG_4.d | 0.853283 | 0.898268 | 0.875776 |
REG_3.q | 0.778106 | 0.991071 | 0.884589 |
REG_3.clk | 1.000000 | 0.000000 | 0.500000 |
REG_3.d | 0.858534 | 0.898268 | 0.878401 |
REG_2.q | 0.882107 | 1.000000 | 0.941054 |
REG_2.clk | 1.000000 | 0.000000 | 0.500000 |
REG_2.d | 0.973285 | 0.906385 | 0.939835 |
REG_1.q | 0.884740 | 1.000000 | 0.942370 |
REG_1.clk | 1.000000 | 0.000000 | 0.500000 |
REG_1.d | 0.976190 | 0.906385 | 0.941288 |
MUX2_5.q | 0.997024 | 0.997024 | 0.997024 |
MUX2_5.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_5.b | 1.000000 | 0.994048 | 0.997024 |
MUX2_5.a | 0.775726 | 0.994048 | 0.884887 |
MUX2_4.q | 0.997024 | 0.997024 | 0.997024 |
MUX2_4.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_4.b | 0.775662 | 0.994048 | 0.884855 |
MUX2_4.a | 1.000000 | 0.994048 | 0.997024 |
MUX2_3.q | 0.994048 | 1.000000 | 0.997024 |
MUX2_3.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_3.b | 0.778049 | 0.997024 | 0.887536 |
MUX2_3.a | 0.997024 | 0.997024 | 0.997024 |
MUX2_2.q | 0.775726 | 0.994048 | 0.884887 |
MUX2_2.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_2.b | 0.778106 | 0.991071 | 0.884589 |
MUX2_2.a | 0.773347 | 0.991071 | 0.882209 |
MUX2_1.q | 0.994048 | 1.000000 | 0.997024 |
MUX2_1.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_1.b | 0.997024 | 0.997024 | 0.997024 |
MUX2_1.a | 0.879474 | 0.997024 | 0.938249 |
ADD_5.q | 0.853283 | 0.898268 | 0.875776 |
ADD_5.b | 1.000000 | 0.766252 | 0.883126 |
ADD_5.a | 0.874095 | 0.898268 | 0.886182 |
ADD_4.q | 0.858534 | 0.898268 | 0.878401 |
ADD_4.b | 0.879474 | 0.876623 | 0.878049 |
ADD_4.a | 1.000000 | 0.790004 | 0.895002 |
ADD_3.q | 0.973285 | 0.810891 | 0.892088 |
ADD_3.b | 1.000000 | 0.789113 | 0.894557 |
ADD_3.a | 0.997024 | 0.810891 | 0.903957 |
ADD_2.q | 0.858479 | 0.906385 | 0.882432 |
ADD_2.b | 0.997024 | 0.780436 | 0.888730 |
ADD_2.a | 0.882107 | 0.903688 | 0.892897 |
ADD_1.q | 0.970380 | 0.903680 | 0.937030 |
ADD_1.b | 1.000000 | 0.876784 | 0.938392 |
ADD_1.a | 0.994048 | 0.903680 | 0.948864 |
SUB_5.q | 0.964463 | 0.806006 | 0.885235 |
SUB_5.b | 0.994048 | 0.781844 | 0.887946 |
SUB_5.a | 0.994048 | 0.801209 | 0.897628 |
SUB_4.q | 0.976190 | 0.906385 | 0.941288 |
SUB_4.b | 1.000000 | 0.884740 | 0.942370 |
SUB_4.a | 1.000000 | 0.906385 | 0.953193 |
SUB_3.q | 0.858479 | 0.903680 | 0.881079 |
SUB_3.b | 0.997024 | 0.778049 | 0.887536 |
SUB_3.a | 0.882107 | 0.900990 | 0.891549 |
SUB_2.q | 0.973285 | 0.906385 | 0.939835 |
SUB_2.b | 0.997024 | 0.884740 | 0.940882 |
SUB_2.a | 1.000000 | 0.903688 | 0.951844 |
SUB_1.q | 0.855854 | 0.900974 | 0.878414 |
SUB_1.b | 0.994048 | 0.775662 | 0.884855 |
SUB_1.a | 0.882107 | 0.895611 | 0.888859 |
CIRCUIT.CLK | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_5_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_4_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_3_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_2_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_1_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.pri_out_4 | 0.778049 | 1.000000 | 0.889025 |
CIRCUIT.pri_out_3 | 0.994048 | 1.000000 | 0.997024 |
CIRCUIT.pri_out_2 | 0.994048 | 1.000000 | 0.997024 |
CIRCUIT.pri_out_1 | 0.882107 | 1.000000 | 0.941054 |
CIRCUIT.pri_out_0 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_in_4 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_3 | 1.000000 | 0.884740 | 0.942370 |
CIRCUIT.pri_in_2 | 1.000000 | 0.994048 | 0.997024 |
CIRCUIT.pri_in_1 | 1.000000 | 0.994048 | 0.997024 |
CIRCUIT.pri_in_0 | 1.000000 | 0.903688 | 0.951844 |
Global measures | 0.968644 | 0.830214 | 0.804182 |
Arithmetic average | 0.937288 | 0.718543 | 0.827916 |
#Nodes(Total=621) | C(621/100.0%) | O(600/96.6%) | T(600/96.6%) |
This table was automatically generated by RTL-ADFT system Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz) Faculty of Information Technology Brno University of Technology Czech Republic |