'CIRCUIT' testability results | |||
Port name | Con. | Obs. | Tst. |
REG_10.q | 0.879474 | 0.900990 | 0.890232 |
REG_10.clk | 1.000000 | 0.000000 | 0.500000 |
REG_10.d | 0.970380 | 0.808471 | 0.889425 |
REG_9.q | 0.884740 | 1.000000 | 0.942370 |
REG_9.clk | 1.000000 | 0.000000 | 0.500000 |
REG_9.d | 0.976190 | 0.906385 | 0.941288 |
REG_8.q | 0.773347 | 1.000000 | 0.886673 |
REG_8.clk | 1.000000 | 0.000000 | 0.500000 |
REG_8.d | 0.853299 | 0.906385 | 0.879842 |
REG_7.q | 0.879474 | 0.997024 | 0.938249 |
REG_7.clk | 1.000000 | 0.000000 | 0.500000 |
REG_7.d | 0.970380 | 0.903680 | 0.937030 |
REG_6.q | 0.879474 | 0.997024 | 0.938249 |
REG_6.clk | 1.000000 | 0.000000 | 0.500000 |
REG_6.d | 0.970380 | 0.903680 | 0.937030 |
REG_5.q | 0.778106 | 0.997024 | 0.887565 |
REG_5.clk | 1.000000 | 0.000000 | 0.500000 |
REG_5.d | 0.858534 | 0.903680 | 0.881107 |
REG_4.q | 0.879474 | 0.997024 | 0.938249 |
REG_4.clk | 1.000000 | 0.000000 | 0.500000 |
REG_4.d | 0.970380 | 0.903680 | 0.937030 |
REG_3.q | 0.879474 | 0.994048 | 0.936761 |
REG_3.clk | 1.000000 | 0.000000 | 0.500000 |
REG_3.d | 0.970380 | 0.900974 | 0.935677 |
REG_2.q | 0.674897 | 0.994048 | 0.834472 |
REG_2.clk | 1.000000 | 0.000000 | 0.500000 |
REG_2.d | 0.752244 | 0.900974 | 0.826609 |
REG_1.q | 0.674897 | 0.994048 | 0.834472 |
REG_1.clk | 1.000000 | 0.000000 | 0.500000 |
REG_1.d | 0.752244 | 0.900974 | 0.826609 |
MUX2_5.q | 0.876784 | 1.000000 | 0.938392 |
MUX2_5.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_5.b | 0.879474 | 0.997024 | 0.938249 |
MUX2_5.a | 0.879474 | 0.997024 | 0.938249 |
MUX2_4.q | 0.994048 | 1.000000 | 0.997024 |
MUX2_4.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_4.b | 0.672775 | 0.997024 | 0.834899 |
MUX2_4.a | 0.997024 | 0.997024 | 0.997024 |
MUX2_3.q | 0.997024 | 0.997024 | 0.997024 |
MUX2_3.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_3.b | 1.000000 | 0.994048 | 0.997024 |
MUX2_3.a | 0.879474 | 0.994048 | 0.936761 |
MUX2_2.q | 0.672775 | 0.997024 | 0.834899 |
MUX2_2.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_2.b | 0.674897 | 0.994048 | 0.834472 |
MUX2_2.a | 0.674897 | 0.994048 | 0.834472 |
MUX2_1.q | 0.876784 | 1.000000 | 0.938392 |
MUX2_1.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_1.b | 0.879474 | 0.997024 | 0.938249 |
MUX2_1.a | 0.778106 | 0.997024 | 0.887565 |
ADD_5.q | 0.970380 | 0.903680 | 0.937030 |
ADD_5.b | 0.994048 | 0.882035 | 0.938041 |
ADD_5.a | 1.000000 | 0.898301 | 0.949150 |
ADD_4.q | 0.752244 | 0.900974 | 0.826609 |
ADD_4.b | 0.879474 | 0.770982 | 0.825228 |
ADD_4.a | 0.876784 | 0.792383 | 0.834584 |
ADD_3.q | 0.970380 | 0.903680 | 0.937030 |
ADD_3.b | 1.000000 | 0.876784 | 0.938392 |
ADD_3.a | 0.994048 | 0.903680 | 0.948864 |
ADD_2.q | 0.970380 | 0.808471 | 0.889425 |
ADD_2.b | 0.994048 | 0.789106 | 0.891577 |
ADD_2.a | 1.000000 | 0.803658 | 0.901829 |
ADD_1.q | 0.976190 | 0.906385 | 0.941288 |
ADD_1.b | 1.000000 | 0.884740 | 0.942370 |
ADD_1.a | 1.000000 | 0.906385 | 0.953193 |
SUB_5.q | 0.752244 | 0.900974 | 0.826609 |
SUB_5.b | 0.876784 | 0.773347 | 0.825066 |
SUB_5.a | 0.879474 | 0.789960 | 0.834717 |
SUB_4.q | 0.853299 | 0.906385 | 0.879842 |
SUB_4.b | 0.994048 | 0.778106 | 0.886077 |
SUB_4.a | 0.879474 | 0.900990 | 0.890232 |
SUB_3.q | 0.970380 | 0.900974 | 0.935677 |
SUB_3.b | 0.994048 | 0.879329 | 0.936688 |
SUB_3.a | 1.000000 | 0.895611 | 0.947806 |
SUB_2.q | 0.970380 | 0.903680 | 0.937030 |
SUB_2.b | 0.994048 | 0.882035 | 0.938041 |
SUB_2.a | 1.000000 | 0.898301 | 0.949150 |
SUB_1.q | 0.858534 | 0.903680 | 0.881107 |
SUB_1.b | 1.000000 | 0.775726 | 0.887863 |
SUB_1.a | 0.879474 | 0.903680 | 0.891577 |
CIRCUIT.CLK | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_5_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_4_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_3_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_2_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_1_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.pri_out_4 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_3 | 0.773347 | 1.000000 | 0.886673 |
CIRCUIT.pri_out_2 | 0.876784 | 1.000000 | 0.938392 |
CIRCUIT.pri_out_1 | 0.876784 | 1.000000 | 0.938392 |
CIRCUIT.pri_out_0 | 0.994048 | 1.000000 | 0.997024 |
CIRCUIT.pri_in_4 | 1.000000 | 0.898301 | 0.949150 |
CIRCUIT.pri_in_3 | 1.000000 | 0.994048 | 0.997024 |
CIRCUIT.pri_in_2 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_1 | 1.000000 | 0.884740 | 0.942370 |
CIRCUIT.pri_in_0 | 1.000000 | 0.898301 | 0.949150 |
Global measures | 0.961701 | 0.831664 | 0.799812 |
Arithmetic average | 0.923403 | 0.721545 | 0.822474 |
#Nodes(Total=621) | C(621/100.0%) | O(600/96.6%) | T(600/96.6%) |
This table was automatically generated by RTL-ADFT system Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz) Faculty of Information Technology Brno University of Technology Czech Republic |