'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8794740.9009900.890232
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9703800.8084710.889425
REG_9.q0.8847401.0000000.942370
REG_9.clk1.0000000.0000000.500000
REG_9.d0.9761900.9063850.941288
REG_8.q0.7733471.0000000.886673
REG_8.clk1.0000000.0000000.500000
REG_8.d0.8532990.9063850.879842
REG_7.q0.8794740.9970240.938249
REG_7.clk1.0000000.0000000.500000
REG_7.d0.9703800.9036800.937030
REG_6.q0.8794740.9970240.938249
REG_6.clk1.0000000.0000000.500000
REG_6.d0.9703800.9036800.937030
REG_5.q0.7781060.9970240.887565
REG_5.clk1.0000000.0000000.500000
REG_5.d0.8585340.9036800.881107
REG_4.q0.8794740.9970240.938249
REG_4.clk1.0000000.0000000.500000
REG_4.d0.9703800.9036800.937030
REG_3.q0.8794740.9940480.936761
REG_3.clk1.0000000.0000000.500000
REG_3.d0.9703800.9009740.935677
REG_2.q0.6748970.9940480.834472
REG_2.clk1.0000000.0000000.500000
REG_2.d0.7522440.9009740.826609
REG_1.q0.6748970.9940480.834472
REG_1.clk1.0000000.0000000.500000
REG_1.d0.7522440.9009740.826609
MUX2_5.q0.8767841.0000000.938392
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.8794740.9970240.938249
MUX2_5.a0.8794740.9970240.938249
MUX2_4.q0.9940481.0000000.997024
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.6727750.9970240.834899
MUX2_4.a0.9970240.9970240.997024
MUX2_3.q0.9970240.9970240.997024
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b1.0000000.9940480.997024
MUX2_3.a0.8794740.9940480.936761
MUX2_2.q0.6727750.9970240.834899
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.6748970.9940480.834472
MUX2_2.a0.6748970.9940480.834472
MUX2_1.q0.8767841.0000000.938392
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.8794740.9970240.938249
MUX2_1.a0.7781060.9970240.887565
ADD_5.q0.9703800.9036800.937030
ADD_5.b0.9940480.8820350.938041
ADD_5.a1.0000000.8983010.949150
ADD_4.q0.7522440.9009740.826609
ADD_4.b0.8794740.7709820.825228
ADD_4.a0.8767840.7923830.834584
ADD_3.q0.9703800.9036800.937030
ADD_3.b1.0000000.8767840.938392
ADD_3.a0.9940480.9036800.948864
ADD_2.q0.9703800.8084710.889425
ADD_2.b0.9940480.7891060.891577
ADD_2.a1.0000000.8036580.901829
ADD_1.q0.9761900.9063850.941288
ADD_1.b1.0000000.8847400.942370
ADD_1.a1.0000000.9063850.953193
SUB_5.q0.7522440.9009740.826609
SUB_5.b0.8767840.7733470.825066
SUB_5.a0.8794740.7899600.834717
SUB_4.q0.8532990.9063850.879842
SUB_4.b0.9940480.7781060.886077
SUB_4.a0.8794740.9009900.890232
SUB_3.q0.9703800.9009740.935677
SUB_3.b0.9940480.8793290.936688
SUB_3.a1.0000000.8956110.947806
SUB_2.q0.9703800.9036800.937030
SUB_2.b0.9940480.8820350.938041
SUB_2.a1.0000000.8983010.949150
SUB_1.q0.8585340.9036800.881107
SUB_1.b1.0000000.7757260.887863
SUB_1.a0.8794740.9036800.891577
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.8847401.0000000.942370
CIRCUIT.pri_out_30.7733471.0000000.886673
CIRCUIT.pri_out_20.8767841.0000000.938392
CIRCUIT.pri_out_10.8767841.0000000.938392
CIRCUIT.pri_out_00.9940481.0000000.997024
CIRCUIT.pri_in_41.0000000.8983010.949150
CIRCUIT.pri_in_31.0000000.9940480.997024
CIRCUIT.pri_in_21.0000000.9063850.953193
CIRCUIT.pri_in_11.0000000.8847400.942370
CIRCUIT.pri_in_01.0000000.8983010.949150
Global measures0.9617010.8316640.799812
Arithmetic average0.9234030.7215450.822474
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic