'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8714780.9063850.888932
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9615750.8133120.887443
REG_9.q0.8847401.0000000.942370
REG_9.clk1.0000000.0000000.500000
REG_9.d0.9761900.9063850.941288
REG_8.q0.8768410.9940480.935444
REG_8.clk1.0000000.0000000.500000
REG_8.d0.9674740.9009740.934224
REG_7.q0.6748970.9940480.834472
REG_7.clk1.0000000.0000000.500000
REG_7.d0.7522440.9009740.826609
REG_6.q0.6759040.9940480.834976
REG_6.clk1.0000000.0000000.500000
REG_6.d0.7457890.9009740.823382
REG_5.q0.8847400.9910710.937906
REG_5.clk1.0000000.0000000.500000
REG_5.d0.9761900.8982680.937229
REG_4.q0.8794740.9970240.938249
REG_4.clk1.0000000.0000000.500000
REG_4.d0.9703800.9036800.937030
REG_3.q0.8794740.9970240.938249
REG_3.clk1.0000000.0000000.500000
REG_3.d0.9703800.9036800.937030
REG_2.q0.8847401.0000000.942370
REG_2.clk1.0000000.0000000.500000
REG_2.d0.9761900.9063850.941288
REG_1.q0.7710321.0000000.885516
REG_1.clk1.0000000.0000000.500000
REG_1.d0.8507280.9063850.878557
MUX2_5.q0.9970240.9940480.995536
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.8847400.9910710.937906
MUX2_5.a1.0000000.9910710.995536
MUX2_4.q0.9940480.9970240.995536
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.8768410.9940480.935444
MUX2_4.a0.9970240.9940480.995536
MUX2_3.q0.8767841.0000000.938392
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.8794740.9970240.938249
MUX2_3.a0.8794740.9970240.938249
MUX2_2.q0.6738180.9970240.835421
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.6759040.9940480.834976
MUX2_2.a0.6748970.9940480.834472
MUX2_1.q0.9910711.0000000.995536
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.9940480.9970240.995536
MUX2_1.a0.6727750.9970240.834899
ADD_5.q0.9674740.9009740.934224
ADD_5.b0.9910710.8793290.935200
ADD_5.a1.0000000.8929300.946465
ADD_4.q0.9703800.9036800.937030
ADD_4.b1.0000000.8767840.938392
ADD_4.a0.9940480.9036800.948864
ADD_3.q0.7522440.9009740.826609
ADD_3.b0.8794740.7709820.825228
ADD_3.a0.8767840.7923830.834584
ADD_2.q0.9615750.8133120.887443
ADD_2.b0.9910710.7891060.890089
ADD_2.a0.9940480.8060500.900049
ADD_1.q0.7457890.9009740.823382
ADD_1.b0.9910710.6779900.834531
ADD_1.a0.7710320.8929300.831981
SUB_5.q0.9761900.8982680.937229
SUB_5.b1.0000000.8766230.938312
SUB_5.a1.0000000.8982680.949134
SUB_4.q0.9761900.9063850.941288
SUB_4.b1.0000000.8847400.942370
SUB_4.a1.0000000.9063850.953193
SUB_3.q0.8507280.9063850.878557
SUB_3.b1.0000000.7710320.885516
SUB_3.a0.8714780.9063850.888932
SUB_2.q0.9761900.9063850.941288
SUB_2.b1.0000000.8847400.942370
SUB_2.a1.0000000.9063850.953193
SUB_1.q0.9703800.9036800.937030
SUB_1.b0.9940480.8820350.938041
SUB_1.a1.0000000.8983010.949150
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.8847401.0000000.942370
CIRCUIT.pri_out_30.9910711.0000000.995536
CIRCUIT.pri_out_20.8767841.0000000.938392
CIRCUIT.pri_out_10.8847401.0000000.942370
CIRCUIT.pri_out_00.7710321.0000000.885516
CIRCUIT.pri_in_41.0000000.9910710.995536
CIRCUIT.pri_in_31.0000000.8847400.942370
CIRCUIT.pri_in_21.0000000.8847400.942370
CIRCUIT.pri_in_11.0000000.9063850.953193
CIRCUIT.pri_in_01.0000000.9063850.953193
Global measures0.9656670.8321290.803559
Arithmetic average0.9313340.7225060.826920
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic