'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8847400.9036800.894210
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9761900.8108770.893534
REG_9.q0.7827650.9970240.889895
REG_9.clk1.0000000.0000000.500000
REG_9.d0.8636750.9036800.883677
REG_8.q0.8821070.9940480.938077
REG_8.clk1.0000000.0000000.500000
REG_8.d0.9732850.9009740.937130
REG_7.q0.6042810.9970240.800653
REG_7.clk1.0000000.0000000.500000
REG_7.d0.6735350.9036800.788607
REG_6.q0.7827650.9970240.889895
REG_6.clk1.0000000.0000000.500000
REG_6.d0.8636750.9036800.883677
REG_5.q0.8847401.0000000.942370
REG_5.clk1.0000000.0000000.500000
REG_5.d0.9761900.9063850.941288
REG_4.q0.8847400.9970240.940882
REG_4.clk1.0000000.0000000.500000
REG_4.d0.9761900.9036800.939935
REG_3.q0.6042810.9970240.800653
REG_3.clk1.0000000.0000000.500000
REG_3.d0.6735350.9036800.788607
REG_2.q0.7779850.9970240.887504
REG_2.clk1.0000000.0000000.500000
REG_2.d0.8584090.9036800.881044
REG_1.q0.8847400.9970240.940882
REG_1.clk1.0000000.0000000.500000
REG_1.d0.9761900.9036800.939935
MUX2_5.q0.9940481.0000000.997024
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.9970240.9970240.997024
MUX2_5.a0.7827650.9970240.889895
MUX2_4.q0.9970240.9970240.997024
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b1.0000000.9940480.997024
MUX2_4.a0.8821070.9940480.938077
MUX2_3.q0.7803721.0000000.890186
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.6042810.9970240.800653
MUX2_3.a0.7827650.9970240.889895
MUX2_2.q0.8820351.0000000.941017
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.8847400.9970240.940882
MUX2_2.a0.6042810.9970240.800653
MUX2_1.q0.8820351.0000000.941017
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.7779850.9970240.887504
MUX2_1.a0.8847400.9970240.940882
ADD_5.q0.9761900.9036800.939935
ADD_5.b1.0000000.8820350.941017
ADD_5.a1.0000000.9036800.951840
ADD_4.q0.9761900.9063850.941288
ADD_4.b1.0000000.8847400.942370
ADD_4.a1.0000000.9063850.953193
ADD_3.q0.9732850.9009740.937130
ADD_3.b0.9970240.8793290.938176
ADD_3.a1.0000000.8982930.949146
ADD_2.q0.9761900.8108770.893534
ADD_2.b1.0000000.7913960.895698
ADD_2.a1.0000000.8108770.905438
ADD_1.q0.6735350.9036800.788607
ADD_1.b0.8847400.6883150.786527
ADD_1.a0.7803720.7995220.789947
SUB_5.q0.8636750.9036800.883677
SUB_5.b0.8847400.8820350.883387
SUB_5.a1.0000000.7995220.899761
SUB_4.q0.6735350.9036800.788607
SUB_4.b0.7803720.7803720.780372
SUB_4.a0.8847400.7052060.794973
SUB_3.q0.8636750.9036800.883677
SUB_3.b1.0000000.7803720.890186
SUB_3.a0.8847400.9036800.894210
SUB_2.q0.8584090.9036800.881044
SUB_2.b0.9970240.7779850.887504
SUB_2.a0.8820350.9009900.891512
SUB_1.q0.9761900.9036800.939935
SUB_1.b1.0000000.8820350.941017
SUB_1.a1.0000000.9036800.951840
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.7803721.0000000.890186
CIRCUIT.pri_out_30.7803721.0000000.890186
CIRCUIT.pri_out_20.8847401.0000000.942370
CIRCUIT.pri_out_10.8820351.0000000.941017
CIRCUIT.pri_out_00.8820351.0000000.941017
CIRCUIT.pri_in_41.0000000.8847400.942370
CIRCUIT.pri_in_31.0000000.9940480.997024
CIRCUIT.pri_in_21.0000000.9036800.951840
CIRCUIT.pri_in_11.0000000.9063850.953193
CIRCUIT.pri_in_01.0000000.8982930.949146
Global measures0.9558150.8306850.793981
Arithmetic average0.9116300.7195190.815574
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic