'CIRCUIT' testability results | |||
Port name | Con. | Obs. | Tst. |
REG_10.q | 0.680909 | 0.997024 | 0.838966 |
REG_10.clk | 1.000000 | 0.000000 | 0.500000 |
REG_10.d | 0.758945 | 0.903680 | 0.831312 |
REG_9.q | 0.780372 | 0.994048 | 0.887210 |
REG_9.clk | 1.000000 | 0.000000 | 0.500000 |
REG_9.d | 0.861034 | 0.900974 | 0.881004 |
REG_8.q | 0.775584 | 0.991071 | 0.883328 |
REG_8.clk | 1.000000 | 0.000000 | 0.500000 |
REG_8.d | 0.855751 | 0.898268 | 0.877010 |
REG_7.q | 0.884740 | 0.991071 | 0.937906 |
REG_7.clk | 1.000000 | 0.000000 | 0.500000 |
REG_7.d | 0.976190 | 0.898268 | 0.937229 |
REG_6.q | 0.884740 | 0.997024 | 0.940882 |
REG_6.clk | 1.000000 | 0.000000 | 0.500000 |
REG_6.d | 0.976190 | 0.903680 | 0.939935 |
REG_5.q | 0.680856 | 0.994048 | 0.837452 |
REG_5.clk | 1.000000 | 0.000000 | 0.500000 |
REG_5.d | 0.758893 | 0.900974 | 0.829934 |
REG_4.q | 0.780372 | 0.994048 | 0.887210 |
REG_4.clk | 1.000000 | 0.000000 | 0.500000 |
REG_4.d | 0.861034 | 0.900974 | 0.881004 |
REG_3.q | 0.884740 | 1.000000 | 0.942370 |
REG_3.clk | 1.000000 | 0.000000 | 0.500000 |
REG_3.d | 0.976190 | 0.906385 | 0.941288 |
REG_2.q | 0.884740 | 1.000000 | 0.942370 |
REG_2.clk | 1.000000 | 0.000000 | 0.500000 |
REG_2.d | 0.976190 | 0.906385 | 0.941288 |
REG_1.q | 0.884740 | 1.000000 | 0.942370 |
REG_1.clk | 1.000000 | 0.000000 | 0.500000 |
REG_1.d | 0.976190 | 0.906385 | 0.941288 |
MUX2_5.q | 0.876623 | 1.000000 | 0.938312 |
MUX2_5.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_5.b | 0.879329 | 0.997024 | 0.938176 |
MUX2_5.a | 0.680909 | 0.997024 | 0.838966 |
MUX2_4.q | 0.879329 | 0.997024 | 0.938176 |
MUX2_4.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_4.b | 0.882035 | 0.994048 | 0.938041 |
MUX2_4.a | 0.780372 | 0.994048 | 0.887210 |
MUX2_3.q | 0.882035 | 0.994048 | 0.938041 |
MUX2_3.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_3.b | 0.775584 | 0.991071 | 0.883328 |
MUX2_3.a | 0.884740 | 0.991071 | 0.937906 |
MUX2_2.q | 0.882035 | 1.000000 | 0.941017 |
MUX2_2.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_2.b | 0.777985 | 0.997024 | 0.887504 |
MUX2_2.a | 0.884740 | 0.997024 | 0.940882 |
MUX2_1.q | 0.777985 | 0.997024 | 0.887504 |
MUX2_1.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_1.b | 0.680856 | 0.994048 | 0.837452 |
MUX2_1.a | 0.780372 | 0.994048 | 0.887210 |
ADD_5.q | 0.758945 | 0.903680 | 0.831312 |
ADD_5.b | 0.884740 | 0.775599 | 0.830169 |
ADD_5.a | 0.879329 | 0.799522 | 0.839425 |
ADD_4.q | 0.861034 | 0.900974 | 0.881004 |
ADD_4.b | 0.882035 | 0.879329 | 0.880682 |
ADD_4.a | 1.000000 | 0.794690 | 0.897345 |
ADD_3.q | 0.855751 | 0.898268 | 0.877010 |
ADD_3.b | 1.000000 | 0.768469 | 0.884234 |
ADD_3.a | 0.876623 | 0.898268 | 0.887446 |
ADD_2.q | 0.976190 | 0.906385 | 0.941288 |
ADD_2.b | 1.000000 | 0.884740 | 0.942370 |
ADD_2.a | 1.000000 | 0.906385 | 0.953193 |
ADD_1.q | 0.976190 | 0.906385 | 0.941288 |
ADD_1.b | 1.000000 | 0.884740 | 0.942370 |
ADD_1.a | 1.000000 | 0.906385 | 0.953193 |
SUB_5.q | 0.861034 | 0.900974 | 0.881004 |
SUB_5.b | 0.882035 | 0.879329 | 0.880682 |
SUB_5.a | 1.000000 | 0.794690 | 0.897345 |
SUB_4.q | 0.976190 | 0.898268 | 0.937229 |
SUB_4.b | 1.000000 | 0.876623 | 0.938312 |
SUB_4.a | 1.000000 | 0.898268 | 0.949134 |
SUB_3.q | 0.976190 | 0.906385 | 0.941288 |
SUB_3.b | 1.000000 | 0.884740 | 0.942370 |
SUB_3.a | 1.000000 | 0.906385 | 0.953193 |
SUB_2.q | 0.976190 | 0.903680 | 0.939935 |
SUB_2.b | 1.000000 | 0.882035 | 0.941017 |
SUB_2.a | 1.000000 | 0.903680 | 0.951840 |
SUB_1.q | 0.758893 | 0.900974 | 0.829934 |
SUB_1.b | 0.882035 | 0.775599 | 0.828817 |
SUB_1.a | 0.882035 | 0.794690 | 0.838362 |
CIRCUIT.CLK | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_5_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_4_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_3_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_2_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_1_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.pri_out_4 | 0.876623 | 1.000000 | 0.938312 |
CIRCUIT.pri_out_3 | 0.882035 | 1.000000 | 0.941017 |
CIRCUIT.pri_out_2 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_1 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_0 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_in_4 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_3 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_2 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_1 | 1.000000 | 0.884740 | 0.942370 |
CIRCUIT.pri_in_0 | 1.000000 | 0.882035 | 0.941017 |
Global measures | 0.958134 | 0.832955 | 0.798083 |
Arithmetic average | 0.916267 | 0.724218 | 0.820242 |
#Nodes(Total=621) | C(621/100.0%) | O(600/96.6%) | T(600/96.6%) |
This table was automatically generated by RTL-ADFT system Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz) Faculty of Information Technology Brno University of Technology Czech Republic |