'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8847400.9009740.892857
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9761900.8084420.892316
REG_9.q0.8794741.0000000.939737
REG_9.clk1.0000000.0000000.500000
REG_9.d0.9703800.9063850.938383
REG_8.q0.7663081.0000000.883154
REG_8.clk1.0000000.0000000.500000
REG_8.d0.8455410.9063850.875963
REG_7.q0.7827650.9940480.888406
REG_7.clk1.0000000.0000000.500000
REG_7.d0.8636750.9009740.882325
REG_6.q0.7757760.9940480.884912
REG_6.clk1.0000000.0000000.500000
REG_6.d0.8559640.9009740.878469
REG_5.q0.8768410.9970240.936932
REG_5.clk1.0000000.0000000.500000
REG_5.d0.9674740.9036800.935577
REG_4.q0.8847401.0000000.942370
REG_4.clk1.0000000.0000000.500000
REG_4.d0.9761900.9063850.941288
REG_3.q0.6862030.9910710.838637
REG_3.clk1.0000000.0000000.500000
REG_3.d0.7571460.8982680.827707
REG_2.q0.8847400.9970240.940882
REG_2.clk1.0000000.0000000.500000
REG_2.d0.9761900.9036800.939935
REG_1.q0.7755840.9940480.884816
REG_1.clk1.0000000.0000000.500000
REG_1.d0.8557760.9009740.878375
MUX2_5.q0.9940480.9970240.995536
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.9970240.9940480.995536
MUX2_5.a0.7755840.9940480.884816
MUX2_4.q0.9970240.9940480.995536
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.6862030.9910710.838637
MUX2_4.a1.0000000.9910710.995536
MUX2_3.q0.7803720.9970240.888698
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.7827650.9940480.888406
MUX2_3.a0.7757760.9940480.884912
MUX2_2.q0.9910711.0000000.995536
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.9940480.9970240.995536
MUX2_2.a0.8847400.9970240.940882
MUX2_1.q0.8741591.0000000.937080
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.7803720.9970240.888698
MUX2_1.a0.8768410.9970240.936932
ADD_5.q0.8559640.9009740.878469
ADD_5.b0.8768410.8793290.878085
ADD_5.a1.0000000.7900110.895005
ADD_4.q0.8455410.9063850.875963
ADD_4.b0.9910710.7734040.882238
ADD_4.a0.8741590.8982930.886226
ADD_3.q0.9703800.9063850.938383
ADD_3.b0.9940480.8847400.939394
ADD_3.a1.0000000.9009900.950495
ADD_2.q0.9674740.9036800.935577
ADD_2.b1.0000000.8741590.937080
ADD_2.a0.9910710.9036800.947376
ADD_1.q0.9761900.9036800.939935
ADD_1.b1.0000000.8820350.941017
ADD_1.a1.0000000.9036800.951840
SUB_5.q0.9761900.9063850.941288
SUB_5.b1.0000000.8847400.942370
SUB_5.a1.0000000.9063850.953193
SUB_4.q0.8557760.9009740.878375
SUB_4.b0.8847400.8714780.878109
SUB_4.a0.9910710.7971280.894100
SUB_3.q0.7571460.8982680.827707
SUB_3.b0.9940480.6840920.839070
SUB_3.a0.7803720.8929220.836647
SUB_2.q0.8636750.9009740.882325
SUB_2.b1.0000000.7779780.888989
SUB_2.a0.8847400.9009740.892857
SUB_1.q0.9761900.8084420.892316
SUB_1.b1.0000000.7889610.894481
SUB_1.a1.0000000.8084420.904221
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.8794741.0000000.939737
CIRCUIT.pri_out_30.7663081.0000000.883154
CIRCUIT.pri_out_20.8741591.0000000.937080
CIRCUIT.pri_out_10.8847401.0000000.942370
CIRCUIT.pri_out_00.9910711.0000000.995536
CIRCUIT.pri_in_41.0000000.9063850.953193
CIRCUIT.pri_in_31.0000000.8847400.942370
CIRCUIT.pri_in_21.0000000.9009900.950495
CIRCUIT.pri_in_11.0000000.9910710.995536
CIRCUIT.pri_in_01.0000000.9036800.951840
Global measures0.9642400.8316490.801910
Arithmetic average0.9284810.7215140.824997
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic