'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8821070.9009740.891541
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9732850.8084420.890863
REG_9.q0.8847401.0000000.942370
REG_9.clk1.0000000.0000000.500000
REG_9.d0.9761900.9063850.941288
REG_8.q0.6809710.9910710.836021
REG_8.clk1.0000000.0000000.500000
REG_8.d0.7590140.8982680.828641
REG_7.q0.6830040.9910710.837038
REG_7.clk1.0000000.0000000.500000
REG_7.d0.7612800.8982680.829774
REG_6.q0.7804360.9940480.887242
REG_6.clk1.0000000.0000000.500000
REG_6.d0.8611050.9009740.881039
REG_5.q0.8847401.0000000.942370
REG_5.clk1.0000000.0000000.500000
REG_5.d0.9761900.9063850.941288
REG_4.q0.8847401.0000000.942370
REG_4.clk1.0000000.0000000.500000
REG_4.d0.9761900.9063850.941288
REG_3.q0.8847400.9940480.939394
REG_3.clk1.0000000.0000000.500000
REG_3.d0.9761900.9009740.938582
REG_2.q0.8847400.9940480.939394
REG_2.clk1.0000000.0000000.500000
REG_2.d0.9761900.9009740.938582
REG_1.q0.8821070.9970240.939565
REG_1.clk1.0000000.0000000.500000
REG_1.d0.9732850.9036800.938482
MUX2_5.q0.7780490.9970240.887536
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.6808560.9940480.837452
MUX2_5.a0.7804360.9940480.887242
MUX2_4.q0.6808560.9940480.837452
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.6830040.9910710.837038
MUX2_4.a0.6809710.9910710.836021
MUX2_3.q0.8820350.9970240.939529
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.8847400.9940480.939394
MUX2_3.a0.8847400.9940480.939394
MUX2_2.q0.8794101.0000000.939705
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.8821070.9970240.939565
MUX2_2.a0.8820350.9970240.939529
MUX2_1.q0.9970241.0000000.998512
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.6787080.9970240.837866
MUX2_1.a1.0000000.9970240.998512
ADD_5.q0.7612800.8982680.829774
ADD_5.b0.8847400.7732120.828976
ADD_5.a0.8820350.7947340.838384
ADD_4.q0.9761900.9009740.938582
ADD_4.b1.0000000.8793290.939665
ADD_4.a1.0000000.9009740.950487
ADD_3.q0.9761900.9009740.938582
ADD_3.b1.0000000.8793290.939665
ADD_3.a1.0000000.9009740.950487
ADD_2.q0.9761900.9063850.941288
ADD_2.b1.0000000.8847400.942370
ADD_2.a1.0000000.9063850.953193
ADD_1.q0.9732850.9036800.938482
ADD_1.b0.9970240.8820350.939529
ADD_1.a1.0000000.9009900.950495
SUB_5.q0.8611050.9009740.881039
SUB_5.b1.0000000.7756620.887831
SUB_5.a0.8821070.9009740.891541
SUB_4.q0.9761900.9063850.941288
SUB_4.b1.0000000.8847400.942370
SUB_4.a1.0000000.9063850.953193
SUB_3.q0.9732850.8084420.890863
SUB_3.b1.0000000.7866130.893306
SUB_3.a0.9970240.8084420.902733
SUB_2.q0.9761900.9063850.941288
SUB_2.b1.0000000.8847400.942370
SUB_2.a1.0000000.9063850.953193
SUB_1.q0.7590140.8982680.828641
SUB_1.b0.8847400.7709110.827826
SUB_1.a0.8794100.7947340.837072
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.8847401.0000000.942370
CIRCUIT.pri_out_30.9970241.0000000.998512
CIRCUIT.pri_out_20.8847401.0000000.942370
CIRCUIT.pri_out_10.8847401.0000000.942370
CIRCUIT.pri_out_00.8794101.0000000.939705
CIRCUIT.pri_in_41.0000000.9063850.953193
CIRCUIT.pri_in_31.0000000.9063850.953193
CIRCUIT.pri_in_21.0000000.9970240.998512
CIRCUIT.pri_in_11.0000000.8847400.942370
CIRCUIT.pri_in_01.0000000.9063850.953193
Global measures0.9632440.8322340.801644
Arithmetic average0.9264880.7227240.824606
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic