'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8740950.8982680.886182
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9644630.8060060.885235
REG_9.q0.8821070.9036880.892897
REG_9.clk1.0000000.0000000.500000
REG_9.d0.9732850.8108910.892088
REG_8.q0.7780491.0000000.889025
REG_8.clk1.0000000.0000000.500000
REG_8.d0.8584790.9063850.882432
REG_7.q0.7756620.9940480.884855
REG_7.clk1.0000000.0000000.500000
REG_7.d0.8558540.9009740.878414
REG_6.q0.8794740.9970240.938249
REG_6.clk1.0000000.0000000.500000
REG_6.d0.9703800.9036800.937030
REG_5.q0.7780490.9970240.887536
REG_5.clk1.0000000.0000000.500000
REG_5.d0.8584790.9036800.881079
REG_4.q0.7733470.9910710.882209
REG_4.clk1.0000000.0000000.500000
REG_4.d0.8532830.8982680.875776
REG_3.q0.7781060.9910710.884589
REG_3.clk1.0000000.0000000.500000
REG_3.d0.8585340.8982680.878401
REG_2.q0.8821071.0000000.941054
REG_2.clk1.0000000.0000000.500000
REG_2.d0.9732850.9063850.939835
REG_1.q0.8847401.0000000.942370
REG_1.clk1.0000000.0000000.500000
REG_1.d0.9761900.9063850.941288
MUX2_5.q0.9970240.9970240.997024
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b1.0000000.9940480.997024
MUX2_5.a0.7757260.9940480.884887
MUX2_4.q0.9970240.9970240.997024
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.7756620.9940480.884855
MUX2_4.a1.0000000.9940480.997024
MUX2_3.q0.9940481.0000000.997024
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.7780490.9970240.887536
MUX2_3.a0.9970240.9970240.997024
MUX2_2.q0.7757260.9940480.884887
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.7781060.9910710.884589
MUX2_2.a0.7733470.9910710.882209
MUX2_1.q0.9940481.0000000.997024
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.9970240.9970240.997024
MUX2_1.a0.8794740.9970240.938249
ADD_5.q0.8532830.8982680.875776
ADD_5.b1.0000000.7662520.883126
ADD_5.a0.8740950.8982680.886182
ADD_4.q0.8585340.8982680.878401
ADD_4.b0.8794740.8766230.878049
ADD_4.a1.0000000.7900040.895002
ADD_3.q0.9732850.8108910.892088
ADD_3.b1.0000000.7891130.894557
ADD_3.a0.9970240.8108910.903957
ADD_2.q0.8584790.9063850.882432
ADD_2.b0.9970240.7804360.888730
ADD_2.a0.8821070.9036880.892897
ADD_1.q0.9703800.9036800.937030
ADD_1.b1.0000000.8767840.938392
ADD_1.a0.9940480.9036800.948864
SUB_5.q0.9644630.8060060.885235
SUB_5.b0.9940480.7818440.887946
SUB_5.a0.9940480.8012090.897628
SUB_4.q0.9761900.9063850.941288
SUB_4.b1.0000000.8847400.942370
SUB_4.a1.0000000.9063850.953193
SUB_3.q0.8584790.9036800.881079
SUB_3.b0.9970240.7780490.887536
SUB_3.a0.8821070.9009900.891549
SUB_2.q0.9732850.9063850.939835
SUB_2.b0.9970240.8847400.940882
SUB_2.a1.0000000.9036880.951844
SUB_1.q0.8558540.9009740.878414
SUB_1.b0.9940480.7756620.884855
SUB_1.a0.8821070.8956110.888859
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.7780491.0000000.889025
CIRCUIT.pri_out_30.9940481.0000000.997024
CIRCUIT.pri_out_20.9940481.0000000.997024
CIRCUIT.pri_out_10.8821071.0000000.941054
CIRCUIT.pri_out_00.8847401.0000000.942370
CIRCUIT.pri_in_41.0000000.9063850.953193
CIRCUIT.pri_in_31.0000000.8847400.942370
CIRCUIT.pri_in_21.0000000.9940480.997024
CIRCUIT.pri_in_11.0000000.9940480.997024
CIRCUIT.pri_in_01.0000000.9036880.951844
Global measures0.9686440.8302140.804182
Arithmetic average0.9372880.7185430.827916
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic