'CIRCUIT' testability results | |||
Port name | Con. | Obs. | Tst. |
REG_10.q | 0.884740 | 0.900974 | 0.892857 |
REG_10.clk | 1.000000 | 0.000000 | 0.500000 |
REG_10.d | 0.976190 | 0.808442 | 0.892316 |
REG_9.q | 0.879474 | 1.000000 | 0.939737 |
REG_9.clk | 1.000000 | 0.000000 | 0.500000 |
REG_9.d | 0.970380 | 0.906385 | 0.938383 |
REG_8.q | 0.766308 | 1.000000 | 0.883154 |
REG_8.clk | 1.000000 | 0.000000 | 0.500000 |
REG_8.d | 0.845541 | 0.906385 | 0.875963 |
REG_7.q | 0.782765 | 0.994048 | 0.888406 |
REG_7.clk | 1.000000 | 0.000000 | 0.500000 |
REG_7.d | 0.863675 | 0.900974 | 0.882325 |
REG_6.q | 0.775776 | 0.994048 | 0.884912 |
REG_6.clk | 1.000000 | 0.000000 | 0.500000 |
REG_6.d | 0.855964 | 0.900974 | 0.878469 |
REG_5.q | 0.876841 | 0.997024 | 0.936932 |
REG_5.clk | 1.000000 | 0.000000 | 0.500000 |
REG_5.d | 0.967474 | 0.903680 | 0.935577 |
REG_4.q | 0.884740 | 1.000000 | 0.942370 |
REG_4.clk | 1.000000 | 0.000000 | 0.500000 |
REG_4.d | 0.976190 | 0.906385 | 0.941288 |
REG_3.q | 0.686203 | 0.991071 | 0.838637 |
REG_3.clk | 1.000000 | 0.000000 | 0.500000 |
REG_3.d | 0.757146 | 0.898268 | 0.827707 |
REG_2.q | 0.884740 | 0.997024 | 0.940882 |
REG_2.clk | 1.000000 | 0.000000 | 0.500000 |
REG_2.d | 0.976190 | 0.903680 | 0.939935 |
REG_1.q | 0.775584 | 0.994048 | 0.884816 |
REG_1.clk | 1.000000 | 0.000000 | 0.500000 |
REG_1.d | 0.855776 | 0.900974 | 0.878375 |
MUX2_5.q | 0.994048 | 0.997024 | 0.995536 |
MUX2_5.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_5.b | 0.997024 | 0.994048 | 0.995536 |
MUX2_5.a | 0.775584 | 0.994048 | 0.884816 |
MUX2_4.q | 0.997024 | 0.994048 | 0.995536 |
MUX2_4.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_4.b | 0.686203 | 0.991071 | 0.838637 |
MUX2_4.a | 1.000000 | 0.991071 | 0.995536 |
MUX2_3.q | 0.780372 | 0.997024 | 0.888698 |
MUX2_3.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_3.b | 0.782765 | 0.994048 | 0.888406 |
MUX2_3.a | 0.775776 | 0.994048 | 0.884912 |
MUX2_2.q | 0.991071 | 1.000000 | 0.995536 |
MUX2_2.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_2.b | 0.994048 | 0.997024 | 0.995536 |
MUX2_2.a | 0.884740 | 0.997024 | 0.940882 |
MUX2_1.q | 0.874159 | 1.000000 | 0.937080 |
MUX2_1.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_1.b | 0.780372 | 0.997024 | 0.888698 |
MUX2_1.a | 0.876841 | 0.997024 | 0.936932 |
ADD_5.q | 0.855964 | 0.900974 | 0.878469 |
ADD_5.b | 0.876841 | 0.879329 | 0.878085 |
ADD_5.a | 1.000000 | 0.790011 | 0.895005 |
ADD_4.q | 0.845541 | 0.906385 | 0.875963 |
ADD_4.b | 0.991071 | 0.773404 | 0.882238 |
ADD_4.a | 0.874159 | 0.898293 | 0.886226 |
ADD_3.q | 0.970380 | 0.906385 | 0.938383 |
ADD_3.b | 0.994048 | 0.884740 | 0.939394 |
ADD_3.a | 1.000000 | 0.900990 | 0.950495 |
ADD_2.q | 0.967474 | 0.903680 | 0.935577 |
ADD_2.b | 1.000000 | 0.874159 | 0.937080 |
ADD_2.a | 0.991071 | 0.903680 | 0.947376 |
ADD_1.q | 0.976190 | 0.903680 | 0.939935 |
ADD_1.b | 1.000000 | 0.882035 | 0.941017 |
ADD_1.a | 1.000000 | 0.903680 | 0.951840 |
SUB_5.q | 0.976190 | 0.906385 | 0.941288 |
SUB_5.b | 1.000000 | 0.884740 | 0.942370 |
SUB_5.a | 1.000000 | 0.906385 | 0.953193 |
SUB_4.q | 0.855776 | 0.900974 | 0.878375 |
SUB_4.b | 0.884740 | 0.871478 | 0.878109 |
SUB_4.a | 0.991071 | 0.797128 | 0.894100 |
SUB_3.q | 0.757146 | 0.898268 | 0.827707 |
SUB_3.b | 0.994048 | 0.684092 | 0.839070 |
SUB_3.a | 0.780372 | 0.892922 | 0.836647 |
SUB_2.q | 0.863675 | 0.900974 | 0.882325 |
SUB_2.b | 1.000000 | 0.777978 | 0.888989 |
SUB_2.a | 0.884740 | 0.900974 | 0.892857 |
SUB_1.q | 0.976190 | 0.808442 | 0.892316 |
SUB_1.b | 1.000000 | 0.788961 | 0.894481 |
SUB_1.a | 1.000000 | 0.808442 | 0.904221 |
CIRCUIT.CLK | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_5_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_4_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_3_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_2_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_1_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.pri_out_4 | 0.879474 | 1.000000 | 0.939737 |
CIRCUIT.pri_out_3 | 0.766308 | 1.000000 | 0.883154 |
CIRCUIT.pri_out_2 | 0.874159 | 1.000000 | 0.937080 |
CIRCUIT.pri_out_1 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_0 | 0.991071 | 1.000000 | 0.995536 |
CIRCUIT.pri_in_4 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_3 | 1.000000 | 0.884740 | 0.942370 |
CIRCUIT.pri_in_2 | 1.000000 | 0.900990 | 0.950495 |
CIRCUIT.pri_in_1 | 1.000000 | 0.991071 | 0.995536 |
CIRCUIT.pri_in_0 | 1.000000 | 0.903680 | 0.951840 |
Global measures | 0.964240 | 0.831649 | 0.801910 |
Arithmetic average | 0.928481 | 0.721514 | 0.824997 |
#Nodes(Total=621) | C(621/100.0%) | O(600/96.6%) | T(600/96.6%) |
This table was automatically generated by RTL-ADFT system Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz) Faculty of Information Technology Brno University of Technology Czech Republic |