'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.6809090.9970240.838966
REG_10.clk1.0000000.0000000.500000
REG_10.d0.7589450.9036800.831312
REG_9.q0.7803720.9940480.887210
REG_9.clk1.0000000.0000000.500000
REG_9.d0.8610340.9009740.881004
REG_8.q0.7755840.9910710.883328
REG_8.clk1.0000000.0000000.500000
REG_8.d0.8557510.8982680.877010
REG_7.q0.8847400.9910710.937906
REG_7.clk1.0000000.0000000.500000
REG_7.d0.9761900.8982680.937229
REG_6.q0.8847400.9970240.940882
REG_6.clk1.0000000.0000000.500000
REG_6.d0.9761900.9036800.939935
REG_5.q0.6808560.9940480.837452
REG_5.clk1.0000000.0000000.500000
REG_5.d0.7588930.9009740.829934
REG_4.q0.7803720.9940480.887210
REG_4.clk1.0000000.0000000.500000
REG_4.d0.8610340.9009740.881004
REG_3.q0.8847401.0000000.942370
REG_3.clk1.0000000.0000000.500000
REG_3.d0.9761900.9063850.941288
REG_2.q0.8847401.0000000.942370
REG_2.clk1.0000000.0000000.500000
REG_2.d0.9761900.9063850.941288
REG_1.q0.8847401.0000000.942370
REG_1.clk1.0000000.0000000.500000
REG_1.d0.9761900.9063850.941288
MUX2_5.q0.8766231.0000000.938312
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.8793290.9970240.938176
MUX2_5.a0.6809090.9970240.838966
MUX2_4.q0.8793290.9970240.938176
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.8820350.9940480.938041
MUX2_4.a0.7803720.9940480.887210
MUX2_3.q0.8820350.9940480.938041
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.7755840.9910710.883328
MUX2_3.a0.8847400.9910710.937906
MUX2_2.q0.8820351.0000000.941017
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.7779850.9970240.887504
MUX2_2.a0.8847400.9970240.940882
MUX2_1.q0.7779850.9970240.887504
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.6808560.9940480.837452
MUX2_1.a0.7803720.9940480.887210
ADD_5.q0.7589450.9036800.831312
ADD_5.b0.8847400.7755990.830169
ADD_5.a0.8793290.7995220.839425
ADD_4.q0.8610340.9009740.881004
ADD_4.b0.8820350.8793290.880682
ADD_4.a1.0000000.7946900.897345
ADD_3.q0.8557510.8982680.877010
ADD_3.b1.0000000.7684690.884234
ADD_3.a0.8766230.8982680.887446
ADD_2.q0.9761900.9063850.941288
ADD_2.b1.0000000.8847400.942370
ADD_2.a1.0000000.9063850.953193
ADD_1.q0.9761900.9063850.941288
ADD_1.b1.0000000.8847400.942370
ADD_1.a1.0000000.9063850.953193
SUB_5.q0.8610340.9009740.881004
SUB_5.b0.8820350.8793290.880682
SUB_5.a1.0000000.7946900.897345
SUB_4.q0.9761900.8982680.937229
SUB_4.b1.0000000.8766230.938312
SUB_4.a1.0000000.8982680.949134
SUB_3.q0.9761900.9063850.941288
SUB_3.b1.0000000.8847400.942370
SUB_3.a1.0000000.9063850.953193
SUB_2.q0.9761900.9036800.939935
SUB_2.b1.0000000.8820350.941017
SUB_2.a1.0000000.9036800.951840
SUB_1.q0.7588930.9009740.829934
SUB_1.b0.8820350.7755990.828817
SUB_1.a0.8820350.7946900.838362
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.8766231.0000000.938312
CIRCUIT.pri_out_30.8820351.0000000.941017
CIRCUIT.pri_out_20.8847401.0000000.942370
CIRCUIT.pri_out_10.8847401.0000000.942370
CIRCUIT.pri_out_00.8847401.0000000.942370
CIRCUIT.pri_in_41.0000000.9063850.953193
CIRCUIT.pri_in_31.0000000.9063850.953193
CIRCUIT.pri_in_21.0000000.9063850.953193
CIRCUIT.pri_in_11.0000000.8847400.942370
CIRCUIT.pri_in_01.0000000.8820350.941017
Global measures0.9581340.8329550.798083
Arithmetic average0.9162670.7242180.820242
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic