'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8794740.9036880.891581
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9703800.8108910.890635
REG_9.q0.7757261.0000000.887863
REG_9.clk1.0000000.0000000.500000
REG_9.d0.8559170.9063850.881151
REG_8.q0.7803720.9940480.887210
REG_8.clk1.0000000.0000000.500000
REG_8.d0.8610420.9009740.881008
REG_7.q0.8821070.9970240.939565
REG_7.clk1.0000000.0000000.500000
REG_7.d0.9732850.9036800.938482
REG_6.q0.7756700.9940480.884859
REG_6.clk1.0000000.0000000.500000
REG_6.d0.8558540.9009740.878414
REG_5.q0.8847401.0000000.942370
REG_5.clk1.0000000.0000000.500000
REG_5.d0.9761900.9063850.941288
REG_4.q0.8794740.9970240.938249
REG_4.clk1.0000000.0000000.500000
REG_4.d0.9703800.9036800.937030
REG_3.q0.7756620.9910710.883367
REG_3.clk1.0000000.0000000.500000
REG_3.d0.8558540.8982680.877061
REG_2.q0.7780490.9910710.884560
REG_2.clk1.0000000.0000000.500000
REG_2.d0.8584790.8982680.878374
REG_1.q0.8821071.0000000.941054
REG_1.clk1.0000000.0000000.500000
REG_1.d0.9732850.9063850.939835
MUX2_5.q0.9940481.0000000.997024
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.9970240.9970240.997024
MUX2_5.a0.8794740.9970240.938249
MUX2_4.q0.7779780.9970240.887501
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.7803720.9940480.887210
MUX2_4.a0.7756700.9940480.884859
MUX2_3.q0.9970240.9970240.997024
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.7756620.9940480.884855
MUX2_3.a1.0000000.9940480.997024
MUX2_2.q0.8794101.0000000.939705
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.8821070.9970240.939565
MUX2_2.a0.7779780.9970240.887501
MUX2_1.q0.7756620.9940480.884855
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.7756620.9910710.883367
MUX2_1.a0.7780490.9910710.884560
ADD_5.q0.9732850.9036800.938482
ADD_5.b0.9970240.8820350.939529
ADD_5.a1.0000000.9009900.950495
ADD_4.q0.8558540.8982680.877061
ADD_4.b0.8821070.8714050.876756
ADD_4.a0.9940480.7923690.893208
ADD_3.q0.8558540.9009740.878414
ADD_3.b0.8794100.8767120.878061
ADD_3.a0.9970240.7923250.894674
ADD_2.q0.9761900.9063850.941288
ADD_2.b1.0000000.8847400.942370
ADD_2.a1.0000000.9063850.953193
ADD_1.q0.8584790.8982680.878374
ADD_1.b0.9970240.7732760.885150
ADD_1.a0.8821070.8955950.888851
SUB_5.q0.9703800.8108910.890635
SUB_5.b0.9940480.7914690.892758
SUB_5.a1.0000000.8060640.903032
SUB_4.q0.9732850.9063850.939835
SUB_4.b0.9970240.8847400.940882
SUB_4.a1.0000000.9036880.951844
SUB_3.q0.9703800.9036800.937030
SUB_3.b1.0000000.8767840.938392
SUB_3.a0.9940480.9036800.948864
SUB_2.q0.8610420.9009740.881008
SUB_2.b0.9970240.7779780.887501
SUB_2.a0.8847400.8982930.891516
SUB_1.q0.8559170.9063850.881151
SUB_1.b0.9970240.7781060.887565
SUB_1.a0.8794740.9036880.891581
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.7757261.0000000.887863
CIRCUIT.pri_out_30.8794101.0000000.939705
CIRCUIT.pri_out_20.8847401.0000000.942370
CIRCUIT.pri_out_10.9940481.0000000.997024
CIRCUIT.pri_out_00.8821071.0000000.941054
CIRCUIT.pri_in_41.0000000.9009900.950495
CIRCUIT.pri_in_31.0000000.9940480.997024
CIRCUIT.pri_in_21.0000000.9063850.953193
CIRCUIT.pri_in_11.0000000.8847400.942370
CIRCUIT.pri_in_01.0000000.9036880.951844
Global measures0.9647340.8321480.802802
Arithmetic average0.9294690.7225460.826007
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic