'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8847400.9009740.892857
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9761900.8084420.892316
REG_9.q0.7827650.9940480.888406
REG_9.clk1.0000000.0000000.500000
REG_9.d0.8636750.9009740.882325
REG_8.q0.7780490.9910710.884560
REG_8.clk1.0000000.0000000.500000
REG_8.d0.8584710.8982680.878370
REG_7.q0.7780490.9910710.884560
REG_7.clk1.0000000.0000000.500000
REG_7.d0.8584710.8982680.878370
REG_6.q0.7827650.9970240.889895
REG_6.clk1.0000000.0000000.500000
REG_6.d0.8636750.9036800.883677
REG_5.q0.8821070.9940480.938077
REG_5.clk1.0000000.0000000.500000
REG_5.d0.9732850.9009740.937130
REG_4.q0.7756700.9940480.884859
REG_4.clk1.0000000.0000000.500000
REG_4.d0.8558540.9009740.878414
REG_3.q0.8847401.0000000.942370
REG_3.clk1.0000000.0000000.500000
REG_3.d0.9761900.9063850.941288
REG_2.q0.8847401.0000000.942370
REG_2.clk1.0000000.0000000.500000
REG_2.d0.9761900.9063850.941288
REG_1.q0.8847401.0000000.942370
REG_1.clk1.0000000.0000000.500000
REG_1.d0.9761900.9063850.941288
MUX2_5.q0.9970241.0000000.998512
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.7803720.9970240.888698
MUX2_5.a1.0000000.9970240.998512
MUX2_4.q0.7803720.9970240.888698
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.7756700.9940480.884859
MUX2_4.a0.7827650.9940480.888406
MUX2_3.q0.8767121.0000000.938356
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.8794100.9970240.938217
MUX2_3.a0.7827650.9970240.889895
MUX2_2.q0.8794100.9970240.938217
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b0.8821070.9940480.938077
MUX2_2.a0.7756700.9940480.884859
MUX2_1.q0.7756700.9940480.884859
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.7780490.9910710.884560
MUX2_1.a0.7780490.9910710.884560
ADD_5.q0.9761900.9063850.941288
ADD_5.b1.0000000.8847400.942370
ADD_5.a1.0000000.9063850.953193
ADD_4.q0.8636750.9009740.882325
ADD_4.b1.0000000.7779780.888989
ADD_4.a0.8847400.9009740.892857
ADD_3.q0.8558540.9009740.878414
ADD_3.b0.8794100.8767120.878061
ADD_3.a0.9970240.7923250.894674
ADD_2.q0.9761900.9063850.941288
ADD_2.b1.0000000.8847400.942370
ADD_2.a1.0000000.9063850.953193
ADD_1.q0.8584710.8982680.878370
ADD_1.b1.0000000.7709110.885455
ADD_1.a0.8794100.8982680.888839
SUB_5.q0.8584710.8982680.878370
SUB_5.b1.0000000.7709110.885455
SUB_5.a0.8794100.8982680.888839
SUB_4.q0.9761900.8084420.892316
SUB_4.b1.0000000.7889610.894481
SUB_4.a1.0000000.8084420.904221
SUB_3.q0.8636750.9036800.883677
SUB_3.b1.0000000.7803720.890186
SUB_3.a0.8847400.9036800.894210
SUB_2.q0.9732850.9009740.937130
SUB_2.b0.9970240.8793290.938176
SUB_2.a1.0000000.8982930.949146
SUB_1.q0.9761900.9063850.941288
SUB_1.b1.0000000.8847400.942370
SUB_1.a1.0000000.9063850.953193
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.9970241.0000000.998512
CIRCUIT.pri_out_30.7803721.0000000.890186
CIRCUIT.pri_out_20.8847401.0000000.942370
CIRCUIT.pri_out_10.8847401.0000000.942370
CIRCUIT.pri_out_00.8847401.0000000.942370
CIRCUIT.pri_in_41.0000000.9063850.953193
CIRCUIT.pri_in_31.0000000.8982930.949146
CIRCUIT.pri_in_21.0000000.9970240.998512
CIRCUIT.pri_in_11.0000000.8847400.942370
CIRCUIT.pri_in_01.0000000.9063850.953193
Global measures0.9637090.8321750.801975
Arithmetic average0.9274180.7226030.825011
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic