'CIRCUIT' testability results | |||
Port name | Con. | Obs. | Tst. |
REG_10.q | 0.884740 | 0.900974 | 0.892857 |
REG_10.clk | 1.000000 | 0.000000 | 0.500000 |
REG_10.d | 0.976190 | 0.808442 | 0.892316 |
REG_9.q | 0.782765 | 0.994048 | 0.888406 |
REG_9.clk | 1.000000 | 0.000000 | 0.500000 |
REG_9.d | 0.863675 | 0.900974 | 0.882325 |
REG_8.q | 0.778049 | 0.991071 | 0.884560 |
REG_8.clk | 1.000000 | 0.000000 | 0.500000 |
REG_8.d | 0.858471 | 0.898268 | 0.878370 |
REG_7.q | 0.778049 | 0.991071 | 0.884560 |
REG_7.clk | 1.000000 | 0.000000 | 0.500000 |
REG_7.d | 0.858471 | 0.898268 | 0.878370 |
REG_6.q | 0.782765 | 0.997024 | 0.889895 |
REG_6.clk | 1.000000 | 0.000000 | 0.500000 |
REG_6.d | 0.863675 | 0.903680 | 0.883677 |
REG_5.q | 0.882107 | 0.994048 | 0.938077 |
REG_5.clk | 1.000000 | 0.000000 | 0.500000 |
REG_5.d | 0.973285 | 0.900974 | 0.937130 |
REG_4.q | 0.775670 | 0.994048 | 0.884859 |
REG_4.clk | 1.000000 | 0.000000 | 0.500000 |
REG_4.d | 0.855854 | 0.900974 | 0.878414 |
REG_3.q | 0.884740 | 1.000000 | 0.942370 |
REG_3.clk | 1.000000 | 0.000000 | 0.500000 |
REG_3.d | 0.976190 | 0.906385 | 0.941288 |
REG_2.q | 0.884740 | 1.000000 | 0.942370 |
REG_2.clk | 1.000000 | 0.000000 | 0.500000 |
REG_2.d | 0.976190 | 0.906385 | 0.941288 |
REG_1.q | 0.884740 | 1.000000 | 0.942370 |
REG_1.clk | 1.000000 | 0.000000 | 0.500000 |
REG_1.d | 0.976190 | 0.906385 | 0.941288 |
MUX2_5.q | 0.997024 | 1.000000 | 0.998512 |
MUX2_5.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_5.b | 0.780372 | 0.997024 | 0.888698 |
MUX2_5.a | 1.000000 | 0.997024 | 0.998512 |
MUX2_4.q | 0.780372 | 0.997024 | 0.888698 |
MUX2_4.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_4.b | 0.775670 | 0.994048 | 0.884859 |
MUX2_4.a | 0.782765 | 0.994048 | 0.888406 |
MUX2_3.q | 0.876712 | 1.000000 | 0.938356 |
MUX2_3.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_3.b | 0.879410 | 0.997024 | 0.938217 |
MUX2_3.a | 0.782765 | 0.997024 | 0.889895 |
MUX2_2.q | 0.879410 | 0.997024 | 0.938217 |
MUX2_2.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_2.b | 0.882107 | 0.994048 | 0.938077 |
MUX2_2.a | 0.775670 | 0.994048 | 0.884859 |
MUX2_1.q | 0.775670 | 0.994048 | 0.884859 |
MUX2_1.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_1.b | 0.778049 | 0.991071 | 0.884560 |
MUX2_1.a | 0.778049 | 0.991071 | 0.884560 |
ADD_5.q | 0.976190 | 0.906385 | 0.941288 |
ADD_5.b | 1.000000 | 0.884740 | 0.942370 |
ADD_5.a | 1.000000 | 0.906385 | 0.953193 |
ADD_4.q | 0.863675 | 0.900974 | 0.882325 |
ADD_4.b | 1.000000 | 0.777978 | 0.888989 |
ADD_4.a | 0.884740 | 0.900974 | 0.892857 |
ADD_3.q | 0.855854 | 0.900974 | 0.878414 |
ADD_3.b | 0.879410 | 0.876712 | 0.878061 |
ADD_3.a | 0.997024 | 0.792325 | 0.894674 |
ADD_2.q | 0.976190 | 0.906385 | 0.941288 |
ADD_2.b | 1.000000 | 0.884740 | 0.942370 |
ADD_2.a | 1.000000 | 0.906385 | 0.953193 |
ADD_1.q | 0.858471 | 0.898268 | 0.878370 |
ADD_1.b | 1.000000 | 0.770911 | 0.885455 |
ADD_1.a | 0.879410 | 0.898268 | 0.888839 |
SUB_5.q | 0.858471 | 0.898268 | 0.878370 |
SUB_5.b | 1.000000 | 0.770911 | 0.885455 |
SUB_5.a | 0.879410 | 0.898268 | 0.888839 |
SUB_4.q | 0.976190 | 0.808442 | 0.892316 |
SUB_4.b | 1.000000 | 0.788961 | 0.894481 |
SUB_4.a | 1.000000 | 0.808442 | 0.904221 |
SUB_3.q | 0.863675 | 0.903680 | 0.883677 |
SUB_3.b | 1.000000 | 0.780372 | 0.890186 |
SUB_3.a | 0.884740 | 0.903680 | 0.894210 |
SUB_2.q | 0.973285 | 0.900974 | 0.937130 |
SUB_2.b | 0.997024 | 0.879329 | 0.938176 |
SUB_2.a | 1.000000 | 0.898293 | 0.949146 |
SUB_1.q | 0.976190 | 0.906385 | 0.941288 |
SUB_1.b | 1.000000 | 0.884740 | 0.942370 |
SUB_1.a | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.CLK | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_5_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_4_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_3_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_2_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_1_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.pri_out_4 | 0.997024 | 1.000000 | 0.998512 |
CIRCUIT.pri_out_3 | 0.780372 | 1.000000 | 0.890186 |
CIRCUIT.pri_out_2 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_1 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_0 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_in_4 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_3 | 1.000000 | 0.898293 | 0.949146 |
CIRCUIT.pri_in_2 | 1.000000 | 0.997024 | 0.998512 |
CIRCUIT.pri_in_1 | 1.000000 | 0.884740 | 0.942370 |
CIRCUIT.pri_in_0 | 1.000000 | 0.906385 | 0.953193 |
Global measures | 0.963709 | 0.832175 | 0.801975 |
Arithmetic average | 0.927418 | 0.722603 | 0.825011 |
#Nodes(Total=621) | C(621/100.0%) | O(600/96.6%) | T(600/96.6%) |
This table was automatically generated by RTL-ADFT system Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz) Faculty of Information Technology Brno University of Technology Czech Republic |