'CIRCUIT' testability results
Port name Con. Obs. Tst.
REG_10.q0.8821070.9036880.892897
REG_10.clk1.0000000.0000000.500000
REG_10.d0.9732850.8108910.892088
REG_9.q0.6768040.9940480.835426
REG_9.clk1.0000000.0000000.500000
REG_9.d0.7543760.9009740.827675
REG_8.q0.7733470.9940480.883697
REG_8.clk1.0000000.0000000.500000
REG_8.d0.8532830.9009740.877129
REG_7.q0.8767840.9970240.936904
REG_7.clk1.0000000.0000000.500000
REG_7.d0.9674210.9036800.935550
REG_6.q0.8847401.0000000.942370
REG_6.clk1.0000000.0000000.500000
REG_6.d0.9761900.9063850.941288
REG_5.q0.7780491.0000000.889025
REG_5.clk1.0000000.0000000.500000
REG_5.d0.8584790.9063850.882432
REG_4.q0.7779850.9940480.886016
REG_4.clk1.0000000.0000000.500000
REG_4.d0.8584090.9009740.879691
REG_3.q0.7709820.9970240.884003
REG_3.clk1.0000000.0000000.500000
REG_3.d0.8506820.9036800.877181
REG_2.q0.8794740.9970240.938249
REG_2.clk1.0000000.0000000.500000
REG_2.d0.9703800.9036800.937030
REG_1.q0.8847400.9970240.940882
REG_1.clk1.0000000.0000000.500000
REG_1.d0.9761900.9036800.939935
MUX2_5.q0.8740951.0000000.937047
MUX2_5.sel1.0000000.0000000.500000
MUX2_5.b0.7709820.9970240.884003
MUX2_5.a0.8767840.9970240.936904
MUX2_4.q0.7709820.9970240.884003
MUX2_4.sel1.0000000.0000000.500000
MUX2_4.b0.7733470.9940480.883697
MUX2_4.a0.6768040.9940480.835426
MUX2_3.q0.9940481.0000000.997024
MUX2_3.sel1.0000000.0000000.500000
MUX2_3.b0.9970240.9970240.997024
MUX2_3.a0.7709820.9970240.884003
MUX2_2.q0.9970240.9970240.997024
MUX2_2.sel1.0000000.0000000.500000
MUX2_2.b1.0000000.9940480.997024
MUX2_2.a0.7779850.9940480.886016
MUX2_1.q0.8820351.0000000.941017
MUX2_1.sel1.0000000.0000000.500000
MUX2_1.b0.8794740.9970240.938249
MUX2_1.a0.8847400.9970240.940882
ADD_5.q0.8584090.9009740.879691
ADD_5.b0.9970240.7755990.886311
ADD_5.a0.8820350.8982930.890164
ADD_4.q0.9761900.9063850.941288
ADD_4.b1.0000000.8847400.942370
ADD_4.a1.0000000.9063850.953193
ADD_3.q0.9732850.8108910.892088
ADD_3.b1.0000000.7891130.894557
ADD_3.a0.9970240.8108910.903957
ADD_2.q0.8506820.9036800.877181
ADD_2.b0.9970240.7709820.884003
ADD_2.a0.8740950.9009900.887543
ADD_1.q0.8532830.9009740.877129
ADD_1.b1.0000000.7686170.884309
ADD_1.a0.8740950.9009740.887534
SUB_5.q0.9674210.9036800.935550
SUB_5.b0.9940480.8794100.936729
SUB_5.a0.9970240.8983010.947662
SUB_4.q0.9761900.9036800.939935
SUB_4.b1.0000000.8820350.941017
SUB_4.a1.0000000.9036800.951840
SUB_3.q0.8584790.9063850.882432
SUB_3.b0.9970240.7804360.888730
SUB_3.a0.8821070.9036880.892897
SUB_2.q0.7543760.9009740.827675
SUB_2.b0.8820350.7709820.826508
SUB_2.a0.8767840.7946900.835737
SUB_1.q0.9703800.9036800.937030
SUB_1.b1.0000000.8767840.938392
SUB_1.a0.9940480.9036800.948864
CIRCUIT.CLK1.0000000.0000000.500000
CIRCUIT.C_MUX2_5_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_4_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_3_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_2_sel1.0000000.0000000.500000
CIRCUIT.C_MUX2_1_sel1.0000000.0000000.500000
CIRCUIT.pri_out_40.8740951.0000000.937047
CIRCUIT.pri_out_30.8847401.0000000.942370
CIRCUIT.pri_out_20.7780491.0000000.889025
CIRCUIT.pri_out_10.9940481.0000000.997024
CIRCUIT.pri_out_00.8820351.0000000.941017
CIRCUIT.pri_in_41.0000000.9063850.953193
CIRCUIT.pri_in_31.0000000.9036800.951840
CIRCUIT.pri_in_21.0000000.9940480.997024
CIRCUIT.pri_in_11.0000000.8847400.942370
CIRCUIT.pri_in_01.0000000.8820350.941017
Global measures0.9627400.8317230.800733
Arithmetic average0.9254800.7216670.823573
#Nodes(Total=621)C(621/100.0%)O(600/96.6%)T(600/96.6%)
This table was automatically generated by RTL-ADFT system
Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz)
Faculty of Information Technology
Brno University of Technology
Czech Republic