'CIRCUIT' testability results | |||
Port name | Con. | Obs. | Tst. |
REG_10.q | 0.882107 | 0.900974 | 0.891541 |
REG_10.clk | 1.000000 | 0.000000 | 0.500000 |
REG_10.d | 0.973285 | 0.808442 | 0.890863 |
REG_9.q | 0.884740 | 1.000000 | 0.942370 |
REG_9.clk | 1.000000 | 0.000000 | 0.500000 |
REG_9.d | 0.976190 | 0.906385 | 0.941288 |
REG_8.q | 0.680971 | 0.991071 | 0.836021 |
REG_8.clk | 1.000000 | 0.000000 | 0.500000 |
REG_8.d | 0.759014 | 0.898268 | 0.828641 |
REG_7.q | 0.683004 | 0.991071 | 0.837038 |
REG_7.clk | 1.000000 | 0.000000 | 0.500000 |
REG_7.d | 0.761280 | 0.898268 | 0.829774 |
REG_6.q | 0.780436 | 0.994048 | 0.887242 |
REG_6.clk | 1.000000 | 0.000000 | 0.500000 |
REG_6.d | 0.861105 | 0.900974 | 0.881039 |
REG_5.q | 0.884740 | 1.000000 | 0.942370 |
REG_5.clk | 1.000000 | 0.000000 | 0.500000 |
REG_5.d | 0.976190 | 0.906385 | 0.941288 |
REG_4.q | 0.884740 | 1.000000 | 0.942370 |
REG_4.clk | 1.000000 | 0.000000 | 0.500000 |
REG_4.d | 0.976190 | 0.906385 | 0.941288 |
REG_3.q | 0.884740 | 0.994048 | 0.939394 |
REG_3.clk | 1.000000 | 0.000000 | 0.500000 |
REG_3.d | 0.976190 | 0.900974 | 0.938582 |
REG_2.q | 0.884740 | 0.994048 | 0.939394 |
REG_2.clk | 1.000000 | 0.000000 | 0.500000 |
REG_2.d | 0.976190 | 0.900974 | 0.938582 |
REG_1.q | 0.882107 | 0.997024 | 0.939565 |
REG_1.clk | 1.000000 | 0.000000 | 0.500000 |
REG_1.d | 0.973285 | 0.903680 | 0.938482 |
MUX2_5.q | 0.778049 | 0.997024 | 0.887536 |
MUX2_5.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_5.b | 0.680856 | 0.994048 | 0.837452 |
MUX2_5.a | 0.780436 | 0.994048 | 0.887242 |
MUX2_4.q | 0.680856 | 0.994048 | 0.837452 |
MUX2_4.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_4.b | 0.683004 | 0.991071 | 0.837038 |
MUX2_4.a | 0.680971 | 0.991071 | 0.836021 |
MUX2_3.q | 0.882035 | 0.997024 | 0.939529 |
MUX2_3.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_3.b | 0.884740 | 0.994048 | 0.939394 |
MUX2_3.a | 0.884740 | 0.994048 | 0.939394 |
MUX2_2.q | 0.879410 | 1.000000 | 0.939705 |
MUX2_2.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_2.b | 0.882107 | 0.997024 | 0.939565 |
MUX2_2.a | 0.882035 | 0.997024 | 0.939529 |
MUX2_1.q | 0.997024 | 1.000000 | 0.998512 |
MUX2_1.sel | 1.000000 | 0.000000 | 0.500000 |
MUX2_1.b | 0.678708 | 0.997024 | 0.837866 |
MUX2_1.a | 1.000000 | 0.997024 | 0.998512 |
ADD_5.q | 0.761280 | 0.898268 | 0.829774 |
ADD_5.b | 0.884740 | 0.773212 | 0.828976 |
ADD_5.a | 0.882035 | 0.794734 | 0.838384 |
ADD_4.q | 0.976190 | 0.900974 | 0.938582 |
ADD_4.b | 1.000000 | 0.879329 | 0.939665 |
ADD_4.a | 1.000000 | 0.900974 | 0.950487 |
ADD_3.q | 0.976190 | 0.900974 | 0.938582 |
ADD_3.b | 1.000000 | 0.879329 | 0.939665 |
ADD_3.a | 1.000000 | 0.900974 | 0.950487 |
ADD_2.q | 0.976190 | 0.906385 | 0.941288 |
ADD_2.b | 1.000000 | 0.884740 | 0.942370 |
ADD_2.a | 1.000000 | 0.906385 | 0.953193 |
ADD_1.q | 0.973285 | 0.903680 | 0.938482 |
ADD_1.b | 0.997024 | 0.882035 | 0.939529 |
ADD_1.a | 1.000000 | 0.900990 | 0.950495 |
SUB_5.q | 0.861105 | 0.900974 | 0.881039 |
SUB_5.b | 1.000000 | 0.775662 | 0.887831 |
SUB_5.a | 0.882107 | 0.900974 | 0.891541 |
SUB_4.q | 0.976190 | 0.906385 | 0.941288 |
SUB_4.b | 1.000000 | 0.884740 | 0.942370 |
SUB_4.a | 1.000000 | 0.906385 | 0.953193 |
SUB_3.q | 0.973285 | 0.808442 | 0.890863 |
SUB_3.b | 1.000000 | 0.786613 | 0.893306 |
SUB_3.a | 0.997024 | 0.808442 | 0.902733 |
SUB_2.q | 0.976190 | 0.906385 | 0.941288 |
SUB_2.b | 1.000000 | 0.884740 | 0.942370 |
SUB_2.a | 1.000000 | 0.906385 | 0.953193 |
SUB_1.q | 0.759014 | 0.898268 | 0.828641 |
SUB_1.b | 0.884740 | 0.770911 | 0.827826 |
SUB_1.a | 0.879410 | 0.794734 | 0.837072 |
CIRCUIT.CLK | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_5_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_4_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_3_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_2_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.C_MUX2_1_sel | 1.000000 | 0.000000 | 0.500000 |
CIRCUIT.pri_out_4 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_3 | 0.997024 | 1.000000 | 0.998512 |
CIRCUIT.pri_out_2 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_1 | 0.884740 | 1.000000 | 0.942370 |
CIRCUIT.pri_out_0 | 0.879410 | 1.000000 | 0.939705 |
CIRCUIT.pri_in_4 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_3 | 1.000000 | 0.906385 | 0.953193 |
CIRCUIT.pri_in_2 | 1.000000 | 0.997024 | 0.998512 |
CIRCUIT.pri_in_1 | 1.000000 | 0.884740 | 0.942370 |
CIRCUIT.pri_in_0 | 1.000000 | 0.906385 | 0.953193 |
Global measures | 0.963244 | 0.832234 | 0.801644 |
Arithmetic average | 0.926488 | 0.722724 | 0.824606 |
#Nodes(Total=621) | C(621/100.0%) | O(600/96.6%) | T(600/96.6%) |
This table was automatically generated by RTL-ADFT system Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz) Faculty of Information Technology Brno University of Technology Czech Republic |