| 'CIRCUIT' testability results | |||
| Port name | Con. | Obs. | Tst. |
| REG_10.q | 0.000000 | 0.000000 | 0.000000 |
| REG_10.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_10.d | 0.000000 | 0.000000 | 0.000000 |
| REG_9.q | 0.000000 | 0.000000 | 0.000000 |
| REG_9.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_9.d | 0.000000 | 0.000000 | 0.000000 |
| REG_8.q | 0.000000 | 1.000000 | 0.500000 |
| REG_8.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_8.d | 0.000000 | 0.906385 | 0.453193 |
| REG_7.q | 0.000000 | 0.000000 | 0.000000 |
| REG_7.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_7.d | 0.000000 | 0.000000 | 0.000000 |
| REG_6.q | 0.000000 | 0.000000 | 0.000000 |
| REG_6.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_6.d | 0.000000 | 0.000000 | 0.000000 |
| REG_5.q | 0.000000 | 1.000000 | 0.500000 |
| REG_5.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_5.d | 0.000000 | 0.906385 | 0.453193 |
| REG_4.q | 0.000000 | 1.000000 | 0.500000 |
| REG_4.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_4.d | 0.000000 | 0.906385 | 0.453193 |
| REG_3.q | 0.000000 | 0.000000 | 0.000000 |
| REG_3.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_3.d | 0.000000 | 0.000000 | 0.000000 |
| REG_2.q | 0.000000 | 1.000000 | 0.500000 |
| REG_2.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_2.d | 0.000000 | 0.906385 | 0.453193 |
| REG_1.q | 0.000000 | 1.000000 | 0.500000 |
| REG_1.clk | 1.000000 | 0.000000 | 0.500000 |
| REG_1.d | 0.000000 | 0.906385 | 0.453193 |
| MUX2_5.q | 0.000000 | 0.000000 | 0.000000 |
| MUX2_5.sel | 1.000000 | 0.000000 | 0.500000 |
| MUX2_5.b | 0.000000 | 0.000000 | 0.000000 |
| MUX2_5.a | 0.000000 | 0.000000 | 0.000000 |
| MUX2_4.q | 0.000000 | 0.000000 | 0.000000 |
| MUX2_4.sel | 1.000000 | 0.000000 | 0.500000 |
| MUX2_4.b | 0.000000 | 0.000000 | 0.000000 |
| MUX2_4.a | 0.000000 | 0.000000 | 0.000000 |
| MUX2_3.q | 0.000000 | 0.000000 | 0.000000 |
| MUX2_3.sel | 1.000000 | 0.000000 | 0.500000 |
| MUX2_3.b | 0.000000 | 0.000000 | 0.000000 |
| MUX2_3.a | 0.000000 | 0.000000 | 0.000000 |
| MUX2_2.q | 0.000000 | 0.000000 | 0.000000 |
| MUX2_2.sel | 1.000000 | 0.000000 | 0.500000 |
| MUX2_2.b | 0.000000 | 0.000000 | 0.000000 |
| MUX2_2.a | 0.000000 | 0.000000 | 0.000000 |
| MUX2_1.q | 0.000000 | 0.000000 | 0.000000 |
| MUX2_1.sel | 1.000000 | 0.000000 | 0.500000 |
| MUX2_1.b | 0.000000 | 0.000000 | 0.000000 |
| MUX2_1.a | 0.000000 | 0.000000 | 0.000000 |
| ADD_5.q | 0.000000 | 0.000000 | 0.000000 |
| ADD_5.b | 0.000000 | 0.000000 | 0.000000 |
| ADD_5.a | 1.000000 | 0.000000 | 0.500000 |
| ADD_4.q | 0.000000 | 0.000000 | 0.000000 |
| ADD_4.b | 1.000000 | 0.000000 | 0.500000 |
| ADD_4.a | 0.000000 | 0.000000 | 0.000000 |
| ADD_3.q | 0.000000 | 0.906385 | 0.453193 |
| ADD_3.b | 0.000000 | 0.000000 | 0.000000 |
| ADD_3.a | 0.000000 | 0.000000 | 0.000000 |
| ADD_2.q | 0.000000 | 0.906385 | 0.453193 |
| ADD_2.b | 0.000000 | 0.000000 | 0.000000 |
| ADD_2.a | 0.000000 | 0.000000 | 0.000000 |
| ADD_1.q | 0.000000 | 0.906385 | 0.453193 |
| ADD_1.b | 0.000000 | 0.000000 | 0.000000 |
| ADD_1.a | 0.000000 | 0.000000 | 0.000000 |
| SUB_5.q | 0.000000 | 0.906385 | 0.453193 |
| SUB_5.b | 0.000000 | 0.000000 | 0.000000 |
| SUB_5.a | 0.000000 | 0.000000 | 0.000000 |
| SUB_4.q | 0.000000 | 0.906385 | 0.453193 |
| SUB_4.b | 0.000000 | 0.000000 | 0.000000 |
| SUB_4.a | 0.000000 | 0.000000 | 0.000000 |
| SUB_3.q | 0.000000 | 0.000000 | 0.000000 |
| SUB_3.b | 0.000000 | 0.000000 | 0.000000 |
| SUB_3.a | 1.000000 | 0.000000 | 0.500000 |
| SUB_2.q | 0.000000 | 0.000000 | 0.000000 |
| SUB_2.b | 0.000000 | 0.000000 | 0.000000 |
| SUB_2.a | 1.000000 | 0.000000 | 0.500000 |
| SUB_1.q | 0.000000 | 0.000000 | 0.000000 |
| SUB_1.b | 0.000000 | 0.000000 | 0.000000 |
| SUB_1.a | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.CLK | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.C_MUX2_5_sel | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.C_MUX2_4_sel | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.C_MUX2_3_sel | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.C_MUX2_2_sel | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.C_MUX2_1_sel | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.pri_out_4 | 0.000000 | 1.000000 | 0.500000 |
| CIRCUIT.pri_out_3 | 0.000000 | 1.000000 | 0.500000 |
| CIRCUIT.pri_out_2 | 0.000000 | 1.000000 | 0.500000 |
| CIRCUIT.pri_out_1 | 0.000000 | 1.000000 | 0.500000 |
| CIRCUIT.pri_out_0 | 0.000000 | 1.000000 | 0.500000 |
| CIRCUIT.pri_in_4 | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.pri_in_3 | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.pri_in_2 | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.pri_in_1 | 1.000000 | 0.000000 | 0.500000 |
| CIRCUIT.pri_in_0 | 1.000000 | 0.000000 | 0.500000 |
| Global measures | 0.107580 | 0.154407 | 0.016611 |
| Arithmetic average | 0.322917 | 0.198582 | 0.260749 |
| #Nodes(Total=621) | C(101/16.3%) | O(160/25.8%) | T(0/0.0%) |
| This table was automatically generated by RTL-ADFT system Copyright © 2000-2002 Josef Strnadel (strnadel@fit.vutbr.cz) Faculty of Information Technology Brno University of Technology Czech Republic | |||