-- ------------------------------------------------------------------------- -- -- This circuit was generated by CirGen -- -- ------------------------------------------------------------------------- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- ---------------------------------------------------------------------------- -- Entity declaration -- ---------------------------------------------------------------------------- entity CIRCUIT is port( -- Primary input gates PRI_IN_0 : in std_logic_vector(15 downto 0); PRI_IN_1 : in std_logic_vector(31 downto 0); PRI_IN_2 : in std_logic_vector(31 downto 0); PRI_IN_3 : in std_logic_vector(15 downto 0); PRI_IN_4 : in std_logic_vector(15 downto 0); PRI_IN_5 : in std_logic_vector(15 downto 0); PRI_IN_6 : in std_logic_vector(15 downto 0); PRI_IN_7 : in std_logic_vector(15 downto 0); PRI_IN_8 : in std_logic_vector(15 downto 0); PRI_IN_9 : in std_logic_vector(31 downto 0); PRI_IN_10 : in std_logic_vector(15 downto 0); PRI_IN_11 : in std_logic_vector(15 downto 0); PRI_IN_12 : in std_logic_vector(15 downto 0); PRI_IN_13 : in std_logic_vector(15 downto 0); PRI_IN_14 : in std_logic_vector(15 downto 0); PRI_IN_15 : in std_logic_vector(15 downto 0); PRI_IN_16 : in std_logic_vector(15 downto 0); PRI_IN_17 : in std_logic_vector(15 downto 0); PRI_IN_18 : in std_logic_vector(15 downto 0); PRI_IN_19 : in std_logic_vector(15 downto 0); PRI_IN_20 : in std_logic_vector(15 downto 0); PRI_IN_21 : in std_logic_vector(31 downto 0); PRI_IN_22 : in std_logic_vector(15 downto 0); PRI_IN_23 : in std_logic_vector(15 downto 0); PRI_IN_24 : in std_logic_vector(31 downto 0); PRI_IN_25 : in std_logic_vector(15 downto 0); PRI_IN_26 : in std_logic_vector(31 downto 0); PRI_IN_27 : in std_logic_vector(15 downto 0); PRI_IN_28 : in std_logic_vector(15 downto 0); PRI_IN_29 : in std_logic_vector(15 downto 0); PRI_IN_30 : in std_logic_vector(31 downto 0); PRI_IN_31 : in std_logic_vector(15 downto 0); PRI_IN_32 : in std_logic_vector(31 downto 0); PRI_IN_33 : in std_logic_vector(15 downto 0); PRI_IN_34 : in std_logic_vector(31 downto 0); -- Primary output gates PRI_OUT_0 : out std_logic_vector(15 downto 0); PRI_OUT_1 : out std_logic_vector(31 downto 0); PRI_OUT_2 : out std_logic_vector(31 downto 0); PRI_OUT_3 : out std_logic_vector(31 downto 0); PRI_OUT_4 : out std_logic_vector(31 downto 0); PRI_OUT_5 : out std_logic_vector(31 downto 0); PRI_OUT_6 : out std_logic_vector(15 downto 0); PRI_OUT_7 : out std_logic_vector(31 downto 0); PRI_OUT_8 : out std_logic_vector(15 downto 0); PRI_OUT_9 : out std_logic_vector(31 downto 0); PRI_OUT_10 : out std_logic_vector(15 downto 0); PRI_OUT_11 : out std_logic_vector(31 downto 0); PRI_OUT_12 : out std_logic_vector(31 downto 0); PRI_OUT_13 : out std_logic_vector(15 downto 0); PRI_OUT_14 : out std_logic_vector(15 downto 0); PRI_OUT_15 : out std_logic_vector(31 downto 0); PRI_OUT_16 : out std_logic_vector(15 downto 0); PRI_OUT_17 : out std_logic_vector(15 downto 0); PRI_OUT_18 : out std_logic_vector(31 downto 0); PRI_OUT_19 : out std_logic_vector(15 downto 0); PRI_OUT_20 : out std_logic_vector(31 downto 0); PRI_OUT_21 : out std_logic_vector(31 downto 0); PRI_OUT_22 : out std_logic_vector(31 downto 0); PRI_OUT_23 : out std_logic_vector(31 downto 0); PRI_OUT_24 : out std_logic_vector(31 downto 0); PRI_OUT_25 : out std_logic_vector(31 downto 0); PRI_OUT_26 : out std_logic_vector(15 downto 0); PRI_OUT_27 : out std_logic_vector(15 downto 0); PRI_OUT_28 : out std_logic_vector(15 downto 0); PRI_OUT_29 : out std_logic_vector(15 downto 0); PRI_OUT_30 : out std_logic_vector(31 downto 0); PRI_OUT_31 : out std_logic_vector(31 downto 0); PRI_OUT_32 : out std_logic_vector(31 downto 0); PRI_OUT_33 : out std_logic_vector(15 downto 0); PRI_OUT_34 : out std_logic_vector(31 downto 0); -- Primary control gates C_MUX2_1_SEL : in std_logic; C_MUX2_2_SEL : in std_logic; C_MUX2_3_SEL : in std_logic; C_MUX2_4_SEL : in std_logic; C_MUX2_5_SEL : in std_logic; C_MUX2_6_SEL : in std_logic; C_MUX2_7_SEL : in std_logic; C_MUX2_8_SEL : in std_logic; C_MUX2_9_SEL : in std_logic; C_MUX2_10_SEL : in std_logic; C_MUX2_11_SEL : in std_logic; C_MUX2_12_SEL : in std_logic; C_MUX2_13_SEL : in std_logic; C_MUX2_14_SEL : in std_logic; C_MUX2_15_SEL : in std_logic; C_MUX2_16_SEL : in std_logic; C_MUX2_17_SEL : in std_logic; C_MUX2_18_SEL : in std_logic; C_MUX2_19_SEL : in std_logic; C_MUX2_20_SEL : in std_logic; C_MUX2_21_SEL : in std_logic; C_MUX2_22_SEL : in std_logic; C_MUX2_23_SEL : in std_logic; C_MUX2_24_SEL : in std_logic; C_MUX2_25_SEL : in std_logic; C_MUX2_26_SEL : in std_logic; C_MUX2_27_SEL : in std_logic; C_MUX2_28_SEL : in std_logic; C_MUX2_29_SEL : in std_logic; C_MUX2_30_SEL : in std_logic; C_MUX2_31_SEL : in std_logic; C_MUX2_32_SEL : in std_logic; C_MUX2_33_SEL : in std_logic; C_MUX2_34_SEL : in std_logic; C_MUX2_35_SEL : in std_logic; C_MUX2_36_SEL : in std_logic; C_MUX2_37_SEL : in std_logic; C_MUX2_38_SEL : in std_logic; C_MUX2_39_SEL : in std_logic; C_MUX2_40_SEL : in std_logic; C_MUX2_41_SEL : in std_logic; C_MUX2_42_SEL : in std_logic; C_MUX2_43_SEL : in std_logic; C_MUX2_44_SEL : in std_logic; C_MUX2_45_SEL : in std_logic; C_MUX2_46_SEL : in std_logic; C_MUX2_47_SEL : in std_logic; C_MUX2_48_SEL : in std_logic; C_MUX2_49_SEL : in std_logic; C_MUX2_50_SEL : in std_logic; C_MUX2_51_SEL : in std_logic; C_MUX2_52_SEL : in std_logic; C_MUX2_53_SEL : in std_logic; C_MUX2_54_SEL : in std_logic; C_MUX2_55_SEL : in std_logic; C_MUX2_56_SEL : in std_logic; C_MUX2_57_SEL : in std_logic; C_MUX2_58_SEL : in std_logic; C_MUX2_59_SEL : in std_logic; C_MUX2_60_SEL : in std_logic; C_MUX2_61_SEL : in std_logic; C_MUX2_62_SEL : in std_logic; C_MUX2_63_SEL : in std_logic; C_MUX2_64_SEL : in std_logic; C_MUX2_65_SEL : in std_logic; C_MUX2_66_SEL : in std_logic; C_MUX2_67_SEL : in std_logic; C_MUX2_68_SEL : in std_logic; C_MUX2_69_SEL : in std_logic; C_MUX2_70_SEL : in std_logic; CLK : in std_logic ); end entity CIRCUIT; -- ---------------------------------------------------------------------------- -- Architecture declaration -- ---------------------------------------------------------------------------- architecture CIRCUIT_arch of CIRCUIT is -- ############################# USED COMPONENTS ############################## component ADD generic ( width_a : positive); port( a : in std_logic_vector (width_a - 1 downto 0); b : in std_logic_vector (width_a - 1 downto 0); q : out std_logic_vector(width_a - 1 downto 0) ); end component ADD; component MUL generic ( width_a : positive; width_b : positive); port( -- Inputs a : in std_logic_vector(width_a - 1 downto 0); b : in std_logic_vector(width_a - 1 downto 0); -- Outputs q : out std_logic_vector(width_b - 1 downto 0) ); end component MUL; component MUX2 generic ( width_a : positive); port( -- Inputs a : in std_logic_vector(width_a - 1 downto 0); b : in std_logic_vector(width_a - 1 downto 0); sel : in std_logic; -- Outputs q : out std_logic_vector(width_a - 1 downto 0) ); end component MUX2; component REG generic ( width_a : positive); port( -- Inputs d : in std_logic_vector(width_a - 1 downto 0); clk : in std_logic; -- Outputs q : out std_logic_vector(width_a - 1 downto 0) ); end component REG; component SUB generic ( width_a : positive); port( -- Inputs a : in std_logic_vector(width_a - 1 downto 0); b : in std_logic_vector(width_a - 1 downto 0); -- Outputs q : out std_logic_vector(width_a - 1 downto 0) ); end component SUB; -- ############################# CONNECTIONS ############################## -- DATA CONNECTIONS signal reg_2_q_c : std_logic_vector(15 downto 0); signal sub_39_q_c : std_logic_vector(31 downto 0); signal reg_4_q_c : std_logic_vector(31 downto 0); signal reg_5_q_c : std_logic_vector(31 downto 0); signal reg_6_q_c : std_logic_vector(31 downto 0); signal sub_48_q_c : std_logic_vector(31 downto 0); signal reg_24_q_c : std_logic_vector(15 downto 0); signal mux2_48_q_c : std_logic_vector(31 downto 0); signal reg_36_q_c : std_logic_vector(15 downto 0); signal reg_37_q_c : std_logic_vector(31 downto 0); signal reg_15_q_c : std_logic_vector(15 downto 0); signal mul_27_q_c : std_logic_vector(31 downto 0); signal reg_41_q_c : std_logic_vector(31 downto 0); signal reg_42_q_c : std_logic_vector(15 downto 0); signal mux2_9_q_c : std_logic_vector(15 downto 0); signal mux2_69_q_c : std_logic_vector(31 downto 0); signal mul_35_q_c : std_logic_vector(31 downto 0); signal mux2_2_q_c : std_logic_vector(15 downto 0); signal reg_27_q_c : std_logic_vector(31 downto 0); signal reg_56_q_c : std_logic_vector(31 downto 0); signal reg_57_q_c : std_logic_vector(31 downto 0); signal reg_58_q_c : std_logic_vector(31 downto 0); signal reg_59_q_c : std_logic_vector(31 downto 0); signal reg_60_q_c : std_logic_vector(31 downto 0); signal reg_51_q_c : std_logic_vector(15 downto 0); signal reg_20_q_c : std_logic_vector(15 downto 0); signal reg_61_q_c : std_logic_vector(15 downto 0); signal reg_34_q_c : std_logic_vector(31 downto 0); signal reg_62_q_c : std_logic_vector(31 downto 0); signal reg_63_q_c : std_logic_vector(31 downto 0); signal mux2_18_q_c : std_logic_vector(15 downto 0); signal mux2_13_q_c : std_logic_vector(15 downto 0); signal reg_54_q_c : std_logic_vector(15 downto 0); signal mux2_25_q_c : std_logic_vector(15 downto 0); signal reg_64_q_c : std_logic_vector(15 downto 0); signal reg_65_q_c : std_logic_vector(15 downto 0); signal mux2_22_q_c : std_logic_vector(15 downto 0); signal reg_66_q_c : std_logic_vector(15 downto 0); signal mux2_11_q_c : std_logic_vector(15 downto 0); signal mux2_17_q_c : std_logic_vector(15 downto 0); signal mux2_10_q_c : std_logic_vector(15 downto 0); signal mux2_34_q_c : std_logic_vector(15 downto 0); signal mux2_31_q_c : std_logic_vector(15 downto 0); signal reg_67_q_c : std_logic_vector(15 downto 0); signal reg_55_q_c : std_logic_vector(15 downto 0); signal reg_21_q_c : std_logic_vector(15 downto 0); signal reg_53_q_c : std_logic_vector(15 downto 0); signal mux2_12_q_c : std_logic_vector(15 downto 0); signal reg_70_q_c : std_logic_vector(15 downto 0); signal mux2_20_q_c : std_logic_vector(15 downto 0); signal reg_72_q_c : std_logic_vector(15 downto 0); signal reg_18_q_c : std_logic_vector(15 downto 0); signal mux2_28_q_c : std_logic_vector(15 downto 0); signal mux2_6_q_c : std_logic_vector(15 downto 0); signal reg_14_q_c : std_logic_vector(15 downto 0); signal reg_75_q_c : std_logic_vector(15 downto 0); signal reg_76_q_c : std_logic_vector(15 downto 0); signal reg_77_q_c : std_logic_vector(15 downto 0); signal sub_26_q_c : std_logic_vector(15 downto 0); signal reg_79_q_c : std_logic_vector(15 downto 0); signal reg_80_q_c : std_logic_vector(15 downto 0); signal mux2_8_q_c : std_logic_vector(15 downto 0); signal add_25_q_c : std_logic_vector(15 downto 0); signal reg_25_q_c : std_logic_vector(15 downto 0); signal reg_1_q_c : std_logic_vector(15 downto 0); signal mux2_5_q_c : std_logic_vector(15 downto 0); signal add_28_q_c : std_logic_vector(15 downto 0); signal reg_83_q_c : std_logic_vector(15 downto 0); signal mux2_30_q_c : std_logic_vector(15 downto 0); signal reg_86_q_c : std_logic_vector(15 downto 0); signal add_1_q_c : std_logic_vector(15 downto 0); signal mux2_14_q_c : std_logic_vector(15 downto 0); signal mux2_35_q_c : std_logic_vector(15 downto 0); signal reg_19_q_c : std_logic_vector(15 downto 0); signal mux2_3_q_c : std_logic_vector(15 downto 0); signal reg_91_q_c : std_logic_vector(15 downto 0); signal mux2_32_q_c : std_logic_vector(15 downto 0); signal reg_92_q_c : std_logic_vector(15 downto 0); signal mux2_19_q_c : std_logic_vector(15 downto 0); signal reg_93_q_c : std_logic_vector(15 downto 0); signal reg_94_q_c : std_logic_vector(15 downto 0); signal reg_22_q_c : std_logic_vector(15 downto 0); signal add_7_q_c : std_logic_vector(15 downto 0); signal mux2_26_q_c : std_logic_vector(15 downto 0); signal reg_71_q_c : std_logic_vector(15 downto 0); signal add_3_q_c : std_logic_vector(15 downto 0); signal mux2_33_q_c : std_logic_vector(15 downto 0); signal reg_97_q_c : std_logic_vector(15 downto 0); signal reg_69_q_c : std_logic_vector(15 downto 0); signal add_5_q_c : std_logic_vector(15 downto 0); signal mux2_15_q_c : std_logic_vector(15 downto 0); signal reg_12_q_c : std_logic_vector(15 downto 0); signal mux2_29_q_c : std_logic_vector(15 downto 0); signal add_2_q_c : std_logic_vector(15 downto 0); signal mux2_16_q_c : std_logic_vector(15 downto 0); signal sub_16_q_c : std_logic_vector(15 downto 0); signal mux2_27_q_c : std_logic_vector(15 downto 0); signal reg_52_q_c : std_logic_vector(15 downto 0); signal reg_11_q_c : std_logic_vector(15 downto 0); signal reg_43_q_c : std_logic_vector(15 downto 0); signal mux2_24_q_c : std_logic_vector(15 downto 0); signal mux2_4_q_c : std_logic_vector(15 downto 0); signal reg_68_q_c : std_logic_vector(15 downto 0); signal mux2_21_q_c : std_logic_vector(15 downto 0); signal sub_20_q_c : std_logic_vector(15 downto 0); signal add_4_q_c : std_logic_vector(15 downto 0); signal reg_17_q_c : std_logic_vector(15 downto 0); signal reg_13_q_c : std_logic_vector(15 downto 0); signal reg_16_q_c : std_logic_vector(15 downto 0); signal reg_87_q_c : std_logic_vector(15 downto 0); signal reg_23_q_c : std_logic_vector(15 downto 0); signal reg_73_q_c : std_logic_vector(15 downto 0); signal reg_74_q_c : std_logic_vector(15 downto 0); signal reg_85_q_c : std_logic_vector(15 downto 0); signal reg_84_q_c : std_logic_vector(15 downto 0); signal sub_66_q_c : std_logic_vector(31 downto 0); signal mul_19_q_c : std_logic_vector(31 downto 0); signal reg_103_q_c : std_logic_vector(31 downto 0); signal reg_105_q_c : std_logic_vector(31 downto 0); signal add_36_q_c : std_logic_vector(31 downto 0); signal mux2_42_q_c : std_logic_vector(31 downto 0); signal mux2_61_q_c : std_logic_vector(31 downto 0); signal mux2_51_q_c : std_logic_vector(31 downto 0); signal reg_109_q_c : std_logic_vector(31 downto 0); signal mux2_66_q_c : std_logic_vector(31 downto 0); signal mux2_49_q_c : std_logic_vector(31 downto 0); signal reg_115_q_c : std_logic_vector(31 downto 0); signal mul_14_q_c : std_logic_vector(31 downto 0); signal mul_28_q_c : std_logic_vector(31 downto 0); signal sub_63_q_c : std_logic_vector(31 downto 0); signal reg_121_q_c : std_logic_vector(31 downto 0); signal reg_122_q_c : std_logic_vector(31 downto 0); signal mux2_70_q_c : std_logic_vector(31 downto 0); signal add_41_q_c : std_logic_vector(31 downto 0); signal reg_124_q_c : std_logic_vector(31 downto 0); signal reg_125_q_c : std_logic_vector(31 downto 0); signal reg_126_q_c : std_logic_vector(31 downto 0); signal reg_112_q_c : std_logic_vector(31 downto 0); signal add_61_q_c : std_logic_vector(31 downto 0); signal add_42_q_c : std_logic_vector(31 downto 0); signal mux2_58_q_c : std_logic_vector(31 downto 0); signal add_70_q_c : std_logic_vector(31 downto 0); signal reg_130_q_c : std_logic_vector(31 downto 0); signal sub_37_q_c : std_logic_vector(31 downto 0); signal reg_110_q_c : std_logic_vector(31 downto 0); signal reg_132_q_c : std_logic_vector(31 downto 0); signal mul_25_q_c : std_logic_vector(31 downto 0); signal add_52_q_c : std_logic_vector(31 downto 0); signal mux2_55_q_c : std_logic_vector(31 downto 0); signal sub_43_q_c : std_logic_vector(31 downto 0); signal reg_136_q_c : std_logic_vector(31 downto 0); signal reg_137_q_c : std_logic_vector(31 downto 0); signal mux2_64_q_c : std_logic_vector(31 downto 0); signal sub_52_q_c : std_logic_vector(31 downto 0); signal mux2_39_q_c : std_logic_vector(31 downto 0); signal mul_21_q_c : std_logic_vector(31 downto 0); signal mul_23_q_c : std_logic_vector(31 downto 0); signal mul_15_q_c : std_logic_vector(31 downto 0); signal mux2_67_q_c : std_logic_vector(31 downto 0); signal reg_44_q_c : std_logic_vector(31 downto 0); signal reg_50_q_c : std_logic_vector(31 downto 0); signal reg_141_q_c : std_logic_vector(31 downto 0); signal add_40_q_c : std_logic_vector(31 downto 0); signal mux2_53_q_c : std_logic_vector(31 downto 0); signal reg_143_q_c : std_logic_vector(31 downto 0); signal reg_144_q_c : std_logic_vector(31 downto 0); signal mux2_45_q_c : std_logic_vector(31 downto 0); signal mul_4_q_c : std_logic_vector(31 downto 0); signal mul_33_q_c : std_logic_vector(31 downto 0); signal add_38_q_c : std_logic_vector(31 downto 0); signal mux2_38_q_c : std_logic_vector(31 downto 0); signal reg_35_q_c : std_logic_vector(31 downto 0); signal add_67_q_c : std_logic_vector(31 downto 0); signal reg_26_q_c : std_logic_vector(31 downto 0); signal mux2_52_q_c : std_logic_vector(31 downto 0); signal mux2_46_q_c : std_logic_vector(31 downto 0); signal mul_26_q_c : std_logic_vector(31 downto 0); signal mul_32_q_c : std_logic_vector(31 downto 0); signal sub_58_q_c : std_logic_vector(31 downto 0); signal mux2_54_q_c : std_logic_vector(31 downto 0); signal sub_41_q_c : std_logic_vector(31 downto 0); signal mux2_59_q_c : std_logic_vector(31 downto 0); signal mux2_43_q_c : std_logic_vector(31 downto 0); signal mux2_36_q_c : std_logic_vector(31 downto 0); signal sub_40_q_c : std_logic_vector(31 downto 0); signal add_53_q_c : std_logic_vector(31 downto 0); signal sub_61_q_c : std_logic_vector(31 downto 0); signal mul_7_q_c : std_logic_vector(31 downto 0); signal sub_49_q_c : std_logic_vector(31 downto 0); signal mux2_44_q_c : std_logic_vector(31 downto 0); signal add_57_q_c : std_logic_vector(31 downto 0); signal mul_5_q_c : std_logic_vector(31 downto 0); signal add_69_q_c : std_logic_vector(31 downto 0); signal mux2_60_q_c : std_logic_vector(31 downto 0); signal mul_1_q_c : std_logic_vector(31 downto 0); signal mux2_63_q_c : std_logic_vector(31 downto 0); signal sub_65_q_c : std_logic_vector(31 downto 0); signal sub_69_q_c : std_logic_vector(31 downto 0); signal reg_40_q_c : std_logic_vector(31 downto 0); signal reg_31_q_c : std_logic_vector(31 downto 0); signal mux2_68_q_c : std_logic_vector(31 downto 0); signal reg_148_q_c : std_logic_vector(31 downto 0); signal reg_30_q_c : std_logic_vector(31 downto 0); signal reg_45_q_c : std_logic_vector(31 downto 0); signal mul_10_q_c : std_logic_vector(31 downto 0); signal mul_17_q_c : std_logic_vector(31 downto 0); signal reg_46_q_c : std_logic_vector(31 downto 0); signal reg_28_q_c : std_logic_vector(31 downto 0); signal mux2_40_q_c : std_logic_vector(31 downto 0); signal reg_49_q_c : std_logic_vector(31 downto 0); signal mux2_57_q_c : std_logic_vector(31 downto 0); signal mux2_62_q_c : std_logic_vector(31 downto 0); signal sub_59_q_c : std_logic_vector(31 downto 0); signal mul_29_q_c : std_logic_vector(31 downto 0); signal add_48_q_c : std_logic_vector(31 downto 0); signal mul_9_q_c : std_logic_vector(31 downto 0); signal mux2_65_q_c : std_logic_vector(31 downto 0); signal mux2_47_q_c : std_logic_vector(31 downto 0); signal reg_48_q_c : std_logic_vector(31 downto 0); signal reg_33_q_c : std_logic_vector(31 downto 0); signal reg_104_q_c : std_logic_vector(31 downto 0); signal add_51_q_c : std_logic_vector(31 downto 0); signal sub_57_q_c : std_logic_vector(31 downto 0); signal add_44_q_c : std_logic_vector(31 downto 0); signal reg_29_q_c : std_logic_vector(31 downto 0); signal mux2_37_q_c : std_logic_vector(31 downto 0); signal mul_34_q_c : std_logic_vector(31 downto 0); signal mux2_50_q_c : std_logic_vector(31 downto 0); signal add_43_q_c : std_logic_vector(31 downto 0); signal reg_111_q_c : std_logic_vector(31 downto 0); signal reg_32_q_c : std_logic_vector(31 downto 0); signal reg_149_q_c : std_logic_vector(31 downto 0); signal reg_47_q_c : std_logic_vector(31 downto 0); signal mux2_41_q_c : std_logic_vector(31 downto 0); signal mux2_56_q_c : std_logic_vector(31 downto 0); signal reg_167_q_c : std_logic_vector(15 downto 0); signal mux2_1_q_c : std_logic_vector(15 downto 0); signal reg_168_q_c : std_logic_vector(15 downto 0); signal mux2_7_q_c : std_logic_vector(15 downto 0); signal mux2_23_q_c : std_logic_vector(15 downto 0); signal add_9_q_c : std_logic_vector(15 downto 0); signal reg_170_q_c : std_logic_vector(15 downto 0); signal add_18_q_c : std_logic_vector(15 downto 0); signal sub_7_q_c : std_logic_vector(15 downto 0); signal sub_8_q_c : std_logic_vector(15 downto 0); signal sub_14_q_c : std_logic_vector(15 downto 0); signal sub_4_q_c : std_logic_vector(15 downto 0); signal reg_3_q_c : std_logic_vector(31 downto 0); signal sub_54_q_c : std_logic_vector(31 downto 0); signal mul_20_q_c : std_logic_vector(31 downto 0); signal sub_64_q_c : std_logic_vector(31 downto 0); signal reg_7_q_c : std_logic_vector(31 downto 0); signal reg_8_q_c : std_logic_vector(31 downto 0); signal reg_9_q_c : std_logic_vector(31 downto 0); signal reg_10_q_c : std_logic_vector(31 downto 0); signal sub_10_q_c : std_logic_vector(15 downto 0); signal sub_12_q_c : std_logic_vector(15 downto 0); signal sub_17_q_c : std_logic_vector(15 downto 0); signal sub_19_q_c : std_logic_vector(15 downto 0); signal sub_27_q_c : std_logic_vector(15 downto 0); signal sub_29_q_c : std_logic_vector(15 downto 0); signal sub_30_q_c : std_logic_vector(15 downto 0); signal sub_34_q_c : std_logic_vector(15 downto 0); signal sub_35_q_c : std_logic_vector(15 downto 0); signal add_11_q_c : std_logic_vector(15 downto 0); signal add_13_q_c : std_logic_vector(15 downto 0); signal add_16_q_c : std_logic_vector(15 downto 0); signal add_20_q_c : std_logic_vector(15 downto 0); signal add_21_q_c : std_logic_vector(15 downto 0); signal add_29_q_c : std_logic_vector(15 downto 0); signal sub_36_q_c : std_logic_vector(31 downto 0); signal sub_67_q_c : std_logic_vector(31 downto 0); signal sub_68_q_c : std_logic_vector(31 downto 0); signal add_39_q_c : std_logic_vector(31 downto 0); signal add_49_q_c : std_logic_vector(31 downto 0); signal add_50_q_c : std_logic_vector(31 downto 0); signal add_66_q_c : std_logic_vector(31 downto 0); signal add_68_q_c : std_logic_vector(31 downto 0); signal mul_3_q_c : std_logic_vector(31 downto 0); signal mul_6_q_c : std_logic_vector(31 downto 0); signal sub_25_q_c : std_logic_vector(15 downto 0); signal sub_62_q_c : std_logic_vector(31 downto 0); signal reg_38_q_c : std_logic_vector(31 downto 0); signal reg_39_q_c : std_logic_vector(31 downto 0); signal add_37_q_c : std_logic_vector(31 downto 0); signal add_58_q_c : std_logic_vector(31 downto 0); signal add_8_q_c : std_logic_vector(15 downto 0); signal add_27_q_c : std_logic_vector(15 downto 0); signal sub_38_q_c : std_logic_vector(31 downto 0); signal sub_44_q_c : std_logic_vector(31 downto 0); signal sub_53_q_c : std_logic_vector(31 downto 0); signal add_60_q_c : std_logic_vector(31 downto 0); signal mul_11_q_c : std_logic_vector(31 downto 0); signal mul_18_q_c : std_logic_vector(31 downto 0); signal mul_30_q_c : std_logic_vector(31 downto 0); signal sub_31_q_c : std_logic_vector(15 downto 0); signal add_6_q_c : std_logic_vector(15 downto 0); signal add_31_q_c : std_logic_vector(15 downto 0); signal add_32_q_c : std_logic_vector(15 downto 0); signal sub_2_q_c : std_logic_vector(15 downto 0); signal add_46_q_c : std_logic_vector(31 downto 0); signal sub_60_q_c : std_logic_vector(31 downto 0); signal mul_12_q_c : std_logic_vector(31 downto 0); signal add_62_q_c : std_logic_vector(31 downto 0); signal sub_51_q_c : std_logic_vector(31 downto 0); signal sub_1_q_c : std_logic_vector(15 downto 0); signal add_63_q_c : std_logic_vector(31 downto 0); signal sub_42_q_c : std_logic_vector(31 downto 0); signal sub_33_q_c : std_logic_vector(15 downto 0); signal add_15_q_c : std_logic_vector(15 downto 0); signal sub_23_q_c : std_logic_vector(15 downto 0); signal sub_18_q_c : std_logic_vector(15 downto 0); signal add_12_q_c : std_logic_vector(15 downto 0); signal sub_6_q_c : std_logic_vector(15 downto 0); signal sub_21_q_c : std_logic_vector(15 downto 0); signal add_14_q_c : std_logic_vector(15 downto 0); signal add_24_q_c : std_logic_vector(15 downto 0); signal add_23_q_c : std_logic_vector(15 downto 0); signal add_35_q_c : std_logic_vector(15 downto 0); signal sub_13_q_c : std_logic_vector(15 downto 0); signal sub_11_q_c : std_logic_vector(15 downto 0); signal sub_5_q_c : std_logic_vector(15 downto 0); signal reg_78_q_c : std_logic_vector(15 downto 0); signal add_19_q_c : std_logic_vector(15 downto 0); signal add_33_q_c : std_logic_vector(15 downto 0); signal reg_81_q_c : std_logic_vector(15 downto 0); signal reg_82_q_c : std_logic_vector(15 downto 0); signal add_30_q_c : std_logic_vector(15 downto 0); signal sub_22_q_c : std_logic_vector(15 downto 0); signal sub_24_q_c : std_logic_vector(15 downto 0); signal sub_9_q_c : std_logic_vector(15 downto 0); signal sub_32_q_c : std_logic_vector(15 downto 0); signal reg_88_q_c : std_logic_vector(15 downto 0); signal reg_89_q_c : std_logic_vector(15 downto 0); signal reg_90_q_c : std_logic_vector(15 downto 0); signal sub_3_q_c : std_logic_vector(15 downto 0); signal sub_15_q_c : std_logic_vector(15 downto 0); signal sub_28_q_c : std_logic_vector(15 downto 0); signal add_10_q_c : std_logic_vector(15 downto 0); signal reg_95_q_c : std_logic_vector(15 downto 0); signal reg_96_q_c : std_logic_vector(15 downto 0); signal add_26_q_c : std_logic_vector(15 downto 0); signal reg_98_q_c : std_logic_vector(15 downto 0); signal reg_99_q_c : std_logic_vector(15 downto 0); signal reg_100_q_c : std_logic_vector(15 downto 0); signal reg_101_q_c : std_logic_vector(31 downto 0); signal reg_102_q_c : std_logic_vector(31 downto 0); signal mul_13_q_c : std_logic_vector(31 downto 0); signal mul_31_q_c : std_logic_vector(31 downto 0); signal add_65_q_c : std_logic_vector(31 downto 0); signal reg_106_q_c : std_logic_vector(31 downto 0); signal reg_107_q_c : std_logic_vector(31 downto 0); signal reg_108_q_c : std_logic_vector(31 downto 0); signal mul_8_q_c : std_logic_vector(31 downto 0); signal sub_47_q_c : std_logic_vector(31 downto 0); signal add_54_q_c : std_logic_vector(31 downto 0); signal mul_24_q_c : std_logic_vector(31 downto 0); signal reg_113_q_c : std_logic_vector(31 downto 0); signal reg_114_q_c : std_logic_vector(31 downto 0); signal mul_22_q_c : std_logic_vector(31 downto 0); signal reg_116_q_c : std_logic_vector(31 downto 0); signal reg_117_q_c : std_logic_vector(31 downto 0); signal reg_118_q_c : std_logic_vector(31 downto 0); signal reg_119_q_c : std_logic_vector(31 downto 0); signal reg_120_q_c : std_logic_vector(31 downto 0); signal sub_46_q_c : std_logic_vector(31 downto 0); signal add_45_q_c : std_logic_vector(31 downto 0); signal reg_123_q_c : std_logic_vector(31 downto 0); signal add_56_q_c : std_logic_vector(31 downto 0); signal add_55_q_c : std_logic_vector(31 downto 0); signal sub_45_q_c : std_logic_vector(31 downto 0); signal reg_127_q_c : std_logic_vector(31 downto 0); signal reg_128_q_c : std_logic_vector(31 downto 0); signal reg_129_q_c : std_logic_vector(31 downto 0); signal sub_56_q_c : std_logic_vector(31 downto 0); signal reg_131_q_c : std_logic_vector(31 downto 0); signal add_59_q_c : std_logic_vector(31 downto 0); signal reg_133_q_c : std_logic_vector(31 downto 0); signal reg_134_q_c : std_logic_vector(31 downto 0); signal reg_135_q_c : std_logic_vector(31 downto 0); signal sub_70_q_c : std_logic_vector(31 downto 0); signal add_64_q_c : std_logic_vector(31 downto 0); signal reg_138_q_c : std_logic_vector(31 downto 0); signal reg_139_q_c : std_logic_vector(31 downto 0); signal reg_140_q_c : std_logic_vector(31 downto 0); signal add_47_q_c : std_logic_vector(31 downto 0); signal reg_142_q_c : std_logic_vector(31 downto 0); signal mul_2_q_c : std_logic_vector(31 downto 0); signal mul_16_q_c : std_logic_vector(31 downto 0); signal reg_145_q_c : std_logic_vector(31 downto 0); signal reg_146_q_c : std_logic_vector(31 downto 0); signal reg_147_q_c : std_logic_vector(31 downto 0); signal sub_50_q_c : std_logic_vector(31 downto 0); signal sub_55_q_c : std_logic_vector(31 downto 0); signal reg_150_q_c : std_logic_vector(31 downto 0); signal reg_151_q_c : std_logic_vector(31 downto 0); signal reg_152_q_c : std_logic_vector(31 downto 0); signal reg_153_q_c : std_logic_vector(31 downto 0); signal reg_154_q_c : std_logic_vector(31 downto 0); signal reg_155_q_c : std_logic_vector(31 downto 0); signal reg_156_q_c : std_logic_vector(31 downto 0); signal reg_157_q_c : std_logic_vector(31 downto 0); signal reg_158_q_c : std_logic_vector(31 downto 0); signal reg_159_q_c : std_logic_vector(31 downto 0); signal reg_160_q_c : std_logic_vector(31 downto 0); signal reg_161_q_c : std_logic_vector(31 downto 0); signal reg_162_q_c : std_logic_vector(31 downto 0); signal reg_163_q_c : std_logic_vector(31 downto 0); signal reg_164_q_c : std_logic_vector(31 downto 0); signal reg_165_q_c : std_logic_vector(31 downto 0); signal reg_166_q_c : std_logic_vector(31 downto 0); signal add_17_q_c : std_logic_vector(15 downto 0); signal add_34_q_c : std_logic_vector(15 downto 0); signal reg_169_q_c : std_logic_vector(15 downto 0); signal add_22_q_c : std_logic_vector(15 downto 0); signal reg_171_q_c : std_logic_vector(15 downto 0); signal reg_172_q_c : std_logic_vector(15 downto 0); signal reg_173_q_c : std_logic_vector(15 downto 0); begin -- Connect signal to primary outputs PRI_OUT_0 <= reg_2_q_c; PRI_OUT_1 <= reg_3_q_c; PRI_OUT_2 <= reg_4_q_c; PRI_OUT_3 <= reg_5_q_c; PRI_OUT_4 <= reg_6_q_c; PRI_OUT_5 <= reg_7_q_c; PRI_OUT_6 <= reg_24_q_c; PRI_OUT_7 <= mux2_48_q_c; PRI_OUT_8 <= reg_36_q_c; PRI_OUT_9 <= reg_37_q_c; PRI_OUT_10 <= reg_15_q_c; PRI_OUT_11 <= reg_38_q_c; PRI_OUT_12 <= reg_41_q_c; PRI_OUT_13 <= reg_42_q_c; PRI_OUT_14 <= mux2_9_q_c; PRI_OUT_15 <= mux2_69_q_c; PRI_OUT_16 <= reg_42_q_c; PRI_OUT_17 <= PRI_IN_0; PRI_OUT_18 <= reg_8_q_c; PRI_OUT_19 <= mux2_2_q_c; PRI_OUT_20 <= reg_27_q_c; PRI_OUT_21 <= reg_56_q_c; PRI_OUT_22 <= reg_57_q_c; PRI_OUT_23 <= reg_58_q_c; PRI_OUT_24 <= reg_59_q_c; PRI_OUT_25 <= reg_60_q_c; PRI_OUT_26 <= reg_51_q_c; PRI_OUT_27 <= PRI_IN_8; PRI_OUT_28 <= reg_20_q_c; PRI_OUT_29 <= reg_61_q_c; PRI_OUT_30 <= reg_34_q_c; PRI_OUT_31 <= reg_62_q_c; PRI_OUT_32 <= reg_63_q_c; PRI_OUT_33 <= mux2_18_q_c; PRI_OUT_34 <= reg_41_q_c; -- Subtracter (SUB_1) --------------------------------------------------- SUB_1: SUB generic map ( width_a => 16 ) port map ( a => mux2_13_q_c, b => reg_54_q_c, q => sub_1_q_c ); -- Subtracter (SUB_2) --------------------------------------------------- SUB_2: SUB generic map ( width_a => 16 ) port map ( a => mux2_25_q_c, b => reg_64_q_c, q => sub_2_q_c ); -- Subtracter (SUB_3) --------------------------------------------------- SUB_3: SUB generic map ( width_a => 16 ) port map ( a => reg_65_q_c, b => mux2_22_q_c, q => sub_3_q_c ); -- Subtracter (SUB_4) --------------------------------------------------- SUB_4: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_6, b => PRI_IN_33, q => sub_4_q_c ); -- Subtracter (SUB_5) --------------------------------------------------- SUB_5: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_11, b => PRI_IN_15, q => sub_5_q_c ); -- Subtracter (SUB_6) --------------------------------------------------- SUB_6: SUB generic map ( width_a => 16 ) port map ( a => reg_66_q_c, b => PRI_IN_19, q => sub_6_q_c ); -- Subtracter (SUB_7) --------------------------------------------------- SUB_7: SUB generic map ( width_a => 16 ) port map ( a => mux2_11_q_c, b => mux2_17_q_c, q => sub_7_q_c ); -- Subtracter (SUB_8) --------------------------------------------------- SUB_8: SUB generic map ( width_a => 16 ) port map ( a => mux2_10_q_c, b => mux2_34_q_c, q => sub_8_q_c ); -- Subtracter (SUB_9) --------------------------------------------------- SUB_9: SUB generic map ( width_a => 16 ) port map ( a => mux2_31_q_c, b => reg_67_q_c, q => sub_9_q_c ); -- Subtracter (SUB_10) -------------------------------------------------- SUB_10: SUB generic map ( width_a => 16 ) port map ( a => reg_55_q_c, b => reg_21_q_c, q => sub_10_q_c ); -- Subtracter (SUB_11) -------------------------------------------------- SUB_11: SUB generic map ( width_a => 16 ) port map ( a => reg_53_q_c, b => mux2_12_q_c, q => sub_11_q_c ); -- Subtracter (SUB_12) -------------------------------------------------- SUB_12: SUB generic map ( width_a => 16 ) port map ( a => reg_70_q_c, b => mux2_20_q_c, q => sub_12_q_c ); -- Subtracter (SUB_13) -------------------------------------------------- SUB_13: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_27, b => PRI_IN_33, q => sub_13_q_c ); -- Subtracter (SUB_14) -------------------------------------------------- SUB_14: SUB generic map ( width_a => 16 ) port map ( a => mux2_22_q_c, b => mux2_12_q_c, q => sub_14_q_c ); -- Subtracter (SUB_15) -------------------------------------------------- SUB_15: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_17, b => reg_72_q_c, q => sub_15_q_c ); -- Subtracter (SUB_16) -------------------------------------------------- SUB_16: SUB generic map ( width_a => 16 ) port map ( a => reg_18_q_c, b => mux2_28_q_c, q => sub_16_q_c ); -- Subtracter (SUB_17) -------------------------------------------------- SUB_17: SUB generic map ( width_a => 16 ) port map ( a => mux2_6_q_c, b => mux2_28_q_c, q => sub_17_q_c ); -- Subtracter (SUB_18) -------------------------------------------------- SUB_18: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_8, b => reg_14_q_c, q => sub_18_q_c ); -- Subtracter (SUB_19) -------------------------------------------------- SUB_19: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_29, b => PRI_IN_13, q => sub_19_q_c ); -- Subtracter (SUB_20) -------------------------------------------------- SUB_20: SUB generic map ( width_a => 16 ) port map ( a => reg_61_q_c, b => reg_75_q_c, q => sub_20_q_c ); -- Subtracter (SUB_21) -------------------------------------------------- SUB_21: SUB generic map ( width_a => 16 ) port map ( a => reg_76_q_c, b => reg_77_q_c, q => sub_21_q_c ); -- Subtracter (SUB_22) -------------------------------------------------- SUB_22: SUB generic map ( width_a => 16 ) port map ( a => reg_78_q_c, b => PRI_IN_23, q => sub_22_q_c ); -- Subtracter (SUB_23) -------------------------------------------------- SUB_23: SUB generic map ( width_a => 16 ) port map ( a => reg_79_q_c, b => reg_67_q_c, q => sub_23_q_c ); -- Subtracter (SUB_24) -------------------------------------------------- SUB_24: SUB generic map ( width_a => 16 ) port map ( a => reg_80_q_c, b => mux2_8_q_c, q => sub_24_q_c ); -- Subtracter (SUB_25) -------------------------------------------------- SUB_25: SUB generic map ( width_a => 16 ) port map ( a => mux2_11_q_c, b => reg_81_q_c, q => sub_25_q_c ); -- Subtracter (SUB_26) -------------------------------------------------- SUB_26: SUB generic map ( width_a => 16 ) port map ( a => reg_66_q_c, b => reg_64_q_c, q => sub_26_q_c ); -- Subtracter (SUB_27) -------------------------------------------------- SUB_27: SUB generic map ( width_a => 16 ) port map ( a => reg_25_q_c, b => reg_1_q_c, q => sub_27_q_c ); -- Subtracter (SUB_28) -------------------------------------------------- SUB_28: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_27, b => mux2_5_q_c, q => sub_28_q_c ); -- Subtracter (SUB_29) -------------------------------------------------- SUB_29: SUB generic map ( width_a => 16 ) port map ( a => reg_42_q_c, b => PRI_IN_23, q => sub_29_q_c ); -- Subtracter (SUB_30) -------------------------------------------------- SUB_30: SUB generic map ( width_a => 16 ) port map ( a => reg_36_q_c, b => reg_82_q_c, q => sub_30_q_c ); -- Subtracter (SUB_31) -------------------------------------------------- SUB_31: SUB generic map ( width_a => 16 ) port map ( a => reg_83_q_c, b => mux2_30_q_c, q => sub_31_q_c ); -- Subtracter (SUB_32) -------------------------------------------------- SUB_32: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_29, b => reg_2_q_c, q => sub_32_q_c ); -- Subtracter (SUB_33) -------------------------------------------------- SUB_33: SUB generic map ( width_a => 16 ) port map ( a => PRI_IN_19, b => reg_86_q_c, q => sub_33_q_c ); -- Subtracter (SUB_34) -------------------------------------------------- SUB_34: SUB generic map ( width_a => 16 ) port map ( a => reg_88_q_c, b => reg_89_q_c, q => sub_34_q_c ); -- Subtracter (SUB_35) -------------------------------------------------- SUB_35: SUB generic map ( width_a => 16 ) port map ( a => mux2_35_q_c, b => PRI_IN_17, q => sub_35_q_c ); -- Adder (ADD_1) -------------------------------------------------------- ADD_1: ADD generic map ( width_a => 16 ) port map ( a => mux2_20_q_c, b => reg_19_q_c, q => add_1_q_c ); -- Adder (ADD_2) -------------------------------------------------------- ADD_2: ADD generic map ( width_a => 16 ) port map ( a => mux2_28_q_c, b => PRI_IN_16, q => add_2_q_c ); -- Adder (ADD_3) -------------------------------------------------------- ADD_3: ADD generic map ( width_a => 16 ) port map ( a => mux2_25_q_c, b => mux2_3_q_c, q => add_3_q_c ); -- Adder (ADD_4) -------------------------------------------------------- ADD_4: ADD generic map ( width_a => 16 ) port map ( a => PRI_IN_12, b => reg_15_q_c, q => add_4_q_c ); -- Adder (ADD_5) -------------------------------------------------------- ADD_5: ADD generic map ( width_a => 16 ) port map ( a => mux2_2_q_c, b => reg_91_q_c, q => add_5_q_c ); -- Adder (ADD_6) -------------------------------------------------------- ADD_6: ADD generic map ( width_a => 16 ) port map ( a => PRI_IN_27, b => mux2_32_q_c, q => add_6_q_c ); -- Adder (ADD_7) -------------------------------------------------------- ADD_7: ADD generic map ( width_a => 16 ) port map ( a => mux2_8_q_c, b => PRI_IN_23, q => add_7_q_c ); -- Adder (ADD_8) -------------------------------------------------------- ADD_8: ADD generic map ( width_a => 16 ) port map ( a => PRI_IN_22, b => mux2_17_q_c, q => add_8_q_c ); -- Adder (ADD_9) -------------------------------------------------------- ADD_9: ADD generic map ( width_a => 16 ) port map ( a => reg_92_q_c, b => mux2_19_q_c, q => add_9_q_c ); -- Adder (ADD_10) ------------------------------------------------------- ADD_10: ADD generic map ( width_a => 16 ) port map ( a => mux2_28_q_c, b => PRI_IN_31, q => add_10_q_c ); -- Adder (ADD_11) ------------------------------------------------------- ADD_11: ADD generic map ( width_a => 16 ) port map ( a => reg_93_q_c, b => reg_72_q_c, q => add_11_q_c ); -- Adder (ADD_12) ------------------------------------------------------- ADD_12: ADD generic map ( width_a => 16 ) port map ( a => reg_21_q_c, b => reg_66_q_c, q => add_12_q_c ); -- Adder (ADD_13) ------------------------------------------------------- ADD_13: ADD generic map ( width_a => 16 ) port map ( a => reg_61_q_c, b => reg_93_q_c, q => add_13_q_c ); -- Adder (ADD_14) ------------------------------------------------------- ADD_14: ADD generic map ( width_a => 16 ) port map ( a => reg_94_q_c, b => reg_22_q_c, q => add_14_q_c ); -- Adder (ADD_15) ------------------------------------------------------- ADD_15: ADD generic map ( width_a => 16 ) port map ( a => reg_95_q_c, b => reg_92_q_c, q => add_15_q_c ); -- Adder (ADD_16) ------------------------------------------------------- ADD_16: ADD generic map ( width_a => 16 ) port map ( a => mux2_26_q_c, b => PRI_IN_20, q => add_16_q_c ); -- Adder (ADD_17) ------------------------------------------------------- ADD_17: ADD generic map ( width_a => 16 ) port map ( a => mux2_9_q_c, b => PRI_IN_28, q => add_17_q_c ); -- Adder (ADD_18) ------------------------------------------------------- ADD_18: ADD generic map ( width_a => 16 ) port map ( a => reg_71_q_c, b => mux2_22_q_c, q => add_18_q_c ); -- Adder (ADD_19) ------------------------------------------------------- ADD_19: ADD generic map ( width_a => 16 ) port map ( a => reg_86_q_c, b => PRI_IN_25, q => add_19_q_c ); -- Adder (ADD_20) ------------------------------------------------------- ADD_20: ADD generic map ( width_a => 16 ) port map ( a => reg_96_q_c, b => mux2_5_q_c, q => add_20_q_c ); -- Adder (ADD_21) ------------------------------------------------------- ADD_21: ADD generic map ( width_a => 16 ) port map ( a => PRI_IN_15, b => reg_25_q_c, q => add_21_q_c ); -- Adder (ADD_22) ------------------------------------------------------- ADD_22: ADD generic map ( width_a => 16 ) port map ( a => mux2_33_q_c, b => reg_97_q_c, q => add_22_q_c ); -- Adder (ADD_23) ------------------------------------------------------- ADD_23: ADD generic map ( width_a => 16 ) port map ( a => reg_69_q_c, b => PRI_IN_10, q => add_23_q_c ); -- Adder (ADD_24) ------------------------------------------------------- ADD_24: ADD generic map ( width_a => 16 ) port map ( a => reg_94_q_c, b => mux2_11_q_c, q => add_24_q_c ); -- Adder (ADD_25) ------------------------------------------------------- ADD_25: ADD generic map ( width_a => 16 ) port map ( a => mux2_9_q_c, b => reg_98_q_c, q => add_25_q_c ); -- Adder (ADD_26) ------------------------------------------------------- ADD_26: ADD generic map ( width_a => 16 ) port map ( a => reg_70_q_c, b => PRI_IN_12, q => add_26_q_c ); -- Adder (ADD_27) ------------------------------------------------------- ADD_27: ADD generic map ( width_a => 16 ) port map ( a => reg_92_q_c, b => PRI_IN_23, q => add_27_q_c ); -- Adder (ADD_28) ------------------------------------------------------- ADD_28: ADD generic map ( width_a => 16 ) port map ( a => mux2_15_q_c, b => reg_12_q_c, q => add_28_q_c ); -- Adder (ADD_29) ------------------------------------------------------- ADD_29: ADD generic map ( width_a => 16 ) port map ( a => mux2_32_q_c, b => PRI_IN_12, q => add_29_q_c ); -- Adder (ADD_30) ------------------------------------------------------- ADD_30: ADD generic map ( width_a => 16 ) port map ( a => reg_76_q_c, b => mux2_29_q_c, q => add_30_q_c ); -- Adder (ADD_31) ------------------------------------------------------- ADD_31: ADD generic map ( width_a => 16 ) port map ( a => reg_99_q_c, b => mux2_16_q_c, q => add_31_q_c ); -- Adder (ADD_32) ------------------------------------------------------- ADD_32: ADD generic map ( width_a => 16 ) port map ( a => reg_80_q_c, b => reg_76_q_c, q => add_32_q_c ); -- Adder (ADD_33) ------------------------------------------------------- ADD_33: ADD generic map ( width_a => 16 ) port map ( a => PRI_IN_15, b => reg_65_q_c, q => add_33_q_c ); -- Adder (ADD_34) ------------------------------------------------------- ADD_34: ADD generic map ( width_a => 16 ) port map ( a => reg_100_q_c, b => PRI_IN_17, q => add_34_q_c ); -- Adder (ADD_35) ------------------------------------------------------- ADD_35: ADD generic map ( width_a => 16 ) port map ( a => mux2_11_q_c, b => mux2_27_q_c, q => add_35_q_c ); -- Multiplexor - 2 inputs (MUX2_1) -------------------------------------- MUX2_1: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_27_q_c, b => reg_21_q_c, sel => C_MUX2_1_SEL, q => mux2_1_q_c ); -- Multiplexor - 2 inputs (MUX2_2) -------------------------------------- MUX2_2: MUX2 generic map ( width_a => 16 ) port map ( a => reg_52_q_c, b => PRI_IN_5, sel => C_MUX2_2_SEL, q => mux2_2_q_c ); -- Multiplexor - 2 inputs (MUX2_3) -------------------------------------- MUX2_3: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_32_q_c, b => reg_11_q_c, sel => C_MUX2_3_SEL, q => mux2_3_q_c ); -- Multiplexor - 2 inputs (MUX2_4) -------------------------------------- MUX2_4: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_25, b => PRI_IN_6, sel => C_MUX2_4_SEL, q => mux2_4_q_c ); -- Multiplexor - 2 inputs (MUX2_5) -------------------------------------- MUX2_5: MUX2 generic map ( width_a => 16 ) port map ( a => reg_18_q_c, b => reg_14_q_c, sel => C_MUX2_5_SEL, q => mux2_5_q_c ); -- Multiplexor - 2 inputs (MUX2_6) -------------------------------------- MUX2_6: MUX2 generic map ( width_a => 16 ) port map ( a => reg_22_q_c, b => reg_19_q_c, sel => C_MUX2_6_SEL, q => mux2_6_q_c ); -- Multiplexor - 2 inputs (MUX2_7) -------------------------------------- MUX2_7: MUX2 generic map ( width_a => 16 ) port map ( a => reg_43_q_c, b => reg_42_q_c, sel => C_MUX2_7_SEL, q => mux2_7_q_c ); -- Multiplexor - 2 inputs (MUX2_8) -------------------------------------- MUX2_8: MUX2 generic map ( width_a => 16 ) port map ( a => reg_1_q_c, b => reg_2_q_c, sel => C_MUX2_8_SEL, q => mux2_8_q_c ); -- Multiplexor - 2 inputs (MUX2_9) -------------------------------------- MUX2_9: MUX2 generic map ( width_a => 16 ) port map ( a => reg_22_q_c, b => mux2_20_q_c, sel => C_MUX2_9_SEL, q => mux2_9_q_c ); -- Multiplexor - 2 inputs (MUX2_10) ------------------------------------- MUX2_10: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_24_q_c, b => mux2_4_q_c, sel => C_MUX2_10_SEL, q => mux2_10_q_c ); -- Multiplexor - 2 inputs (MUX2_11) ------------------------------------- MUX2_11: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_13, b => PRI_IN_18, sel => C_MUX2_11_SEL, q => mux2_11_q_c ); -- Multiplexor - 2 inputs (MUX2_12) ------------------------------------- MUX2_12: MUX2 generic map ( width_a => 16 ) port map ( a => reg_69_q_c, b => reg_68_q_c, sel => C_MUX2_12_SEL, q => mux2_12_q_c ); -- Multiplexor - 2 inputs (MUX2_13) ------------------------------------- MUX2_13: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_21_q_c, b => PRI_IN_33, sel => C_MUX2_13_SEL, q => mux2_13_q_c ); -- Multiplexor - 2 inputs (MUX2_14) ------------------------------------- MUX2_14: MUX2 generic map ( width_a => 16 ) port map ( a => sub_20_q_c, b => add_4_q_c, sel => C_MUX2_14_SEL, q => mux2_14_q_c ); -- Multiplexor - 2 inputs (MUX2_15) ------------------------------------- MUX2_15: MUX2 generic map ( width_a => 16 ) port map ( a => reg_17_q_c, b => reg_15_q_c, sel => C_MUX2_15_SEL, q => mux2_15_q_c ); -- Multiplexor - 2 inputs (MUX2_16) ------------------------------------- MUX2_16: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_13, b => reg_13_q_c, sel => C_MUX2_16_SEL, q => mux2_16_q_c ); -- Multiplexor - 2 inputs (MUX2_17) ------------------------------------- MUX2_17: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_33_q_c, b => reg_53_q_c, sel => C_MUX2_17_SEL, q => mux2_17_q_c ); -- Multiplexor - 2 inputs (MUX2_18) ------------------------------------- MUX2_18: MUX2 generic map ( width_a => 16 ) port map ( a => reg_16_q_c, b => mux2_15_q_c, sel => C_MUX2_18_SEL, q => mux2_18_q_c ); -- Multiplexor - 2 inputs (MUX2_19) ------------------------------------- MUX2_19: MUX2 generic map ( width_a => 16 ) port map ( a => reg_86_q_c, b => reg_87_q_c, sel => C_MUX2_19_SEL, q => mux2_19_q_c ); -- Multiplexor - 2 inputs (MUX2_20) ------------------------------------- MUX2_20: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_32_q_c, b => mux2_35_q_c, sel => C_MUX2_20_SEL, q => mux2_20_q_c ); -- Multiplexor - 2 inputs (MUX2_21) ------------------------------------- MUX2_21: MUX2 generic map ( width_a => 16 ) port map ( a => reg_55_q_c, b => reg_52_q_c, sel => C_MUX2_21_SEL, q => mux2_21_q_c ); -- Multiplexor - 2 inputs (MUX2_22) ------------------------------------- MUX2_22: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_16, b => reg_20_q_c, sel => C_MUX2_22_SEL, q => mux2_22_q_c ); -- Multiplexor - 2 inputs (MUX2_23) ------------------------------------- MUX2_23: MUX2 generic map ( width_a => 16 ) port map ( a => reg_71_q_c, b => reg_72_q_c, sel => C_MUX2_23_SEL, q => mux2_23_q_c ); -- Multiplexor - 2 inputs (MUX2_24) ------------------------------------- MUX2_24: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_8, b => reg_18_q_c, sel => C_MUX2_24_SEL, q => mux2_24_q_c ); -- Multiplexor - 2 inputs (MUX2_25) ------------------------------------- MUX2_25: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_4, b => mux2_4_q_c, sel => C_MUX2_25_SEL, q => mux2_25_q_c ); -- Multiplexor - 2 inputs (MUX2_26) ------------------------------------- MUX2_26: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_16, b => reg_24_q_c, sel => C_MUX2_26_SEL, q => mux2_26_q_c ); -- Multiplexor - 2 inputs (MUX2_27) ------------------------------------- MUX2_27: MUX2 generic map ( width_a => 16 ) port map ( a => reg_23_q_c, b => reg_25_q_c, sel => C_MUX2_27_SEL, q => mux2_27_q_c ); -- Multiplexor - 2 inputs (MUX2_28) ------------------------------------- MUX2_28: MUX2 generic map ( width_a => 16 ) port map ( a => reg_73_q_c, b => reg_74_q_c, sel => C_MUX2_28_SEL, q => mux2_28_q_c ); -- Multiplexor - 2 inputs (MUX2_29) ------------------------------------- MUX2_29: MUX2 generic map ( width_a => 16 ) port map ( a => reg_54_q_c, b => PRI_IN_5, sel => C_MUX2_29_SEL, q => mux2_29_q_c ); -- Multiplexor - 2 inputs (MUX2_30) ------------------------------------- MUX2_30: MUX2 generic map ( width_a => 16 ) port map ( a => reg_85_q_c, b => reg_84_q_c, sel => C_MUX2_30_SEL, q => mux2_30_q_c ); -- Multiplexor - 2 inputs (MUX2_31) ------------------------------------- MUX2_31: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_22_q_c, b => reg_21_q_c, sel => C_MUX2_31_SEL, q => mux2_31_q_c ); -- Multiplexor - 2 inputs (MUX2_32) ------------------------------------- MUX2_32: MUX2 generic map ( width_a => 16 ) port map ( a => PRI_IN_16, b => PRI_IN_6, sel => C_MUX2_32_SEL, q => mux2_32_q_c ); -- Multiplexor - 2 inputs (MUX2_33) ------------------------------------- MUX2_33: MUX2 generic map ( width_a => 16 ) port map ( a => reg_52_q_c, b => reg_51_q_c, sel => C_MUX2_33_SEL, q => mux2_33_q_c ); -- Multiplexor - 2 inputs (MUX2_34) ------------------------------------- MUX2_34: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_18_q_c, b => PRI_IN_8, sel => C_MUX2_34_SEL, q => mux2_34_q_c ); -- Multiplexor - 2 inputs (MUX2_35) ------------------------------------- MUX2_35: MUX2 generic map ( width_a => 16 ) port map ( a => mux2_11_q_c, b => reg_12_q_c, sel => C_MUX2_35_SEL, q => mux2_35_q_c ); -- Subtracter (SUB_36) -------------------------------------------------- SUB_36: SUB generic map ( width_a => 32 ) port map ( a => reg_63_q_c, b => reg_101_q_c, q => sub_36_q_c ); -- Subtracter (SUB_37) -------------------------------------------------- SUB_37: SUB generic map ( width_a => 32 ) port map ( a => reg_102_q_c, b => reg_103_q_c, q => sub_37_q_c ); -- Subtracter (SUB_38) -------------------------------------------------- SUB_38: SUB generic map ( width_a => 32 ) port map ( a => reg_105_q_c, b => reg_106_q_c, q => sub_38_q_c ); -- Subtracter (SUB_39) -------------------------------------------------- SUB_39: SUB generic map ( width_a => 32 ) port map ( a => mux2_42_q_c, b => reg_107_q_c, q => sub_39_q_c ); -- Subtracter (SUB_40) -------------------------------------------------- SUB_40: SUB generic map ( width_a => 32 ) port map ( a => reg_6_q_c, b => mux2_51_q_c, q => sub_40_q_c ); -- Subtracter (SUB_41) -------------------------------------------------- SUB_41: SUB generic map ( width_a => 32 ) port map ( a => reg_109_q_c, b => mux2_66_q_c, q => sub_41_q_c ); -- Subtracter (SUB_42) -------------------------------------------------- SUB_42: SUB generic map ( width_a => 32 ) port map ( a => reg_113_q_c, b => reg_115_q_c, q => sub_42_q_c ); -- Subtracter (SUB_43) -------------------------------------------------- SUB_43: SUB generic map ( width_a => 32 ) port map ( a => mux2_66_q_c, b => reg_109_q_c, q => sub_43_q_c ); -- Subtracter (SUB_44) -------------------------------------------------- SUB_44: SUB generic map ( width_a => 32 ) port map ( a => reg_116_q_c, b => reg_118_q_c, q => sub_44_q_c ); -- Subtracter (SUB_45) -------------------------------------------------- SUB_45: SUB generic map ( width_a => 32 ) port map ( a => reg_120_q_c, b => reg_121_q_c, q => sub_45_q_c ); -- Subtracter (SUB_46) -------------------------------------------------- SUB_46: SUB generic map ( width_a => 32 ) port map ( a => mux2_69_q_c, b => reg_5_q_c, q => sub_46_q_c ); -- Subtracter (SUB_47) -------------------------------------------------- SUB_47: SUB generic map ( width_a => 32 ) port map ( a => reg_122_q_c, b => mux2_70_q_c, q => sub_47_q_c ); -- Subtracter (SUB_48) -------------------------------------------------- SUB_48: SUB generic map ( width_a => 32 ) port map ( a => reg_123_q_c, b => reg_124_q_c, q => sub_48_q_c ); -- Subtracter (SUB_49) -------------------------------------------------- SUB_49: SUB generic map ( width_a => 32 ) port map ( a => mux2_66_q_c, b => reg_125_q_c, q => sub_49_q_c ); -- Subtracter (SUB_50) -------------------------------------------------- SUB_50: SUB generic map ( width_a => 32 ) port map ( a => reg_126_q_c, b => reg_112_q_c, q => sub_50_q_c ); -- Subtracter (SUB_51) -------------------------------------------------- SUB_51: SUB generic map ( width_a => 32 ) port map ( a => reg_125_q_c, b => mux2_69_q_c, q => sub_51_q_c ); -- Subtracter (SUB_52) -------------------------------------------------- SUB_52: SUB generic map ( width_a => 32 ) port map ( a => reg_58_q_c, b => reg_127_q_c, q => sub_52_q_c ); -- Subtracter (SUB_53) -------------------------------------------------- SUB_53: SUB generic map ( width_a => 32 ) port map ( a => reg_57_q_c, b => reg_4_q_c, q => sub_53_q_c ); -- Subtracter (SUB_54) -------------------------------------------------- SUB_54: SUB generic map ( width_a => 32 ) port map ( a => reg_128_q_c, b => mux2_58_q_c, q => sub_54_q_c ); -- Subtracter (SUB_55) -------------------------------------------------- SUB_55: SUB generic map ( width_a => 32 ) port map ( a => reg_129_q_c, b => reg_130_q_c, q => sub_55_q_c ); -- Subtracter (SUB_56) -------------------------------------------------- SUB_56: SUB generic map ( width_a => 32 ) port map ( a => reg_131_q_c, b => reg_110_q_c, q => sub_56_q_c ); -- Subtracter (SUB_57) -------------------------------------------------- SUB_57: SUB generic map ( width_a => 32 ) port map ( a => reg_132_q_c, b => reg_121_q_c, q => sub_57_q_c ); -- Subtracter (SUB_58) -------------------------------------------------- SUB_58: SUB generic map ( width_a => 32 ) port map ( a => reg_133_q_c, b => reg_134_q_c, q => sub_58_q_c ); -- Subtracter (SUB_59) -------------------------------------------------- SUB_59: SUB generic map ( width_a => 32 ) port map ( a => reg_130_q_c, b => mux2_55_q_c, q => sub_59_q_c ); -- Subtracter (SUB_60) -------------------------------------------------- SUB_60: SUB generic map ( width_a => 32 ) port map ( a => reg_135_q_c, b => reg_136_q_c, q => sub_60_q_c ); -- Subtracter (SUB_61) -------------------------------------------------- SUB_61: SUB generic map ( width_a => 32 ) port map ( a => reg_59_q_c, b => PRI_IN_2, q => sub_61_q_c ); -- Subtracter (SUB_62) -------------------------------------------------- SUB_62: SUB generic map ( width_a => 32 ) port map ( a => reg_137_q_c, b => reg_122_q_c, q => sub_62_q_c ); -- Subtracter (SUB_63) -------------------------------------------------- SUB_63: SUB generic map ( width_a => 32 ) port map ( a => mux2_64_q_c, b => reg_138_q_c, q => sub_63_q_c ); -- Subtracter (SUB_64) -------------------------------------------------- SUB_64: SUB generic map ( width_a => 32 ) port map ( a => mux2_39_q_c, b => reg_139_q_c, q => sub_64_q_c ); -- Subtracter (SUB_65) -------------------------------------------------- SUB_65: SUB generic map ( width_a => 32 ) port map ( a => reg_103_q_c, b => reg_140_q_c, q => sub_65_q_c ); -- Subtracter (SUB_66) -------------------------------------------------- SUB_66: SUB generic map ( width_a => 32 ) port map ( a => mux2_48_q_c, b => reg_108_q_c, q => sub_66_q_c ); -- Subtracter (SUB_67) -------------------------------------------------- SUB_67: SUB generic map ( width_a => 32 ) port map ( a => mux2_67_q_c, b => reg_44_q_c, q => sub_67_q_c ); -- Subtracter (SUB_68) -------------------------------------------------- SUB_68: SUB generic map ( width_a => 32 ) port map ( a => PRI_IN_34, b => reg_50_q_c, q => sub_68_q_c ); -- Subtracter (SUB_69) -------------------------------------------------- SUB_69: SUB generic map ( width_a => 32 ) port map ( a => mux2_70_q_c, b => reg_141_q_c, q => sub_69_q_c ); -- Subtracter (SUB_70) -------------------------------------------------- SUB_70: SUB generic map ( width_a => 32 ) port map ( a => reg_132_q_c, b => reg_142_q_c, q => sub_70_q_c ); -- Adder (ADD_36) ------------------------------------------------------- ADD_36: ADD generic map ( width_a => 32 ) port map ( a => PRI_IN_9, b => reg_9_q_c, q => add_36_q_c ); -- Adder (ADD_37) ------------------------------------------------------- ADD_37: ADD generic map ( width_a => 32 ) port map ( a => reg_143_q_c, b => reg_126_q_c, q => add_37_q_c ); -- Adder (ADD_38) ------------------------------------------------------- ADD_38: ADD generic map ( width_a => 32 ) port map ( a => reg_60_q_c, b => PRI_IN_24, q => add_38_q_c ); -- Adder (ADD_39) ------------------------------------------------------- ADD_39: ADD generic map ( width_a => 32 ) port map ( a => reg_124_q_c, b => reg_144_q_c, q => add_39_q_c ); -- Adder (ADD_40) ------------------------------------------------------- ADD_40: ADD generic map ( width_a => 32 ) port map ( a => mux2_45_q_c, b => PRI_IN_26, q => add_40_q_c ); -- Adder (ADD_41) ------------------------------------------------------- ADD_41: ADD generic map ( width_a => 32 ) port map ( a => reg_145_q_c, b => PRI_IN_21, q => add_41_q_c ); -- Adder (ADD_42) ------------------------------------------------------- ADD_42: ADD generic map ( width_a => 32 ) port map ( a => reg_146_q_c, b => reg_147_q_c, q => add_42_q_c ); -- Adder (ADD_43) ------------------------------------------------------- ADD_43: ADD generic map ( width_a => 32 ) port map ( a => reg_114_q_c, b => mux2_38_q_c, q => add_43_q_c ); -- Adder (ADD_44) ------------------------------------------------------- ADD_44: ADD generic map ( width_a => 32 ) port map ( a => reg_124_q_c, b => reg_35_q_c, q => add_44_q_c ); -- Adder (ADD_45) ------------------------------------------------------- ADD_45: ADD generic map ( width_a => 32 ) port map ( a => reg_5_q_c, b => reg_150_q_c, q => add_45_q_c ); -- Adder (ADD_46) ------------------------------------------------------- ADD_46: ADD generic map ( width_a => 32 ) port map ( a => reg_26_q_c, b => reg_39_q_c, q => add_46_q_c ); -- Adder (ADD_47) ------------------------------------------------------- ADD_47: ADD generic map ( width_a => 32 ) port map ( a => reg_136_q_c, b => mux2_46_q_c, q => add_47_q_c ); -- Adder (ADD_48) ------------------------------------------------------- ADD_48: ADD generic map ( width_a => 32 ) port map ( a => reg_63_q_c, b => reg_151_q_c, q => add_48_q_c ); -- Adder (ADD_49) ------------------------------------------------------- ADD_49: ADD generic map ( width_a => 32 ) port map ( a => reg_37_q_c, b => mux2_48_q_c, q => add_49_q_c ); -- Adder (ADD_50) ------------------------------------------------------- ADD_50: ADD generic map ( width_a => 32 ) port map ( a => reg_152_q_c, b => reg_153_q_c, q => add_50_q_c ); -- Adder (ADD_51) ------------------------------------------------------- ADD_51: ADD generic map ( width_a => 32 ) port map ( a => reg_62_q_c, b => reg_115_q_c, q => add_51_q_c ); -- Adder (ADD_52) ------------------------------------------------------- ADD_52: ADD generic map ( width_a => 32 ) port map ( a => reg_109_q_c, b => reg_115_q_c, q => add_52_q_c ); -- Adder (ADD_53) ------------------------------------------------------- ADD_53: ADD generic map ( width_a => 32 ) port map ( a => PRI_IN_21, b => mux2_54_q_c, q => add_53_q_c ); -- Adder (ADD_54) ------------------------------------------------------- ADD_54: ADD generic map ( width_a => 32 ) port map ( a => reg_154_q_c, b => reg_63_q_c, q => add_54_q_c ); -- Adder (ADD_55) ------------------------------------------------------- ADD_55: ADD generic map ( width_a => 32 ) port map ( a => mux2_38_q_c, b => mux2_59_q_c, q => add_55_q_c ); -- Adder (ADD_56) ------------------------------------------------------- ADD_56: ADD generic map ( width_a => 32 ) port map ( a => reg_117_q_c, b => mux2_36_q_c, q => add_56_q_c ); -- Adder (ADD_57) ------------------------------------------------------- ADD_57: ADD generic map ( width_a => 32 ) port map ( a => reg_37_q_c, b => reg_105_q_c, q => add_57_q_c ); -- Adder (ADD_58) ------------------------------------------------------- ADD_58: ADD generic map ( width_a => 32 ) port map ( a => reg_155_q_c, b => reg_156_q_c, q => add_58_q_c ); -- Adder (ADD_59) ------------------------------------------------------- ADD_59: ADD generic map ( width_a => 32 ) port map ( a => reg_157_q_c, b => PRI_IN_30, q => add_59_q_c ); -- Adder (ADD_60) ------------------------------------------------------- ADD_60: ADD generic map ( width_a => 32 ) port map ( a => reg_158_q_c, b => reg_159_q_c, q => add_60_q_c ); -- Adder (ADD_61) ------------------------------------------------------- ADD_61: ADD generic map ( width_a => 32 ) port map ( a => reg_10_q_c, b => reg_160_q_c, q => add_61_q_c ); -- Adder (ADD_62) ------------------------------------------------------- ADD_62: ADD generic map ( width_a => 32 ) port map ( a => reg_56_q_c, b => reg_137_q_c, q => add_62_q_c ); -- Adder (ADD_63) ------------------------------------------------------- ADD_63: ADD generic map ( width_a => 32 ) port map ( a => reg_143_q_c, b => reg_161_q_c, q => add_63_q_c ); -- Adder (ADD_64) ------------------------------------------------------- ADD_64: ADD generic map ( width_a => 32 ) port map ( a => reg_162_q_c, b => reg_136_q_c, q => add_64_q_c ); -- Adder (ADD_65) ------------------------------------------------------- ADD_65: ADD generic map ( width_a => 32 ) port map ( a => reg_124_q_c, b => reg_130_q_c, q => add_65_q_c ); -- Adder (ADD_66) ------------------------------------------------------- ADD_66: ADD generic map ( width_a => 32 ) port map ( a => reg_163_q_c, b => reg_164_q_c, q => add_66_q_c ); -- Adder (ADD_67) ------------------------------------------------------- ADD_67: ADD generic map ( width_a => 32 ) port map ( a => reg_144_q_c, b => reg_119_q_c, q => add_67_q_c ); -- Adder (ADD_68) ------------------------------------------------------- ADD_68: ADD generic map ( width_a => 32 ) port map ( a => mux2_70_q_c, b => mux2_67_q_c, q => add_68_q_c ); -- Adder (ADD_69) ------------------------------------------------------- ADD_69: ADD generic map ( width_a => 32 ) port map ( a => reg_141_q_c, b => reg_165_q_c, q => add_69_q_c ); -- Adder (ADD_70) ------------------------------------------------------- ADD_70: ADD generic map ( width_a => 32 ) port map ( a => reg_166_q_c, b => reg_62_q_c, q => add_70_q_c ); -- Multiplexor - 2 inputs (MUX2_36) ------------------------------------- MUX2_36: MUX2 generic map ( width_a => 32 ) port map ( a => reg_40_q_c, b => reg_41_q_c, sel => C_MUX2_36_SEL, q => mux2_36_q_c ); -- Multiplexor - 2 inputs (MUX2_37) ------------------------------------- MUX2_37: MUX2 generic map ( width_a => 32 ) port map ( a => PRI_IN_34, b => reg_31_q_c, sel => C_MUX2_37_SEL, q => mux2_37_q_c ); -- Multiplexor - 2 inputs (MUX2_38) ------------------------------------- MUX2_38: MUX2 generic map ( width_a => 32 ) port map ( a => mux2_68_q_c, b => reg_148_q_c, sel => C_MUX2_38_SEL, q => mux2_38_q_c ); -- Multiplexor - 2 inputs (MUX2_39) ------------------------------------- MUX2_39: MUX2 generic map ( width_a => 32 ) port map ( a => PRI_IN_24, b => reg_30_q_c, sel => C_MUX2_39_SEL, q => mux2_39_q_c ); -- Multiplexor - 2 inputs (MUX2_40) ------------------------------------- MUX2_40: MUX2 generic map ( width_a => 32 ) port map ( a => mux2_54_q_c, b => reg_30_q_c, sel => C_MUX2_40_SEL, q => mux2_40_q_c ); -- Multiplexor - 2 inputs (MUX2_41) ------------------------------------- MUX2_41: MUX2 generic map ( width_a => 32 ) port map ( a => reg_50_q_c, b => reg_45_q_c, sel => C_MUX2_41_SEL, q => mux2_41_q_c ); -- Multiplexor - 2 inputs (MUX2_42) ------------------------------------- MUX2_42: MUX2 generic map ( width_a => 32 ) port map ( a => reg_27_q_c, b => reg_34_q_c, sel => C_MUX2_42_SEL, q => mux2_42_q_c ); -- Multiplexor - 2 inputs (MUX2_43) ------------------------------------- MUX2_43: MUX2 generic map ( width_a => 32 ) port map ( a => mul_10_q_c, b => mul_14_q_c, sel => C_MUX2_43_SEL, q => mux2_43_q_c ); -- Multiplexor - 2 inputs (MUX2_44) ------------------------------------- MUX2_44: MUX2 generic map ( width_a => 32 ) port map ( a => mul_35_q_c, b => mul_17_q_c, sel => C_MUX2_44_SEL, q => mux2_44_q_c ); -- Multiplexor - 2 inputs (MUX2_45) ------------------------------------- MUX2_45: MUX2 generic map ( width_a => 32 ) port map ( a => reg_50_q_c, b => reg_46_q_c, sel => C_MUX2_45_SEL, q => mux2_45_q_c ); -- Multiplexor - 2 inputs (MUX2_46) ------------------------------------- MUX2_46: MUX2 generic map ( width_a => 32 ) port map ( a => reg_28_q_c, b => mux2_40_q_c, sel => C_MUX2_46_SEL, q => mux2_46_q_c ); -- Multiplexor - 2 inputs (MUX2_47) ------------------------------------- MUX2_47: MUX2 generic map ( width_a => 32 ) port map ( a => reg_49_q_c, b => PRI_IN_1, sel => C_MUX2_47_SEL, q => mux2_47_q_c ); -- Multiplexor - 2 inputs (MUX2_48) ------------------------------------- MUX2_48: MUX2 generic map ( width_a => 32 ) port map ( a => mux2_57_q_c, b => mux2_62_q_c, sel => C_MUX2_48_SEL, q => mux2_48_q_c ); -- Multiplexor - 2 inputs (MUX2_49) ------------------------------------- MUX2_49: MUX2 generic map ( width_a => 32 ) port map ( a => sub_59_q_c, b => mul_29_q_c, sel => C_MUX2_49_SEL, q => mux2_49_q_c ); -- Multiplexor - 2 inputs (MUX2_50) ------------------------------------- MUX2_50: MUX2 generic map ( width_a => 32 ) port map ( a => add_48_q_c, b => mul_28_q_c, sel => C_MUX2_50_SEL, q => mux2_50_q_c ); -- Multiplexor - 2 inputs (MUX2_51) ------------------------------------- MUX2_51: MUX2 generic map ( width_a => 32 ) port map ( a => mux2_62_q_c, b => mux2_51_q_c, sel => C_MUX2_51_SEL, q => mux2_51_q_c ); -- Multiplexor - 2 inputs (MUX2_52) ------------------------------------- MUX2_52: MUX2 generic map ( width_a => 32 ) port map ( a => mul_27_q_c, b => mul_9_q_c, sel => C_MUX2_52_SEL, q => mux2_52_q_c ); -- Multiplexor - 2 inputs (MUX2_53) ------------------------------------- MUX2_53: MUX2 generic map ( width_a => 32 ) port map ( a => mux2_65_q_c, b => mux2_44_q_c, sel => C_MUX2_53_SEL, q => mux2_53_q_c ); -- Multiplexor - 2 inputs (MUX2_54) ------------------------------------- MUX2_54: MUX2 generic map ( width_a => 32 ) port map ( a => reg_27_q_c, b => mux2_48_q_c, sel => C_MUX2_54_SEL, q => mux2_54_q_c ); -- Multiplexor - 2 inputs (MUX2_55) ------------------------------------- MUX2_55: MUX2 generic map ( width_a => 32 ) port map ( a => mux2_47_q_c, b => reg_48_q_c, sel => C_MUX2_55_SEL, q => mux2_55_q_c ); -- Multiplexor - 2 inputs (MUX2_56) ------------------------------------- MUX2_56: MUX2 generic map ( width_a => 32 ) port map ( a => reg_45_q_c, b => PRI_IN_1, sel => C_MUX2_56_SEL, q => mux2_56_q_c ); -- Multiplexor - 2 inputs (MUX2_57) ------------------------------------- MUX2_57: MUX2 generic map ( width_a => 32 ) port map ( a => reg_26_q_c, b => reg_33_q_c, sel => C_MUX2_57_SEL, q => mux2_57_q_c ); -- Multiplexor - 2 inputs (MUX2_58) ------------------------------------- MUX2_58: MUX2 generic map ( width_a => 32 ) port map ( a => reg_112_q_c, b => mux2_66_q_c, sel => C_MUX2_58_SEL, q => mux2_58_q_c ); -- Multiplexor - 2 inputs (MUX2_59) ------------------------------------- MUX2_59: MUX2 generic map ( width_a => 32 ) port map ( a => reg_103_q_c, b => reg_104_q_c, sel => C_MUX2_59_SEL, q => mux2_59_q_c ); -- Multiplexor - 2 inputs (MUX2_60) ------------------------------------- MUX2_60: MUX2 generic map ( width_a => 32 ) port map ( a => add_51_q_c, b => sub_57_q_c, sel => C_MUX2_60_SEL, q => mux2_60_q_c ); -- Multiplexor - 2 inputs (MUX2_61) ------------------------------------- MUX2_61: MUX2 generic map ( width_a => 32 ) port map ( a => add_44_q_c, b => mul_15_q_c, sel => C_MUX2_61_SEL, q => mux2_61_q_c ); -- Multiplexor - 2 inputs (MUX2_62) ------------------------------------- MUX2_62: MUX2 generic map ( width_a => 32 ) port map ( a => reg_29_q_c, b => mux2_37_q_c, sel => C_MUX2_62_SEL, q => mux2_62_q_c ); -- Multiplexor - 2 inputs (MUX2_63) ------------------------------------- MUX2_63: MUX2 generic map ( width_a => 32 ) port map ( a => mul_34_q_c, b => mux2_50_q_c, sel => C_MUX2_63_SEL, q => mux2_63_q_c ); -- Multiplexor - 2 inputs (MUX2_64) ------------------------------------- MUX2_64: MUX2 generic map ( width_a => 32 ) port map ( a => reg_35_q_c, b => reg_26_q_c, sel => C_MUX2_64_SEL, q => mux2_64_q_c ); -- Multiplexor - 2 inputs (MUX2_65) ------------------------------------- MUX2_65: MUX2 generic map ( width_a => 32 ) port map ( a => add_43_q_c, b => sub_48_q_c, sel => C_MUX2_65_SEL, q => mux2_65_q_c ); -- Multiplexor - 2 inputs (MUX2_66) ------------------------------------- MUX2_66: MUX2 generic map ( width_a => 32 ) port map ( a => reg_111_q_c, b => reg_110_q_c, sel => C_MUX2_66_SEL, q => mux2_66_q_c ); -- Multiplexor - 2 inputs (MUX2_67) ------------------------------------- MUX2_67: MUX2 generic map ( width_a => 32 ) port map ( a => reg_32_q_c, b => mux2_64_q_c, sel => C_MUX2_67_SEL, q => mux2_67_q_c ); -- Multiplexor - 2 inputs (MUX2_68) ------------------------------------- MUX2_68: MUX2 generic map ( width_a => 32 ) port map ( a => PRI_IN_32, b => reg_149_q_c, sel => C_MUX2_68_SEL, q => mux2_68_q_c ); -- Multiplexor - 2 inputs (MUX2_69) ------------------------------------- MUX2_69: MUX2 generic map ( width_a => 32 ) port map ( a => reg_47_q_c, b => mux2_41_q_c, sel => C_MUX2_69_SEL, q => mux2_69_q_c ); -- Multiplexor - 2 inputs (MUX2_70) ------------------------------------- MUX2_70: MUX2 generic map ( width_a => 32 ) port map ( a => mux2_56_q_c, b => reg_44_q_c, sel => C_MUX2_70_SEL, q => mux2_70_q_c ); -- Multiplier (MUL_1) --------------------------------------------------- MUL_1: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_167_q_c, b => mux2_10_q_c, q => mul_1_q_c ); -- Multiplier (MUL_2) --------------------------------------------------- MUL_2: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_69_q_c, b => PRI_IN_7, q => mul_2_q_c ); -- Multiplier (MUL_3) --------------------------------------------------- MUL_3: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_84_q_c, b => mux2_35_q_c, q => mul_3_q_c ); -- Multiplier (MUL_4) --------------------------------------------------- MUL_4: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => mux2_1_q_c, b => reg_168_q_c, q => mul_4_q_c ); -- Multiplier (MUL_5) --------------------------------------------------- MUL_5: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => mux2_7_q_c, b => mux2_23_q_c, q => mul_5_q_c ); -- Multiplier (MUL_6) --------------------------------------------------- MUL_6: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_91_q_c, b => reg_97_q_c, q => mul_6_q_c ); -- Multiplier (MUL_7) --------------------------------------------------- MUL_7: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_53_q_c, b => reg_75_q_c, q => mul_7_q_c ); -- Multiplier (MUL_8) --------------------------------------------------- MUL_8: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_77_q_c, b => PRI_IN_3, q => mul_8_q_c ); -- Multiplier (MUL_9) --------------------------------------------------- MUL_9: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_79_q_c, b => mux2_35_q_c, q => mul_9_q_c ); -- Multiplier (MUL_10) -------------------------------------------------- MUL_10: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_20_q_c, b => reg_52_q_c, q => mul_10_q_c ); -- Multiplier (MUL_11) -------------------------------------------------- MUL_11: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_18_q_c, b => PRI_IN_20, q => mul_11_q_c ); -- Multiplier (MUL_12) -------------------------------------------------- MUL_12: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_167_q_c, b => reg_25_q_c, q => mul_12_q_c ); -- Multiplier (MUL_13) -------------------------------------------------- MUL_13: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => mux2_23_q_c, b => reg_55_q_c, q => mul_13_q_c ); -- Multiplier (MUL_14) -------------------------------------------------- MUL_14: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_15_q_c, b => mux2_16_q_c, q => mul_14_q_c ); -- Multiplier (MUL_15) -------------------------------------------------- MUL_15: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_168_q_c, b => mux2_29_q_c, q => mul_15_q_c ); -- Multiplier (MUL_16) -------------------------------------------------- MUL_16: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_168_q_c, b => reg_169_q_c, q => mul_16_q_c ); -- Multiplier (MUL_17) -------------------------------------------------- MUL_17: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => PRI_IN_17, b => reg_90_q_c, q => mul_17_q_c ); -- Multiplier (MUL_18) -------------------------------------------------- MUL_18: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_83_q_c, b => reg_170_q_c, q => mul_18_q_c ); -- Multiplier (MUL_19) -------------------------------------------------- MUL_19: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => PRI_IN_0, b => PRI_IN_4, q => mul_19_q_c ); -- Multiplier (MUL_20) -------------------------------------------------- MUL_20: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => PRI_IN_0, b => reg_97_q_c, q => mul_20_q_c ); -- Multiplier (MUL_21) -------------------------------------------------- MUL_21: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_83_q_c, b => PRI_IN_25, q => mul_21_q_c ); -- Multiplier (MUL_22) -------------------------------------------------- MUL_22: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_171_q_c, b => reg_22_q_c, q => mul_22_q_c ); -- Multiplier (MUL_23) -------------------------------------------------- MUL_23: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_172_q_c, b => reg_15_q_c, q => mul_23_q_c ); -- Multiplier (MUL_24) -------------------------------------------------- MUL_24: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => mux2_6_q_c, b => reg_74_q_c, q => mul_24_q_c ); -- Multiplier (MUL_25) -------------------------------------------------- MUL_25: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_71_q_c, b => mux2_10_q_c, q => mul_25_q_c ); -- Multiplier (MUL_26) -------------------------------------------------- MUL_26: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => mux2_34_q_c, b => mux2_15_q_c, q => mul_26_q_c ); -- Multiplier (MUL_27) -------------------------------------------------- MUL_27: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_97_q_c, b => mux2_5_q_c, q => mul_27_q_c ); -- Multiplier (MUL_28) -------------------------------------------------- MUL_28: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => PRI_IN_31, b => reg_170_q_c, q => mul_28_q_c ); -- Multiplier (MUL_29) -------------------------------------------------- MUL_29: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_173_q_c, b => reg_84_q_c, q => mul_29_q_c ); -- Multiplier (MUL_30) -------------------------------------------------- MUL_30: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_36_q_c, b => mux2_8_q_c, q => mul_30_q_c ); -- Multiplier (MUL_31) -------------------------------------------------- MUL_31: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => PRI_IN_12, b => mux2_32_q_c, q => mul_31_q_c ); -- Multiplier (MUL_32) -------------------------------------------------- MUL_32: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_97_q_c, b => reg_42_q_c, q => mul_32_q_c ); -- Multiplier (MUL_33) -------------------------------------------------- MUL_33: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => PRI_IN_14, b => mux2_7_q_c, q => mul_33_q_c ); -- Multiplier (MUL_34) -------------------------------------------------- MUL_34: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_36_q_c, b => mux2_13_q_c, q => mul_34_q_c ); -- Multiplier (MUL_35) -------------------------------------------------- MUL_35: MUL generic map ( width_a => 16, width_b => 32 ) port map ( a => reg_86_q_c, b => reg_53_q_c, q => mul_35_q_c ); -- Register (REG_1) ----------------------------------------------------- REG_1: REG generic map ( width_a => 16 ) port map ( d => sub_14_q_c, clk => CLK, q => reg_1_q_c ); -- Register (REG_2) ----------------------------------------------------- REG_2: REG generic map ( width_a => 16 ) port map ( d => sub_4_q_c, clk => CLK, q => reg_2_q_c ); -- Register (REG_3) ----------------------------------------------------- REG_3: REG generic map ( width_a => 32 ) port map ( d => sub_39_q_c, clk => CLK, q => reg_3_q_c ); -- Register (REG_4) ----------------------------------------------------- REG_4: REG generic map ( width_a => 32 ) port map ( d => sub_54_q_c, clk => CLK, q => reg_4_q_c ); -- Register (REG_5) ----------------------------------------------------- REG_5: REG generic map ( width_a => 32 ) port map ( d => mul_20_q_c, clk => CLK, q => reg_5_q_c ); -- Register (REG_6) ----------------------------------------------------- REG_6: REG generic map ( width_a => 32 ) port map ( d => sub_64_q_c, clk => CLK, q => reg_6_q_c ); -- Register (REG_7) ----------------------------------------------------- REG_7: REG generic map ( width_a => 32 ) port map ( d => sub_48_q_c, clk => CLK, q => reg_7_q_c ); -- Register (REG_8) ----------------------------------------------------- REG_8: REG generic map ( width_a => 32 ) port map ( d => mul_35_q_c, clk => CLK, q => reg_8_q_c ); -- Register (REG_9) ----------------------------------------------------- REG_9: REG generic map ( width_a => 32 ) port map ( d => mux2_53_q_c, clk => CLK, q => reg_9_q_c ); -- Register (REG_10) ---------------------------------------------------- REG_10: REG generic map ( width_a => 32 ) port map ( d => mux2_44_q_c, clk => CLK, q => reg_10_q_c ); -- Register (REG_11) ---------------------------------------------------- REG_11: REG generic map ( width_a => 16 ) port map ( d => sub_10_q_c, clk => CLK, q => reg_11_q_c ); -- Register (REG_12) ---------------------------------------------------- REG_12: REG generic map ( width_a => 16 ) port map ( d => sub_12_q_c, clk => CLK, q => reg_12_q_c ); -- Register (REG_13) ---------------------------------------------------- REG_13: REG generic map ( width_a => 16 ) port map ( d => sub_17_q_c, clk => CLK, q => reg_13_q_c ); -- Register (REG_14) ---------------------------------------------------- REG_14: REG generic map ( width_a => 16 ) port map ( d => sub_19_q_c, clk => CLK, q => reg_14_q_c ); -- Register (REG_15) ---------------------------------------------------- REG_15: REG generic map ( width_a => 16 ) port map ( d => sub_27_q_c, clk => CLK, q => reg_15_q_c ); -- Register (REG_16) ---------------------------------------------------- REG_16: REG generic map ( width_a => 16 ) port map ( d => sub_29_q_c, clk => CLK, q => reg_16_q_c ); -- Register (REG_17) ---------------------------------------------------- REG_17: REG generic map ( width_a => 16 ) port map ( d => sub_30_q_c, clk => CLK, q => reg_17_q_c ); -- Register (REG_18) ---------------------------------------------------- REG_18: REG generic map ( width_a => 16 ) port map ( d => sub_34_q_c, clk => CLK, q => reg_18_q_c ); -- Register (REG_19) ---------------------------------------------------- REG_19: REG generic map ( width_a => 16 ) port map ( d => sub_35_q_c, clk => CLK, q => reg_19_q_c ); -- Register (REG_20) ---------------------------------------------------- REG_20: REG generic map ( width_a => 16 ) port map ( d => add_11_q_c, clk => CLK, q => reg_20_q_c ); -- Register (REG_21) ---------------------------------------------------- REG_21: REG generic map ( width_a => 16 ) port map ( d => add_13_q_c, clk => CLK, q => reg_21_q_c ); -- Register (REG_22) ---------------------------------------------------- REG_22: REG generic map ( width_a => 16 ) port map ( d => add_16_q_c, clk => CLK, q => reg_22_q_c ); -- Register (REG_23) ---------------------------------------------------- REG_23: REG generic map ( width_a => 16 ) port map ( d => add_20_q_c, clk => CLK, q => reg_23_q_c ); -- Register (REG_24) ---------------------------------------------------- REG_24: REG generic map ( width_a => 16 ) port map ( d => add_21_q_c, clk => CLK, q => reg_24_q_c ); -- Register (REG_25) ---------------------------------------------------- REG_25: REG generic map ( width_a => 16 ) port map ( d => add_29_q_c, clk => CLK, q => reg_25_q_c ); -- Register (REG_26) ---------------------------------------------------- REG_26: REG generic map ( width_a => 32 ) port map ( d => sub_36_q_c, clk => CLK, q => reg_26_q_c ); -- Register (REG_27) ---------------------------------------------------- REG_27: REG generic map ( width_a => 32 ) port map ( d => sub_67_q_c, clk => CLK, q => reg_27_q_c ); -- Register (REG_28) ---------------------------------------------------- REG_28: REG generic map ( width_a => 32 ) port map ( d => sub_68_q_c, clk => CLK, q => reg_28_q_c ); -- Register (REG_29) ---------------------------------------------------- REG_29: REG generic map ( width_a => 32 ) port map ( d => add_39_q_c, clk => CLK, q => reg_29_q_c ); -- Register (REG_30) ---------------------------------------------------- REG_30: REG generic map ( width_a => 32 ) port map ( d => add_49_q_c, clk => CLK, q => reg_30_q_c ); -- Register (REG_31) ---------------------------------------------------- REG_31: REG generic map ( width_a => 32 ) port map ( d => add_50_q_c, clk => CLK, q => reg_31_q_c ); -- Register (REG_32) ---------------------------------------------------- REG_32: REG generic map ( width_a => 32 ) port map ( d => add_66_q_c, clk => CLK, q => reg_32_q_c ); -- Register (REG_33) ---------------------------------------------------- REG_33: REG generic map ( width_a => 32 ) port map ( d => add_68_q_c, clk => CLK, q => reg_33_q_c ); -- Register (REG_34) ---------------------------------------------------- REG_34: REG generic map ( width_a => 32 ) port map ( d => mul_3_q_c, clk => CLK, q => reg_34_q_c ); -- Register (REG_35) ---------------------------------------------------- REG_35: REG generic map ( width_a => 32 ) port map ( d => mul_6_q_c, clk => CLK, q => reg_35_q_c ); -- Register (REG_36) ---------------------------------------------------- REG_36: REG generic map ( width_a => 16 ) port map ( d => sub_25_q_c, clk => CLK, q => reg_36_q_c ); -- Register (REG_37) ---------------------------------------------------- REG_37: REG generic map ( width_a => 32 ) port map ( d => sub_62_q_c, clk => CLK, q => reg_37_q_c ); -- Register (REG_38) ---------------------------------------------------- REG_38: REG generic map ( width_a => 32 ) port map ( d => mul_27_q_c, clk => CLK, q => reg_38_q_c ); -- Register (REG_39) ---------------------------------------------------- REG_39: REG generic map ( width_a => 32 ) port map ( d => mux2_52_q_c, clk => CLK, q => reg_39_q_c ); -- Register (REG_40) ---------------------------------------------------- REG_40: REG generic map ( width_a => 32 ) port map ( d => add_37_q_c, clk => CLK, q => reg_40_q_c ); -- Register (REG_41) ---------------------------------------------------- REG_41: REG generic map ( width_a => 32 ) port map ( d => add_58_q_c, clk => CLK, q => reg_41_q_c ); -- Register (REG_42) ---------------------------------------------------- REG_42: REG generic map ( width_a => 16 ) port map ( d => add_8_q_c, clk => CLK, q => reg_42_q_c ); -- Register (REG_43) ---------------------------------------------------- REG_43: REG generic map ( width_a => 16 ) port map ( d => add_27_q_c, clk => CLK, q => reg_43_q_c ); -- Register (REG_44) ---------------------------------------------------- REG_44: REG generic map ( width_a => 32 ) port map ( d => sub_38_q_c, clk => CLK, q => reg_44_q_c ); -- Register (REG_45) ---------------------------------------------------- REG_45: REG generic map ( width_a => 32 ) port map ( d => sub_44_q_c, clk => CLK, q => reg_45_q_c ); -- Register (REG_46) ---------------------------------------------------- REG_46: REG generic map ( width_a => 32 ) port map ( d => sub_53_q_c, clk => CLK, q => reg_46_q_c ); -- Register (REG_47) ---------------------------------------------------- REG_47: REG generic map ( width_a => 32 ) port map ( d => add_60_q_c, clk => CLK, q => reg_47_q_c ); -- Register (REG_48) ---------------------------------------------------- REG_48: REG generic map ( width_a => 32 ) port map ( d => mul_11_q_c, clk => CLK, q => reg_48_q_c ); -- Register (REG_49) ---------------------------------------------------- REG_49: REG generic map ( width_a => 32 ) port map ( d => mul_18_q_c, clk => CLK, q => reg_49_q_c ); -- Register (REG_50) ---------------------------------------------------- REG_50: REG generic map ( width_a => 32 ) port map ( d => mul_30_q_c, clk => CLK, q => reg_50_q_c ); -- Register (REG_51) ---------------------------------------------------- REG_51: REG generic map ( width_a => 16 ) port map ( d => sub_31_q_c, clk => CLK, q => reg_51_q_c ); -- Register (REG_52) ---------------------------------------------------- REG_52: REG generic map ( width_a => 16 ) port map ( d => add_6_q_c, clk => CLK, q => reg_52_q_c ); -- Register (REG_53) ---------------------------------------------------- REG_53: REG generic map ( width_a => 16 ) port map ( d => add_31_q_c, clk => CLK, q => reg_53_q_c ); -- Register (REG_54) ---------------------------------------------------- REG_54: REG generic map ( width_a => 16 ) port map ( d => add_32_q_c, clk => CLK, q => reg_54_q_c ); -- Register (REG_55) ---------------------------------------------------- REG_55: REG generic map ( width_a => 16 ) port map ( d => sub_2_q_c, clk => CLK, q => reg_55_q_c ); -- Register (REG_56) ---------------------------------------------------- REG_56: REG generic map ( width_a => 32 ) port map ( d => add_46_q_c, clk => CLK, q => reg_56_q_c ); -- Register (REG_57) ---------------------------------------------------- REG_57: REG generic map ( width_a => 32 ) port map ( d => sub_60_q_c, clk => CLK, q => reg_57_q_c ); -- Register (REG_58) ---------------------------------------------------- REG_58: REG generic map ( width_a => 32 ) port map ( d => mul_12_q_c, clk => CLK, q => reg_58_q_c ); -- Register (REG_59) ---------------------------------------------------- REG_59: REG generic map ( width_a => 32 ) port map ( d => add_62_q_c, clk => CLK, q => reg_59_q_c ); -- Register (REG_60) ---------------------------------------------------- REG_60: REG generic map ( width_a => 32 ) port map ( d => sub_51_q_c, clk => CLK, q => reg_60_q_c ); -- Register (REG_61) ---------------------------------------------------- REG_61: REG generic map ( width_a => 16 ) port map ( d => sub_1_q_c, clk => CLK, q => reg_61_q_c ); -- Register (REG_62) ---------------------------------------------------- REG_62: REG generic map ( width_a => 32 ) port map ( d => add_63_q_c, clk => CLK, q => reg_62_q_c ); -- Register (REG_63) ---------------------------------------------------- REG_63: REG generic map ( width_a => 32 ) port map ( d => sub_42_q_c, clk => CLK, q => reg_63_q_c ); -- Register (REG_64) ---------------------------------------------------- REG_64: REG generic map ( width_a => 16 ) port map ( d => sub_33_q_c, clk => CLK, q => reg_64_q_c ); -- Register (REG_65) ---------------------------------------------------- REG_65: REG generic map ( width_a => 16 ) port map ( d => add_15_q_c, clk => CLK, q => reg_65_q_c ); -- Register (REG_66) ---------------------------------------------------- REG_66: REG generic map ( width_a => 16 ) port map ( d => sub_23_q_c, clk => CLK, q => reg_66_q_c ); -- Register (REG_67) ---------------------------------------------------- REG_67: REG generic map ( width_a => 16 ) port map ( d => sub_18_q_c, clk => CLK, q => reg_67_q_c ); -- Register (REG_68) ---------------------------------------------------- REG_68: REG generic map ( width_a => 16 ) port map ( d => add_12_q_c, clk => CLK, q => reg_68_q_c ); -- Register (REG_69) ---------------------------------------------------- REG_69: REG generic map ( width_a => 16 ) port map ( d => sub_6_q_c, clk => CLK, q => reg_69_q_c ); -- Register (REG_70) ---------------------------------------------------- REG_70: REG generic map ( width_a => 16 ) port map ( d => sub_21_q_c, clk => CLK, q => reg_70_q_c ); -- Register (REG_71) ---------------------------------------------------- REG_71: REG generic map ( width_a => 16 ) port map ( d => add_14_q_c, clk => CLK, q => reg_71_q_c ); -- Register (REG_72) ---------------------------------------------------- REG_72: REG generic map ( width_a => 16 ) port map ( d => add_24_q_c, clk => CLK, q => reg_72_q_c ); -- Register (REG_73) ---------------------------------------------------- REG_73: REG generic map ( width_a => 16 ) port map ( d => add_23_q_c, clk => CLK, q => reg_73_q_c ); -- Register (REG_74) ---------------------------------------------------- REG_74: REG generic map ( width_a => 16 ) port map ( d => add_35_q_c, clk => CLK, q => reg_74_q_c ); -- Register (REG_75) ---------------------------------------------------- REG_75: REG generic map ( width_a => 16 ) port map ( d => sub_13_q_c, clk => CLK, q => reg_75_q_c ); -- Register (REG_76) ---------------------------------------------------- REG_76: REG generic map ( width_a => 16 ) port map ( d => sub_11_q_c, clk => CLK, q => reg_76_q_c ); -- Register (REG_77) ---------------------------------------------------- REG_77: REG generic map ( width_a => 16 ) port map ( d => sub_5_q_c, clk => CLK, q => reg_77_q_c ); -- Register (REG_78) ---------------------------------------------------- REG_78: REG generic map ( width_a => 16 ) port map ( d => sub_26_q_c, clk => CLK, q => reg_78_q_c ); -- Register (REG_79) ---------------------------------------------------- REG_79: REG generic map ( width_a => 16 ) port map ( d => add_19_q_c, clk => CLK, q => reg_79_q_c ); -- Register (REG_80) ---------------------------------------------------- REG_80: REG generic map ( width_a => 16 ) port map ( d => add_33_q_c, clk => CLK, q => reg_80_q_c ); -- Register (REG_81) ---------------------------------------------------- REG_81: REG generic map ( width_a => 16 ) port map ( d => add_25_q_c, clk => CLK, q => reg_81_q_c ); -- Register (REG_82) ---------------------------------------------------- REG_82: REG generic map ( width_a => 16 ) port map ( d => add_28_q_c, clk => CLK, q => reg_82_q_c ); -- Register (REG_83) ---------------------------------------------------- REG_83: REG generic map ( width_a => 16 ) port map ( d => add_30_q_c, clk => CLK, q => reg_83_q_c ); -- Register (REG_84) ---------------------------------------------------- REG_84: REG generic map ( width_a => 16 ) port map ( d => sub_22_q_c, clk => CLK, q => reg_84_q_c ); -- Register (REG_85) ---------------------------------------------------- REG_85: REG generic map ( width_a => 16 ) port map ( d => sub_24_q_c, clk => CLK, q => reg_85_q_c ); -- Register (REG_86) ---------------------------------------------------- REG_86: REG generic map ( width_a => 16 ) port map ( d => sub_9_q_c, clk => CLK, q => reg_86_q_c ); -- Register (REG_87) ---------------------------------------------------- REG_87: REG generic map ( width_a => 16 ) port map ( d => sub_32_q_c, clk => CLK, q => reg_87_q_c ); -- Register (REG_88) ---------------------------------------------------- REG_88: REG generic map ( width_a => 16 ) port map ( d => add_1_q_c, clk => CLK, q => reg_88_q_c ); -- Register (REG_89) ---------------------------------------------------- REG_89: REG generic map ( width_a => 16 ) port map ( d => mux2_14_q_c, clk => CLK, q => reg_89_q_c ); -- Register (REG_90) ---------------------------------------------------- REG_90: REG generic map ( width_a => 16 ) port map ( d => add_4_q_c, clk => CLK, q => reg_90_q_c ); -- Register (REG_91) ---------------------------------------------------- REG_91: REG generic map ( width_a => 16 ) port map ( d => sub_3_q_c, clk => CLK, q => reg_91_q_c ); -- Register (REG_92) ---------------------------------------------------- REG_92: REG generic map ( width_a => 16 ) port map ( d => sub_15_q_c, clk => CLK, q => reg_92_q_c ); -- Register (REG_93) ---------------------------------------------------- REG_93: REG generic map ( width_a => 16 ) port map ( d => sub_28_q_c, clk => CLK, q => reg_93_q_c ); -- Register (REG_94) ---------------------------------------------------- REG_94: REG generic map ( width_a => 16 ) port map ( d => add_10_q_c, clk => CLK, q => reg_94_q_c ); -- Register (REG_95) ---------------------------------------------------- REG_95: REG generic map ( width_a => 16 ) port map ( d => add_7_q_c, clk => CLK, q => reg_95_q_c ); -- Register (REG_96) ---------------------------------------------------- REG_96: REG generic map ( width_a => 16 ) port map ( d => add_3_q_c, clk => CLK, q => reg_96_q_c ); -- Register (REG_97) ---------------------------------------------------- REG_97: REG generic map ( width_a => 16 ) port map ( d => add_26_q_c, clk => CLK, q => reg_97_q_c ); -- Register (REG_98) ---------------------------------------------------- REG_98: REG generic map ( width_a => 16 ) port map ( d => add_5_q_c, clk => CLK, q => reg_98_q_c ); -- Register (REG_99) ---------------------------------------------------- REG_99: REG generic map ( width_a => 16 ) port map ( d => add_2_q_c, clk => CLK, q => reg_99_q_c ); -- Register (REG_100) --------------------------------------------------- REG_100: REG generic map ( width_a => 16 ) port map ( d => sub_16_q_c, clk => CLK, q => reg_100_q_c ); -- Register (REG_101) --------------------------------------------------- REG_101: REG generic map ( width_a => 32 ) port map ( d => sub_66_q_c, clk => CLK, q => reg_101_q_c ); -- Register (REG_102) --------------------------------------------------- REG_102: REG generic map ( width_a => 32 ) port map ( d => mul_19_q_c, clk => CLK, q => reg_102_q_c ); -- Register (REG_103) --------------------------------------------------- REG_103: REG generic map ( width_a => 32 ) port map ( d => mul_13_q_c, clk => CLK, q => reg_103_q_c ); -- Register (REG_104) --------------------------------------------------- REG_104: REG generic map ( width_a => 32 ) port map ( d => mul_31_q_c, clk => CLK, q => reg_104_q_c ); -- Register (REG_105) --------------------------------------------------- REG_105: REG generic map ( width_a => 32 ) port map ( d => add_65_q_c, clk => CLK, q => reg_105_q_c ); -- Register (REG_106) --------------------------------------------------- REG_106: REG generic map ( width_a => 32 ) port map ( d => add_36_q_c, clk => CLK, q => reg_106_q_c ); -- Register (REG_107) --------------------------------------------------- REG_107: REG generic map ( width_a => 32 ) port map ( d => mux2_61_q_c, clk => CLK, q => reg_107_q_c ); -- Register (REG_108) --------------------------------------------------- REG_108: REG generic map ( width_a => 32 ) port map ( d => mul_15_q_c, clk => CLK, q => reg_108_q_c ); -- Register (REG_109) --------------------------------------------------- REG_109: REG generic map ( width_a => 32 ) port map ( d => mul_8_q_c, clk => CLK, q => reg_109_q_c ); -- Register (REG_110) --------------------------------------------------- REG_110: REG generic map ( width_a => 32 ) port map ( d => sub_47_q_c, clk => CLK, q => reg_110_q_c ); -- Register (REG_111) --------------------------------------------------- REG_111: REG generic map ( width_a => 32 ) port map ( d => add_54_q_c, clk => CLK, q => reg_111_q_c ); -- Register (REG_112) --------------------------------------------------- REG_112: REG generic map ( width_a => 32 ) port map ( d => mul_24_q_c, clk => CLK, q => reg_112_q_c ); -- Register (REG_113) --------------------------------------------------- REG_113: REG generic map ( width_a => 32 ) port map ( d => mux2_49_q_c, clk => CLK, q => reg_113_q_c ); -- Register (REG_114) --------------------------------------------------- REG_114: REG generic map ( width_a => 32 ) port map ( d => mux2_49_q_c, clk => CLK, q => reg_114_q_c ); -- Register (REG_115) --------------------------------------------------- REG_115: REG generic map ( width_a => 32 ) port map ( d => mul_22_q_c, clk => CLK, q => reg_115_q_c ); -- Register (REG_116) --------------------------------------------------- REG_116: REG generic map ( width_a => 32 ) port map ( d => mul_14_q_c, clk => CLK, q => reg_116_q_c ); -- Register (REG_117) --------------------------------------------------- REG_117: REG generic map ( width_a => 32 ) port map ( d => mux2_43_q_c, clk => CLK, q => reg_117_q_c ); -- Register (REG_118) --------------------------------------------------- REG_118: REG generic map ( width_a => 32 ) port map ( d => mul_28_q_c, clk => CLK, q => reg_118_q_c ); -- Register (REG_119) --------------------------------------------------- REG_119: REG generic map ( width_a => 32 ) port map ( d => mux2_63_q_c, clk => CLK, q => reg_119_q_c ); -- Register (REG_120) --------------------------------------------------- REG_120: REG generic map ( width_a => 32 ) port map ( d => sub_63_q_c, clk => CLK, q => reg_120_q_c ); -- Register (REG_121) --------------------------------------------------- REG_121: REG generic map ( width_a => 32 ) port map ( d => sub_46_q_c, clk => CLK, q => reg_121_q_c ); -- Register (REG_122) --------------------------------------------------- REG_122: REG generic map ( width_a => 32 ) port map ( d => add_45_q_c, clk => CLK, q => reg_122_q_c ); -- Register (REG_123) --------------------------------------------------- REG_123: REG generic map ( width_a => 32 ) port map ( d => add_41_q_c, clk => CLK, q => reg_123_q_c ); -- Register (REG_124) --------------------------------------------------- REG_124: REG generic map ( width_a => 32 ) port map ( d => add_56_q_c, clk => CLK, q => reg_124_q_c ); -- Register (REG_125) --------------------------------------------------- REG_125: REG generic map ( width_a => 32 ) port map ( d => add_55_q_c, clk => CLK, q => reg_125_q_c ); -- Register (REG_126) --------------------------------------------------- REG_126: REG generic map ( width_a => 32 ) port map ( d => sub_45_q_c, clk => CLK, q => reg_126_q_c ); -- Register (REG_127) --------------------------------------------------- REG_127: REG generic map ( width_a => 32 ) port map ( d => add_61_q_c, clk => CLK, q => reg_127_q_c ); -- Register (REG_128) --------------------------------------------------- REG_128: REG generic map ( width_a => 32 ) port map ( d => add_42_q_c, clk => CLK, q => reg_128_q_c ); -- Register (REG_129) --------------------------------------------------- REG_129: REG generic map ( width_a => 32 ) port map ( d => add_70_q_c, clk => CLK, q => reg_129_q_c ); -- Register (REG_130) --------------------------------------------------- REG_130: REG generic map ( width_a => 32 ) port map ( d => sub_56_q_c, clk => CLK, q => reg_130_q_c ); -- Register (REG_131) --------------------------------------------------- REG_131: REG generic map ( width_a => 32 ) port map ( d => sub_37_q_c, clk => CLK, q => reg_131_q_c ); -- Register (REG_132) --------------------------------------------------- REG_132: REG generic map ( width_a => 32 ) port map ( d => add_59_q_c, clk => CLK, q => reg_132_q_c ); -- Register (REG_133) --------------------------------------------------- REG_133: REG generic map ( width_a => 32 ) port map ( d => mul_25_q_c, clk => CLK, q => reg_133_q_c ); -- Register (REG_134) --------------------------------------------------- REG_134: REG generic map ( width_a => 32 ) port map ( d => add_52_q_c, clk => CLK, q => reg_134_q_c ); -- Register (REG_135) --------------------------------------------------- REG_135: REG generic map ( width_a => 32 ) port map ( d => sub_43_q_c, clk => CLK, q => reg_135_q_c ); -- Register (REG_136) --------------------------------------------------- REG_136: REG generic map ( width_a => 32 ) port map ( d => sub_70_q_c, clk => CLK, q => reg_136_q_c ); -- Register (REG_137) --------------------------------------------------- REG_137: REG generic map ( width_a => 32 ) port map ( d => add_64_q_c, clk => CLK, q => reg_137_q_c ); -- Register (REG_138) --------------------------------------------------- REG_138: REG generic map ( width_a => 32 ) port map ( d => sub_52_q_c, clk => CLK, q => reg_138_q_c ); -- Register (REG_139) --------------------------------------------------- REG_139: REG generic map ( width_a => 32 ) port map ( d => mul_21_q_c, clk => CLK, q => reg_139_q_c ); -- Register (REG_140) --------------------------------------------------- REG_140: REG generic map ( width_a => 32 ) port map ( d => mul_23_q_c, clk => CLK, q => reg_140_q_c ); -- Register (REG_141) --------------------------------------------------- REG_141: REG generic map ( width_a => 32 ) port map ( d => add_47_q_c, clk => CLK, q => reg_141_q_c ); -- Register (REG_142) --------------------------------------------------- REG_142: REG generic map ( width_a => 32 ) port map ( d => add_40_q_c, clk => CLK, q => reg_142_q_c ); -- Register (REG_143) --------------------------------------------------- REG_143: REG generic map ( width_a => 32 ) port map ( d => mul_2_q_c, clk => CLK, q => reg_143_q_c ); -- Register (REG_144) --------------------------------------------------- REG_144: REG generic map ( width_a => 32 ) port map ( d => mul_16_q_c, clk => CLK, q => reg_144_q_c ); -- Register (REG_145) --------------------------------------------------- REG_145: REG generic map ( width_a => 32 ) port map ( d => mul_4_q_c, clk => CLK, q => reg_145_q_c ); -- Register (REG_146) --------------------------------------------------- REG_146: REG generic map ( width_a => 32 ) port map ( d => mul_33_q_c, clk => CLK, q => reg_146_q_c ); -- Register (REG_147) --------------------------------------------------- REG_147: REG generic map ( width_a => 32 ) port map ( d => add_38_q_c, clk => CLK, q => reg_147_q_c ); -- Register (REG_148) --------------------------------------------------- REG_148: REG generic map ( width_a => 32 ) port map ( d => sub_50_q_c, clk => CLK, q => reg_148_q_c ); -- Register (REG_149) --------------------------------------------------- REG_149: REG generic map ( width_a => 32 ) port map ( d => sub_55_q_c, clk => CLK, q => reg_149_q_c ); -- Register (REG_150) --------------------------------------------------- REG_150: REG generic map ( width_a => 32 ) port map ( d => add_67_q_c, clk => CLK, q => reg_150_q_c ); -- Register (REG_151) --------------------------------------------------- REG_151: REG generic map ( width_a => 32 ) port map ( d => mul_26_q_c, clk => CLK, q => reg_151_q_c ); -- Register (REG_152) --------------------------------------------------- REG_152: REG generic map ( width_a => 32 ) port map ( d => mul_32_q_c, clk => CLK, q => reg_152_q_c ); -- Register (REG_153) --------------------------------------------------- REG_153: REG generic map ( width_a => 32 ) port map ( d => sub_58_q_c, clk => CLK, q => reg_153_q_c ); -- Register (REG_154) --------------------------------------------------- REG_154: REG generic map ( width_a => 32 ) port map ( d => sub_41_q_c, clk => CLK, q => reg_154_q_c ); -- Register (REG_155) --------------------------------------------------- REG_155: REG generic map ( width_a => 32 ) port map ( d => sub_40_q_c, clk => CLK, q => reg_155_q_c ); -- Register (REG_156) --------------------------------------------------- REG_156: REG generic map ( width_a => 32 ) port map ( d => add_53_q_c, clk => CLK, q => reg_156_q_c ); -- Register (REG_157) --------------------------------------------------- REG_157: REG generic map ( width_a => 32 ) port map ( d => sub_61_q_c, clk => CLK, q => reg_157_q_c ); -- Register (REG_158) --------------------------------------------------- REG_158: REG generic map ( width_a => 32 ) port map ( d => mul_7_q_c, clk => CLK, q => reg_158_q_c ); -- Register (REG_159) --------------------------------------------------- REG_159: REG generic map ( width_a => 32 ) port map ( d => sub_49_q_c, clk => CLK, q => reg_159_q_c ); -- Register (REG_160) --------------------------------------------------- REG_160: REG generic map ( width_a => 32 ) port map ( d => add_57_q_c, clk => CLK, q => reg_160_q_c ); -- Register (REG_161) --------------------------------------------------- REG_161: REG generic map ( width_a => 32 ) port map ( d => mul_5_q_c, clk => CLK, q => reg_161_q_c ); -- Register (REG_162) --------------------------------------------------- REG_162: REG generic map ( width_a => 32 ) port map ( d => add_69_q_c, clk => CLK, q => reg_162_q_c ); -- Register (REG_163) --------------------------------------------------- REG_163: REG generic map ( width_a => 32 ) port map ( d => mux2_60_q_c, clk => CLK, q => reg_163_q_c ); -- Register (REG_164) --------------------------------------------------- REG_164: REG generic map ( width_a => 32 ) port map ( d => mul_1_q_c, clk => CLK, q => reg_164_q_c ); -- Register (REG_165) --------------------------------------------------- REG_165: REG generic map ( width_a => 32 ) port map ( d => sub_65_q_c, clk => CLK, q => reg_165_q_c ); -- Register (REG_166) --------------------------------------------------- REG_166: REG generic map ( width_a => 32 ) port map ( d => sub_69_q_c, clk => CLK, q => reg_166_q_c ); -- Register (REG_167) --------------------------------------------------- REG_167: REG generic map ( width_a => 16 ) port map ( d => add_17_q_c, clk => CLK, q => reg_167_q_c ); -- Register (REG_168) --------------------------------------------------- REG_168: REG generic map ( width_a => 16 ) port map ( d => add_34_q_c, clk => CLK, q => reg_168_q_c ); -- Register (REG_169) --------------------------------------------------- REG_169: REG generic map ( width_a => 16 ) port map ( d => add_9_q_c, clk => CLK, q => reg_169_q_c ); -- Register (REG_170) --------------------------------------------------- REG_170: REG generic map ( width_a => 16 ) port map ( d => add_22_q_c, clk => CLK, q => reg_170_q_c ); -- Register (REG_171) --------------------------------------------------- REG_171: REG generic map ( width_a => 16 ) port map ( d => add_18_q_c, clk => CLK, q => reg_171_q_c ); -- Register (REG_172) --------------------------------------------------- REG_172: REG generic map ( width_a => 16 ) port map ( d => sub_7_q_c, clk => CLK, q => reg_172_q_c ); -- Register (REG_173) --------------------------------------------------- REG_173: REG generic map ( width_a => 16 ) port map ( d => sub_8_q_c, clk => CLK, q => reg_173_q_c ); end architecture CIRCUIT_arch;