-- ------------------------------------------------------------------------- --
--                  This circuit was generated by CirGen                     --
-- ------------------------------------------------------------------------- --

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity CIRCUIT is
   port(

      -- Primary input gates
      PRI_IN_0 : in  std_logic_vector(15 downto 0);
      PRI_IN_1 : in  std_logic_vector(15 downto 0);
      PRI_IN_2 : in  std_logic_vector(15 downto 0);
      PRI_IN_3 : in  std_logic_vector(15 downto 0);
      PRI_IN_4 : in  std_logic_vector(15 downto 0);

      -- Primary output gates
      PRI_OUT_0 : out std_logic_vector(15 downto 0);
      PRI_OUT_1 : out std_logic_vector(15 downto 0);
      PRI_OUT_2 : out std_logic_vector(15 downto 0);
      PRI_OUT_3 : out std_logic_vector(15 downto 0);
      PRI_OUT_4 : out std_logic_vector(15 downto 0);

      -- Primary control gates
      C_MUX2_1_SEL : in  std_logic;
      C_MUX2_2_SEL : in  std_logic;
      C_MUX2_3_SEL : in  std_logic;
      C_MUX2_4_SEL : in  std_logic;
      C_MUX2_5_SEL : in  std_logic;
      CLK : in  std_logic
   );
end entity CIRCUIT;
-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture CIRCUIT_arch of CIRCUIT is

-- ############################# USED COMPONENTS ##############################

      component ADD
         generic (
            width_a : positive);  
         port(
            a : in std_logic_vector (width_a - 1 downto 0);
            b : in std_logic_vector (width_a - 1 downto 0);
            q : out std_logic_vector(width_a - 1 downto 0)
         );
      end component ADD;
    
      component MUX2
         generic (
            width_a : positive);  
         port(
            -- Inputs
            a   : in  std_logic_vector(width_a - 1 downto 0);
            b   : in  std_logic_vector(width_a - 1 downto 0);
            sel : in  std_logic;
            -- Outputs
            q   : out std_logic_vector(width_a - 1 downto 0)
         );
      end component MUX2;
    
      component REG
         generic (
            width_a : positive);  
         port(
            -- Inputs
            d   : in  std_logic_vector(width_a - 1 downto 0);
            clk : in  std_logic;
            -- Outputs
            q   : out std_logic_vector(width_a - 1 downto 0)
         );
      end component REG;
    
      component SUB
         generic (
            width_a : positive);  
         port(
            -- Inputs
            a : in std_logic_vector(width_a - 1 downto 0);
            b : in std_logic_vector(width_a - 1 downto 0);
            -- Outputs
            q : out std_logic_vector(width_a - 1 downto 0)
         );
      end component SUB;
    

-- #############################   CONNECTIONS   ##############################

   -- DATA CONNECTIONS
   signal sub_5_q_c : std_logic_vector(15 downto 0);
   signal mux2_2_q_c : std_logic_vector(15 downto 0);
   signal mux2_1_q_c : std_logic_vector(15 downto 0);
   signal sub_2_q_c : std_logic_vector(15 downto 0);
   signal sub_3_q_c : std_logic_vector(15 downto 0);
   signal mux2_4_q_c : std_logic_vector(15 downto 0);
   signal mux2_3_q_c : std_logic_vector(15 downto 0);
   signal mux2_5_q_c : std_logic_vector(15 downto 0);
   signal sub_4_q_c : std_logic_vector(15 downto 0);
   signal add_2_q_c : std_logic_vector(15 downto 0);
   signal reg_4_q_c : std_logic_vector(15 downto 0);
   signal reg_2_q_c : std_logic_vector(15 downto 0);
   signal reg_3_q_c : std_logic_vector(15 downto 0);
   signal reg_6_q_c : std_logic_vector(15 downto 0);
   signal reg_5_q_c : std_logic_vector(15 downto 0);
   signal reg_1_q_c : std_logic_vector(15 downto 0);
   signal add_4_q_c : std_logic_vector(15 downto 0);
   signal add_5_q_c : std_logic_vector(15 downto 0);
   signal add_1_q_c : std_logic_vector(15 downto 0);
   signal add_3_q_c : std_logic_vector(15 downto 0);
   signal sub_1_q_c : std_logic_vector(15 downto 0);
   signal reg_7_q_c : std_logic_vector(15 downto 0);
   signal reg_8_q_c : std_logic_vector(15 downto 0);
   signal reg_9_q_c : std_logic_vector(15 downto 0);
   signal reg_10_q_c : std_logic_vector(15 downto 0);

begin
      -- Connect signal to primary outputs
      PRI_OUT_0 <= reg_1_q_c;
      PRI_OUT_1 <= mux2_2_q_c;
      PRI_OUT_2 <= mux2_1_q_c;
      PRI_OUT_3 <= reg_7_q_c;
      PRI_OUT_4 <= reg_8_q_c;

      -- Subtracter (SUB_1) ---------------------------------------------------
      SUB_1: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_4_q_c,
         b => PRI_IN_2,
         q => sub_1_q_c
      );
    

      -- Subtracter (SUB_2) ---------------------------------------------------
      SUB_2: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_4,
         b => PRI_IN_0,
         q => sub_2_q_c
      );
    

      -- Subtracter (SUB_3) ---------------------------------------------------
      SUB_3: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_4_q_c,
         b => mux2_3_q_c,
         q => sub_3_q_c
      );
    

      -- Subtracter (SUB_4) ---------------------------------------------------
      SUB_4: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_0,
         b => mux2_5_q_c,
         q => sub_4_q_c
      );
    

      -- Subtracter (SUB_5) ---------------------------------------------------
      SUB_5: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_2,
         b => mux2_1_q_c,
         q => sub_5_q_c
      );
    

      -- Adder (ADD_1) --------------------------------------------------------
      ADD_1: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_9_q_c,
         b => PRI_IN_0,
         q => add_1_q_c
      );
    

      -- Adder (ADD_2) --------------------------------------------------------
      ADD_2: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_0,
         b => PRI_IN_1,
         q => add_2_q_c
      );
    

      -- Adder (ADD_3) --------------------------------------------------------
      ADD_3: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_1,
         b => PRI_IN_2,
         q => add_3_q_c
      );
    

      -- Adder (ADD_4) --------------------------------------------------------
      ADD_4: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_10_q_c,
         b => mux2_4_q_c,
         q => add_4_q_c
      );
    

      -- Adder (ADD_5) --------------------------------------------------------
      ADD_5: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_1,
         b => mux2_3_q_c,
         q => add_5_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_1) --------------------------------------
      MUX2_1: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_4_q_c,
         b   => reg_4_q_c,
         sel => C_MUX2_1_SEL,
         q   => mux2_1_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_2) --------------------------------------
      MUX2_2: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_2_q_c,
         b   => mux2_3_q_c,
         sel => C_MUX2_2_SEL,
         q   => mux2_2_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_3) --------------------------------------
      MUX2_3: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_3_q_c,
         b   => PRI_IN_3,
         sel => C_MUX2_3_SEL,
         q   => mux2_3_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_4) --------------------------------------
      MUX2_4: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_5_q_c,
         b   => reg_6_q_c,
         sel => C_MUX2_4_SEL,
         q   => mux2_4_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_5) --------------------------------------
      MUX2_5: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_5_q_c,
         b   => PRI_IN_1,
         sel => C_MUX2_5_SEL,
         q   => mux2_5_q_c
      );
    

      -- Register (REG_1) -----------------------------------------------------
      REG_1: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_5_q_c,
         clk => CLK,
         q   => reg_1_q_c
      );
    

      -- Register (REG_2) -----------------------------------------------------
      REG_2: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_4_q_c,
         clk => CLK,
         q   => reg_2_q_c
      );
    

      -- Register (REG_3) -----------------------------------------------------
      REG_3: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_5_q_c,
         clk => CLK,
         q   => reg_3_q_c
      );
    

      -- Register (REG_4) -----------------------------------------------------
      REG_4: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_1_q_c,
         clk => CLK,
         q   => reg_4_q_c
      );
    

      -- Register (REG_5) -----------------------------------------------------
      REG_5: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_3_q_c,
         clk => CLK,
         q   => reg_5_q_c
      );
    

      -- Register (REG_6) -----------------------------------------------------
      REG_6: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_1_q_c,
         clk => CLK,
         q   => reg_6_q_c
      );
    

      -- Register (REG_7) -----------------------------------------------------
      REG_7: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_2_q_c,
         clk => CLK,
         q   => reg_7_q_c
      );
    

      -- Register (REG_8) -----------------------------------------------------
      REG_8: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_3_q_c,
         clk => CLK,
         q   => reg_8_q_c
      );
    

      -- Register (REG_9) -----------------------------------------------------
      REG_9: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_4_q_c,
         clk => CLK,
         q   => reg_9_q_c
      );
    

      -- Register (REG_10) ----------------------------------------------------
      REG_10: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_2_q_c,
         clk => CLK,
         q   => reg_10_q_c
      );
    
end architecture CIRCUIT_arch;