-- -- Definition of CIRCUIT -- -- 12/14/05 22:06:01 -- -- LeonardoSpectrum Level 3, 2004a.63 -- library IEEE; use IEEE.STD_LOGIC_1164.all; entity CIRCUIT is port ( PRI_IN_0 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_1 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_2 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_3 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_4 : IN std_logic_vector (15 DOWNTO 0) ; PRI_OUT_0 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_1 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_2 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_3 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_4 : OUT std_logic_vector (15 DOWNTO 0) ; C_MUX2_1_SEL : IN std_logic ; C_MUX2_2_SEL : IN std_logic ; C_MUX2_3_SEL : IN std_logic ; C_MUX2_4_SEL : IN std_logic ; C_MUX2_5_SEL : IN std_logic ; CLK : IN std_logic) ; end CIRCUIT ; architecture CIRCUIT_arch of CIRCUIT is signal PRI_OUT_2_15_EXMPLR, PRI_OUT_2_14_EXMPLR, PRI_OUT_2_12_EXMPLR, PRI_OUT_2_10_EXMPLR, PRI_OUT_2_8_EXMPLR, PRI_OUT_2_6_EXMPLR, PRI_OUT_2_4_EXMPLR, PRI_OUT_2_2_EXMPLR, PRI_OUT_2_0_EXMPLR, reg_5_q_c_0, nx6, nx28, nx36, nx48, nx54, nx80, reg_5_q_c_1, nx88, nx90, nx104, nx110, nx112, nx1413, nx124, nx126, nx144, nx160, reg_5_q_c_2, nx172, nx202, nx204, nx224, nx226, nx244, reg_5_q_c_3, nx268, nx270, nx272, nx286, nx300, nx302, nx304, reg_3_q_c_3, nx322, nx1417, nx324, nx326, nx344, nx360, reg_5_q_c_4, nx372, nx402, nx404, reg_3_q_c_4, nx424, nx426, nx444, reg_5_q_c_5, nx468, nx470, nx472, nx486, nx500, nx502, nx504, reg_3_q_c_5, nx522, nx1425, nx524, nx526, nx544, nx560, reg_5_q_c_6, nx572, nx590, reg_6_q_c_6, nx1427, nx602, nx604, reg_3_q_c_6, nx624, nx626, nx644, reg_5_q_c_7, nx668, nx670, nx672, nx686, nx690, reg_6_q_c_7, nx700, nx1429, nx702, nx704, reg_3_q_c_7, nx722, nx1430, nx724, nx726, nx744, nx760, reg_5_q_c_8, nx772, nx790, reg_6_q_c_8, nx1431, nx802, nx804, reg_3_q_c_8, nx824, nx826, nx844, reg_5_q_c_9, nx868, nx870, nx872, nx886, nx890, reg_6_q_c_9, nx900, nx1433, nx902, nx904, reg_3_q_c_9, nx922, nx1435, nx924, nx926, nx944, nx960, reg_5_q_c_10, nx972, nx990, reg_6_q_c_10, nx1437, nx1002, nx1004, reg_3_q_c_10, nx1024, nx1026, nx1044, reg_5_q_c_11, nx1068, nx1070, nx1072, nx1086, nx1090, reg_6_q_c_11, nx1100, nx1440, nx1102, nx1104, reg_3_q_c_11, nx1122, nx1124, nx1126, nx1144, reg_5_q_c_12, nx1172, nx1190, reg_6_q_c_12, nx1443, nx1202, nx1204, reg_3_q_c_12, nx1224, nx1226, nx1244, reg_5_q_c_13, nx1268, nx1270, nx1272, nx1286, nx1290, reg_6_q_c_13, nx1300, nx1446, nx1302, nx1304, reg_3_q_c_13, nx1322, nx1324, nx1326, nx1344, reg_5_q_c_14, nx1372, nx1390, reg_6_q_c_14, nx1448, nx1402, nx1404, reg_3_q_c_14, nx1424, nx1426, nx1444, reg_5_q_c_15, nx1468, nx1472, nx1490, reg_6_q_c_15, nx1500, nx1450, nx1504, reg_3_q_c_15, nx1522, nx1526, nx1542, nx1544, nx1554, nx1562, nx1570, nx1572, nx1590, nx1592, nx1608, nx1610, nx1612, nx1630, nx1632, nx1648, nx1650, nx1652, nx1670, nx1672, nx1688, nx1690, nx1692, nx1710, nx1712, nx1728, nx1730, nx1732, nx1750, nx1752, nx1768, nx1770, nx1772, nx1790, nx1792, nx1808, nx1810, nx1812, nx1830, nx1832, nx1848, nx1852, nx1862, reg_4_q_c_0, reg_9_q_c_0, nx1874, nx1888, nx1902, nx1910, reg_4_q_c_1, reg_9_q_c_1, nx1924, nx1932, nx1934, nx1946, nx1948, nx1968, reg_4_q_c_2, nx1986, nx1988, nx1990, nx2000, nx2012, nx2014, nx2030, reg_4_q_c_3, nx2042, reg_9_q_c_3, nx2056, nx2064, nx2066, nx2078, nx2080, nx2100, reg_4_q_c_4, nx2118, nx2120, nx2122, nx2132, nx2144, nx2146, nx2162, reg_4_q_c_5, nx2174, reg_9_q_c_5, nx2188, nx2196, nx2198, nx2210, nx2212, nx2232, reg_4_q_c_6, nx2250, nx2252, nx2254, nx2264, nx2276, nx2278, nx2294, reg_4_q_c_7, nx2306, reg_9_q_c_7, nx2320, nx2328, nx2330, nx2342, nx2344, nx2364, reg_4_q_c_8, nx2382, nx2384, nx2386, nx2396, nx2408, nx2410, nx2426, reg_4_q_c_9, nx2438, reg_9_q_c_9, nx2452, nx2460, nx2462, nx2474, nx2476, nx2496, reg_4_q_c_10, nx2514, nx2516, nx2518, nx2528, nx2540, nx2542, nx2558, reg_4_q_c_11, nx2570, reg_9_q_c_11, nx2584, nx2592, nx2594, nx2608, nx2628, reg_4_q_c_12, nx2646, nx2648, nx2650, nx2660, nx2672, nx2674, reg_4_q_c_13, nx2702, reg_9_q_c_13, nx2716, nx2724, nx2726, nx2740, nx2760, reg_4_q_c_14, nx2778, nx2780, nx2782, nx2792, nx2804, nx2806, nx2826, reg_4_q_c_15, nx2834, reg_9_q_c_15, nx2846, nx2848, nx2858, reg_2_q_c_0, reg_10_q_c_0, nx2886, nx2900, nx2912, reg_2_q_c_1, reg_10_q_c_1, nx2916, nx2918, nx2926, nx2928, nx2940, reg_2_q_c_2, reg_10_q_c_2, nx2962, nx2972, nx2984, reg_2_q_c_3, nx2994, reg_10_q_c_3, nx3002, nx3004, nx3006, nx3014, nx3016, nx3028, reg_2_q_c_4, reg_10_q_c_4, nx3050, nx3060, nx3072, reg_2_q_c_5, nx3082, reg_10_q_c_5, nx3090, nx3092, nx3094, nx3102, nx3104, nx3116, reg_2_q_c_6, reg_10_q_c_6, nx3138, nx3148, nx3160, reg_2_q_c_7, nx3170, reg_10_q_c_7, nx3178, nx3180, nx3182, nx3190, nx3192, nx3204, reg_2_q_c_8, reg_10_q_c_8, nx3226, nx3236, nx3248, reg_2_q_c_9, nx3258, reg_10_q_c_9, nx3266, nx3268, nx3270, nx3278, nx3280, nx3292, reg_2_q_c_10, reg_10_q_c_10, nx3314, nx3324, nx3336, reg_2_q_c_11, nx3346, reg_10_q_c_11, nx3354, nx3356, nx3358, nx3366, nx3368, nx3380, reg_2_q_c_12, reg_10_q_c_12, nx3402, nx3412, nx3424, reg_2_q_c_13, nx3434, reg_10_q_c_13, nx3442, nx3444, nx3446, nx3454, nx3456, nx3468, reg_2_q_c_14, reg_10_q_c_14, nx3490, nx3500, nx3512, reg_2_q_c_15, nx3522, reg_10_q_c_15, nx3530, nx3534, nx3544, nx3556, nx1471, nx1479, nx1487, nx1499, nx1505, nx1513, nx1519, nx1521, nx1541, nx1548, nx1550, nx1555, nx1559, nx1565, nx1573, nx1580, nx1583, nx1597, nx1603, nx1605, nx1607, nx1611, nx1617, nx1635, nx1640, nx1643, nx1649, nx1655, nx1660, nx1665, nx1671, nx1679, nx1681, nx1695, nx1700, nx1703, nx1705, nx1709, nx1716, nx1733, nx1738, nx1740, nx1747, nx1753, nx1758, nx1761, nx1767, nx1776, nx1778, nx1791, nx1797, nx1799, nx1801, nx1805, nx1813, nx1829, nx1836, nx1838, nx1843, nx1849, nx1855, nx1858, nx1863, nx1871, nx1873, nx1883, nx1891, nx1893, nx1895, nx1898, nx1907, nx1928, nx1930, nx1935, nx1939, nx1945, nx1953, nx1975, nx1983, nx1985, nx1987, nx1991, nx1996, nx2018, nx2020, nx2025, nx2031, nx2037, nx2047, nx2069, nx2075, nx2077, nx2079, nx2082, nx2087, nx2113, nx2115, nx2121, nx2126, nx2131, nx2138, nx2154, nx2157, nx2161, nx2167, nx2169, nx2171, nx2176, nx2185, nx2191, nx2197, nx2199, nx2209, nx2211, nx2225, nx2227, nx2243, nx2245, nx2260, nx2263, nx2277, nx2279, nx2291, nx2293, nx2309, nx2311, nx2321, nx2333, nx2343, nx2345, nx2349, nx2365, nx2369, nx2377, nx2379, nx2383, nx2393, nx2395, nx2400, nx2403, nx2417, nx2421, nx2429, nx2431, nx2435, nx2449, nx2451, nx2456, nx2459, nx2473, nx2477, nx2482, nx2484, nx2487, nx2499, nx2501, nx2507, nx2511, nx2525, nx2529, nx2534, nx2537, nx2541, nx2550, nx2553, nx2559, nx2563, nx2581, nx2585, nx2590, nx2593, nx2597, nx2607, nx2609, nx2613, nx2616, nx2633, nx2637, nx2645, nx2647, nx2651, nx2659, nx2661, nx2665, nx2669, nx2682, nx2687, nx2695, nx2697, nx2701, nx2715, nx2717, nx2721, nx2730, nx2745, nx2747, nx2753, nx2755, nx2765, nx2769, nx2775, nx2779, nx2789, nx2796, nx2807, nx2810, nx2814, nx2819, nx2831, nx2839, nx2851, nx2854, nx2859, nx2862, nx2875, nx2881, nx2891, nx2895, nx2901, nx2904, nx2917, nx2923, nx2933, nx2936, nx2941, nx2945, nx2959, nx2966, nx2976, nx2979, nx2983, nx2987, nx3001, nx3009, nx3019, nx3022, nx3027, nx3031, nx3045, nx3053, nx3061, nx3071, nx3073, nx3089, nx3091, nx3103, nx3105, nx3117, nx3119, nx3135, nx3137, nx3179, nx3188, nx3191, nx3193, nx3195, nx3197, nx3199, nx1568, reg_3_q_c_2, nx1568_XX0_XREP1, nx1525, reg_3_q_c_1, nx1525_XX0_XREP3, nx1489, reg_3_q_c_0, nx1489_XX0_XREP5, nx1423, reg_6_q_c_5, nx490, nx1419, reg_6_q_c_4, nx390, nx1416, reg_6_q_c_3, nx290, nx1416_XX0_XREP11, nx1414, reg_6_q_c_2, nx190, nx1414_XX0_XREP13, nx1411, reg_6_q_c_1, nx108, nx1409, reg_6_q_c_0, nx24, nx1409_XX0_XREP17, nx3389, nx3390, nx3391, \[8955__XX0_XREP4\, nx3392, nx3393, nx3394, nx3395, nx3396, nx3397, nx3398, nx3399, nx3400, nx3401, nx3403, nx3404, nx3405, nx3406, nx3407, nx3408, nx3409, nx2872, nx3167, nx3169, nx2690, nx3410, nx3411, nx3413, nx3414, nx2738, nx3415, nx3416, nx3417, nx3418, nx3151, nx3153, nx3419, nx3420, nx3421, nx3422, nx2606, nx3423, nx3425, nx3426, nx3427, nx3428, nx3429, nx3430, nx3431, nx3432, nx3433, nx3435, nx3436, nx3437, nx1441, nx3438, nx3439, nx3440, nx3441, nx3443, nx3445, nx2011, nx3447, nx3448, nx3449, nx2057, nx3450, nx3451, nx3452, nx3453, nx3455, nx3457, nx1447, nx3458, nx3459, nx2105, nx3460, nx3461, nx3462, nx2147, nx3463, nx3464, nx1360, nx2134, nx3465, nx3466, nx2059, nx3467, nx1160, nx2041, nx3469, nx1961, nx1963, nx1949, nx3470, nx3471, nx3472, nx3473, nx1921, nx3474, nx3475, nx3476, nx3477, nx3478, nx3479, nx3480, nx3481, nx3482, nx3483, nx3484, nx3485, nx3486 : std_logic ; begin PRI_OUT_2(15) <= PRI_OUT_2_15_EXMPLR ; PRI_OUT_2(14) <= PRI_OUT_2_14_EXMPLR ; PRI_OUT_2(12) <= PRI_OUT_2_12_EXMPLR ; PRI_OUT_2(10) <= PRI_OUT_2_10_EXMPLR ; PRI_OUT_2(8) <= PRI_OUT_2_8_EXMPLR ; PRI_OUT_2(6) <= PRI_OUT_2_6_EXMPLR ; PRI_OUT_2(4) <= PRI_OUT_2_4_EXMPLR ; PRI_OUT_2(2) <= PRI_OUT_2_2_EXMPLR ; PRI_OUT_2(0) <= PRI_OUT_2_0_EXMPLR ; REG_8_reg_q_0 : dff port map ( Q=>PRI_OUT_4(0), QB=>OPEN, D=>nx80, CLK=> CLK); ix81 : ao21 port map ( Y=>nx80, A0=>nx1409, A1=>nx1489, B0=>nx1499); ix37 : oai21 port map ( Y=>nx36, A0=>PRI_IN_2(0), A1=>nx1471, B0=>nx28); REG_5_reg_q_0 : dff port map ( Q=>reg_5_q_c_0, QB=>OPEN, D=>nx6, CLK=>CLK ); ix1480 : inv02 port map ( Y=>nx1479, A=>PRI_IN_1(0)); ix29 : nand02 port map ( Y=>nx28, A0=>nx1471, A1=>PRI_IN_2(0)); ix1488 : mux21 port map ( Y=>nx1487, A0=>reg_5_q_c_0, A1=>PRI_IN_1(0), S0 =>C_MUX2_5_SEL); ix55 : aoi21 port map ( Y=>nx54, A0=>nx1489, A1=>nx1479, B0=>nx48); ix49 : nor02 port map ( Y=>nx48, A0=>nx1479, A1=>nx1489_XX0_XREP5); ix1500 : nor02 port map ( Y=>nx1499, A0=>nx1489, A1=>nx1409_XX0_XREP17); REG_8_reg_q_1 : dff port map ( Q=>PRI_OUT_4(1), QB=>OPEN, D=>nx144, CLK=> CLK); ix145 : xor2 port map ( Y=>nx144, A0=>nx1499, A1=>nx1505); ix1506 : xnor2 port map ( Y=>nx1505, A0=>nx3391, A1=>nx1525); ix113 : xor2 port map ( Y=>nx112, A0=>nx28, A1=>nx110); ix111 : xnor2 port map ( Y=>nx110, A0=>PRI_IN_2(1), A1=>nx3391); ix1514 : mux21 port map ( Y=>nx1513, A0=>reg_5_q_c_1, A1=>PRI_IN_1(1), S0 =>C_MUX2_5_SEL); REG_5_reg_q_1 : dff port map ( Q=>reg_5_q_c_1, QB=>OPEN, D=>nx90, CLK=> CLK); ix91 : xor2 port map ( Y=>nx90, A0=>nx1519, A1=>nx1521); ix1520 : nand02 port map ( Y=>nx1519, A0=>PRI_IN_2(0), A1=>PRI_IN_1(0)); ix1522 : xnor2 port map ( Y=>nx1521, A0=>PRI_IN_2(1), A1=>PRI_IN_1(1)); ix127 : xor2 port map ( Y=>nx126, A0=>nx48, A1=>nx124); ix125 : xnor2 port map ( Y=>nx124, A0=>PRI_IN_1(1), A1=>nx1525_XX0_XREP3 ); REG_8_reg_q_2 : dff port map ( Q=>PRI_OUT_4(2), QB=>OPEN, D=>nx244, CLK=> CLK); ix245 : xnor2 port map ( Y=>nx244, A0=>nx160, A1=>nx1541); ix161 : mux21 port map ( Y=>nx160, A0=>nx1499, A1=>nx1413, S0=>nx1505); ix1542 : xnor2 port map ( Y=>nx1541, A0=>nx1414_XX0_XREP13, A1=>nx1568); ix205 : xnor2 port map ( Y=>nx204, A0=>nx1548, A1=>nx202); ix1549 : mux21 port map ( Y=>nx1548, A0=>nx1550, A1=>nx28, S0=>nx110); ix1551 : inv02 port map ( Y=>nx1550, A=>PRI_IN_2(1)); ix203 : xnor2 port map ( Y=>nx202, A0=>PRI_IN_2(2), A1=>nx1414); ix1556 : mux21 port map ( Y=>nx1555, A0=>reg_5_q_c_2, A1=>PRI_IN_1(2), S0 =>C_MUX2_5_SEL); REG_5_reg_q_2 : dff port map ( Q=>reg_5_q_c_2, QB=>OPEN, D=>nx172, CLK=> CLK); ix173 : xor2 port map ( Y=>nx172, A0=>nx1559, A1=>nx1565); ix1560 : aoi32 port map ( Y=>nx1559, A0=>PRI_IN_2(0), A1=>PRI_IN_1(0), A2 =>nx88, B0=>PRI_IN_1(1), B1=>PRI_IN_2(1)); ix1566 : xnor2 port map ( Y=>nx1565, A0=>PRI_IN_2(2), A1=>PRI_IN_1(2)); ix227 : xnor2 port map ( Y=>nx226, A0=>nx1573, A1=>nx224); ix1574 : aoi22 port map ( Y=>nx1573, A0=>nx48, A1=>nx124, B0=>nx1413, B1 =>PRI_IN_1(1)); ix225 : xnor2 port map ( Y=>nx224, A0=>PRI_IN_1(2), A1=>nx1568_XX0_XREP1 ); REG_8_reg_q_3 : dff port map ( Q=>PRI_OUT_4(3), QB=>OPEN, D=>nx344, CLK=> CLK); ix345 : xor2 port map ( Y=>nx344, A0=>nx1580, A1=>nx1583); ix1582 : mux21 port map ( Y=>nx1580, A0=>nx160, A1=>nx1568, S0=>nx1541); ix1584 : xnor2 port map ( Y=>nx1583, A0=>nx1416, A1=>nx1611); ix305 : xor2 port map ( Y=>nx304, A0=>nx300, A1=>nx302); ix301 : mux21 port map ( Y=>nx300, A0=>PRI_IN_2(2), A1=>nx1548, S0=>nx202 ); ix303 : xnor2 port map ( Y=>nx302, A0=>PRI_IN_2(3), A1=>nx1416); ix1598 : mux21 port map ( Y=>nx1597, A0=>reg_5_q_c_3, A1=>PRI_IN_1(3), S0 =>C_MUX2_5_SEL); REG_5_reg_q_3 : dff port map ( Q=>reg_5_q_c_3, QB=>OPEN, D=>nx272, CLK=> CLK); ix273 : xnor2 port map ( Y=>nx272, A0=>nx268, A1=>nx1607); ix269 : oai22 port map ( Y=>nx268, A0=>nx1559, A1=>nx1565, B0=>nx1603, B1 =>nx1605); ix1604 : inv02 port map ( Y=>nx1603, A=>PRI_IN_1(2)); ix1606 : inv02 port map ( Y=>nx1605, A=>PRI_IN_2(2)); ix1608 : xnor2 port map ( Y=>nx1607, A0=>PRI_IN_2(3), A1=>PRI_IN_1(3)); ix1612 : mux21 port map ( Y=>nx1611, A0=>reg_3_q_c_3, A1=>PRI_IN_3(3), S0 =>C_MUX2_3_SEL); REG_3_reg_q_3 : dff port map ( Q=>reg_3_q_c_3, QB=>OPEN, D=>nx326, CLK=> CLK); ix327 : xor2 port map ( Y=>nx326, A0=>nx322, A1=>nx324); ix323 : oai22 port map ( Y=>nx322, A0=>nx1573, A1=>nx1617, B0=>nx1568, B1 =>nx1603); ix325 : xnor2 port map ( Y=>nx324, A0=>PRI_IN_1(3), A1=>nx1611); REG_8_reg_q_4 : dff port map ( Q=>PRI_OUT_4(4), QB=>OPEN, D=>nx444, CLK=> CLK); ix445 : xnor2 port map ( Y=>nx444, A0=>nx360, A1=>nx1635); ix361 : mux21 port map ( Y=>nx360, A0=>nx1580, A1=>nx1417, S0=>nx1583); ix1636 : xnor2 port map ( Y=>nx1635, A0=>nx3390, A1=>nx1665); ix405 : xnor2 port map ( Y=>nx404, A0=>nx1640, A1=>nx402); ix1642 : mux21 port map ( Y=>nx1640, A0=>nx1643, A1=>nx300, S0=>nx302); ix1644 : inv02 port map ( Y=>nx1643, A=>PRI_IN_2(3)); ix403 : xnor2 port map ( Y=>nx402, A0=>PRI_IN_2(4), A1=>nx3390); ix1650 : mux21 port map ( Y=>nx1649, A0=>reg_5_q_c_4, A1=>PRI_IN_1(4), S0 =>C_MUX2_5_SEL); REG_5_reg_q_4 : dff port map ( Q=>reg_5_q_c_4, QB=>OPEN, D=>nx372, CLK=> CLK); ix373 : xor2 port map ( Y=>nx372, A0=>nx1655, A1=>nx1660); ix1656 : aoi22 port map ( Y=>nx1655, A0=>PRI_IN_1(3), A1=>PRI_IN_2(3), B0 =>nx268, B1=>nx270); ix1662 : xnor2 port map ( Y=>nx1660, A0=>PRI_IN_2(4), A1=>PRI_IN_1(4)); ix1666 : mux21 port map ( Y=>nx1665, A0=>reg_3_q_c_4, A1=>PRI_IN_3(4), S0 =>C_MUX2_3_SEL); REG_3_reg_q_4 : dff port map ( Q=>reg_3_q_c_4, QB=>OPEN, D=>nx426, CLK=> CLK); ix427 : xnor2 port map ( Y=>nx426, A0=>nx1671, A1=>nx424); ix1672 : aoi22 port map ( Y=>nx1671, A0=>nx1417, A1=>PRI_IN_1(3), B0=> nx322, B1=>nx324); ix425 : xnor2 port map ( Y=>nx424, A0=>PRI_IN_1(4), A1=>nx1665); REG_8_reg_q_5 : dff port map ( Q=>PRI_OUT_4(5), QB=>OPEN, D=>nx544, CLK=> CLK); ix545 : xor2 port map ( Y=>nx544, A0=>nx1679, A1=>nx1681); ix1680 : mux21 port map ( Y=>nx1679, A0=>nx360, A1=>nx1665, S0=>nx1635); ix1682 : xnor2 port map ( Y=>nx1681, A0=>nx1423, A1=>nx1709); ix505 : xor2 port map ( Y=>nx504, A0=>nx500, A1=>nx502); ix501 : mux21 port map ( Y=>nx500, A0=>PRI_IN_2(4), A1=>nx1640, S0=>nx402 ); ix503 : xnor2 port map ( Y=>nx502, A0=>PRI_IN_2(5), A1=>nx3389); ix1696 : mux21 port map ( Y=>nx1695, A0=>reg_5_q_c_5, A1=>PRI_IN_1(5), S0 =>C_MUX2_5_SEL); REG_5_reg_q_5 : dff port map ( Q=>reg_5_q_c_5, QB=>OPEN, D=>nx472, CLK=> CLK); ix473 : xnor2 port map ( Y=>nx472, A0=>nx468, A1=>nx1705); ix469 : oai22 port map ( Y=>nx468, A0=>nx1655, A1=>nx1660, B0=>nx1700, B1 =>nx1703); ix1702 : inv02 port map ( Y=>nx1700, A=>PRI_IN_1(4)); ix1704 : inv02 port map ( Y=>nx1703, A=>PRI_IN_2(4)); ix1706 : xnor2 port map ( Y=>nx1705, A0=>PRI_IN_2(5), A1=>PRI_IN_1(5)); ix1710 : mux21 port map ( Y=>nx1709, A0=>reg_3_q_c_5, A1=>PRI_IN_3(5), S0 =>C_MUX2_3_SEL); REG_3_reg_q_5 : dff port map ( Q=>reg_3_q_c_5, QB=>OPEN, D=>nx526, CLK=> CLK); ix527 : xor2 port map ( Y=>nx526, A0=>nx522, A1=>nx524); ix523 : oai22 port map ( Y=>nx522, A0=>nx1671, A1=>nx1716, B0=>nx1665, B1 =>nx1700); ix525 : xnor2 port map ( Y=>nx524, A0=>PRI_IN_1(5), A1=>nx1709); REG_8_reg_q_6 : dff port map ( Q=>PRI_OUT_4(6), QB=>OPEN, D=>nx644, CLK=> CLK); ix645 : xnor2 port map ( Y=>nx644, A0=>nx560, A1=>nx1733); ix561 : mux21 port map ( Y=>nx560, A0=>nx1679, A1=>nx1425, S0=>nx1681); ix1734 : xnor2 port map ( Y=>nx1733, A0=>nx1427, A1=>nx1761); ix615 : ao21 port map ( Y=>nx1427, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_6, B0 =>nx590); REG_6_reg_q_6 : dff port map ( Q=>reg_6_q_c_6, QB=>OPEN, D=>nx604, CLK=> CLK); ix605 : xnor2 port map ( Y=>nx604, A0=>nx1738, A1=>nx602); ix1739 : mux21 port map ( Y=>nx1738, A0=>nx1740, A1=>nx500, S0=>nx502); ix1742 : inv02 port map ( Y=>nx1740, A=>PRI_IN_2(5)); ix603 : xnor2 port map ( Y=>nx602, A0=>PRI_IN_2(6), A1=>nx1427); ix591 : nor02 port map ( Y=>nx590, A0=>C_MUX2_4_SEL, A1=>nx1747); ix1748 : mux21 port map ( Y=>nx1747, A0=>reg_5_q_c_6, A1=>PRI_IN_1(6), S0 =>C_MUX2_5_SEL); REG_5_reg_q_6 : dff port map ( Q=>reg_5_q_c_6, QB=>OPEN, D=>nx572, CLK=> CLK); ix573 : xor2 port map ( Y=>nx572, A0=>nx1753, A1=>nx1758); ix1754 : aoi22 port map ( Y=>nx1753, A0=>PRI_IN_1(5), A1=>PRI_IN_2(5), B0 =>nx468, B1=>nx470); ix1759 : xnor2 port map ( Y=>nx1758, A0=>PRI_IN_2(6), A1=>PRI_IN_1(6)); ix1762 : mux21 port map ( Y=>nx1761, A0=>reg_3_q_c_6, A1=>PRI_IN_3(6), S0 =>C_MUX2_3_SEL); REG_3_reg_q_6 : dff port map ( Q=>reg_3_q_c_6, QB=>OPEN, D=>nx626, CLK=> CLK); ix627 : xnor2 port map ( Y=>nx626, A0=>nx1767, A1=>nx624); ix1768 : aoi22 port map ( Y=>nx1767, A0=>nx1425, A1=>PRI_IN_1(5), B0=> nx522, B1=>nx524); ix625 : xnor2 port map ( Y=>nx624, A0=>PRI_IN_1(6), A1=>nx1761); REG_8_reg_q_7 : dff port map ( Q=>PRI_OUT_4(7), QB=>OPEN, D=>nx744, CLK=> CLK); ix745 : xor2 port map ( Y=>nx744, A0=>nx1776, A1=>nx1778); ix1777 : mux21 port map ( Y=>nx1776, A0=>nx560, A1=>nx1761, S0=>nx1733); ix1779 : xnor2 port map ( Y=>nx1778, A0=>nx1429, A1=>nx1805); ix715 : ao21 port map ( Y=>nx1429, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_7, B0 =>nx690); REG_6_reg_q_7 : dff port map ( Q=>reg_6_q_c_7, QB=>OPEN, D=>nx704, CLK=> CLK); ix705 : xor2 port map ( Y=>nx704, A0=>nx700, A1=>nx702); ix701 : mux21 port map ( Y=>nx700, A0=>PRI_IN_2(6), A1=>nx1738, S0=>nx602 ); ix703 : xnor2 port map ( Y=>nx702, A0=>PRI_IN_2(7), A1=>nx1429); ix691 : nor02 port map ( Y=>nx690, A0=>C_MUX2_4_SEL, A1=>nx1791); ix1792 : mux21 port map ( Y=>nx1791, A0=>reg_5_q_c_7, A1=>PRI_IN_1(7), S0 =>C_MUX2_5_SEL); REG_5_reg_q_7 : dff port map ( Q=>reg_5_q_c_7, QB=>OPEN, D=>nx672, CLK=> CLK); ix673 : xnor2 port map ( Y=>nx672, A0=>nx668, A1=>nx1801); ix669 : oai22 port map ( Y=>nx668, A0=>nx1753, A1=>nx1758, B0=>nx1797, B1 =>nx1799); ix1798 : inv02 port map ( Y=>nx1797, A=>PRI_IN_1(6)); ix1800 : inv02 port map ( Y=>nx1799, A=>PRI_IN_2(6)); ix1802 : xnor2 port map ( Y=>nx1801, A0=>PRI_IN_2(7), A1=>PRI_IN_1(7)); ix1806 : mux21 port map ( Y=>nx1805, A0=>reg_3_q_c_7, A1=>PRI_IN_3(7), S0 =>C_MUX2_3_SEL); REG_3_reg_q_7 : dff port map ( Q=>reg_3_q_c_7, QB=>OPEN, D=>nx726, CLK=> CLK); ix727 : xor2 port map ( Y=>nx726, A0=>nx722, A1=>nx724); ix723 : oai22 port map ( Y=>nx722, A0=>nx1767, A1=>nx1813, B0=>nx1761, B1 =>nx1797); ix725 : xnor2 port map ( Y=>nx724, A0=>PRI_IN_1(7), A1=>nx1805); REG_8_reg_q_8 : dff port map ( Q=>PRI_OUT_4(8), QB=>OPEN, D=>nx844, CLK=> CLK); ix845 : xnor2 port map ( Y=>nx844, A0=>nx760, A1=>nx1829); ix761 : mux21 port map ( Y=>nx760, A0=>nx1776, A1=>nx1430, S0=>nx1778); ix1830 : xnor2 port map ( Y=>nx1829, A0=>nx1431, A1=>nx1858); ix815 : ao21 port map ( Y=>nx1431, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_8, B0 =>nx790); REG_6_reg_q_8 : dff port map ( Q=>reg_6_q_c_8, QB=>OPEN, D=>nx804, CLK=> CLK); ix805 : xnor2 port map ( Y=>nx804, A0=>nx1836, A1=>nx802); ix1837 : mux21 port map ( Y=>nx1836, A0=>nx1838, A1=>nx700, S0=>nx702); ix1839 : inv02 port map ( Y=>nx1838, A=>PRI_IN_2(7)); ix803 : xnor2 port map ( Y=>nx802, A0=>PRI_IN_2(8), A1=>nx1431); ix791 : nor02 port map ( Y=>nx790, A0=>C_MUX2_4_SEL, A1=>nx1843); ix1844 : mux21 port map ( Y=>nx1843, A0=>reg_5_q_c_8, A1=>PRI_IN_1(8), S0 =>C_MUX2_5_SEL); REG_5_reg_q_8 : dff port map ( Q=>reg_5_q_c_8, QB=>OPEN, D=>nx772, CLK=> CLK); ix773 : xor2 port map ( Y=>nx772, A0=>nx1849, A1=>nx1855); ix1850 : aoi22 port map ( Y=>nx1849, A0=>PRI_IN_1(7), A1=>PRI_IN_2(7), B0 =>nx668, B1=>nx670); ix1856 : xnor2 port map ( Y=>nx1855, A0=>PRI_IN_2(8), A1=>PRI_IN_1(8)); ix1859 : mux21 port map ( Y=>nx1858, A0=>reg_3_q_c_8, A1=>PRI_IN_3(8), S0 =>C_MUX2_3_SEL); REG_3_reg_q_8 : dff port map ( Q=>reg_3_q_c_8, QB=>OPEN, D=>nx826, CLK=> CLK); ix827 : xnor2 port map ( Y=>nx826, A0=>nx1863, A1=>nx824); ix1864 : aoi22 port map ( Y=>nx1863, A0=>nx1430, A1=>PRI_IN_1(7), B0=> nx722, B1=>nx724); ix825 : xnor2 port map ( Y=>nx824, A0=>PRI_IN_1(8), A1=>nx1858); REG_8_reg_q_9 : dff port map ( Q=>PRI_OUT_4(9), QB=>OPEN, D=>nx944, CLK=> CLK); ix945 : xor2 port map ( Y=>nx944, A0=>nx1871, A1=>nx1873); ix1872 : mux21 port map ( Y=>nx1871, A0=>nx760, A1=>nx1858, S0=>nx1829); ix1874 : xnor2 port map ( Y=>nx1873, A0=>nx1433, A1=>nx1898); ix915 : ao21 port map ( Y=>nx1433, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_9, B0 =>nx890); REG_6_reg_q_9 : dff port map ( Q=>reg_6_q_c_9, QB=>OPEN, D=>nx904, CLK=> CLK); ix905 : xor2 port map ( Y=>nx904, A0=>nx900, A1=>nx902); ix901 : mux21 port map ( Y=>nx900, A0=>PRI_IN_2(8), A1=>nx1836, S0=>nx802 ); ix903 : xnor2 port map ( Y=>nx902, A0=>PRI_IN_2(9), A1=>nx1433); ix891 : nor02 port map ( Y=>nx890, A0=>C_MUX2_4_SEL, A1=>nx1883); ix1884 : mux21 port map ( Y=>nx1883, A0=>reg_5_q_c_9, A1=>PRI_IN_1(9), S0 =>C_MUX2_5_SEL); REG_5_reg_q_9 : dff port map ( Q=>reg_5_q_c_9, QB=>OPEN, D=>nx872, CLK=> CLK); ix873 : xnor2 port map ( Y=>nx872, A0=>nx868, A1=>nx1895); ix869 : oai22 port map ( Y=>nx868, A0=>nx1849, A1=>nx1855, B0=>nx1891, B1 =>nx1893); ix1892 : inv02 port map ( Y=>nx1891, A=>PRI_IN_1(8)); ix1894 : inv02 port map ( Y=>nx1893, A=>PRI_IN_2(8)); ix1896 : xnor2 port map ( Y=>nx1895, A0=>PRI_IN_2(9), A1=>PRI_IN_1(9)); ix1900 : mux21 port map ( Y=>nx1898, A0=>reg_3_q_c_9, A1=>PRI_IN_3(9), S0 =>C_MUX2_3_SEL); REG_3_reg_q_9 : dff port map ( Q=>reg_3_q_c_9, QB=>OPEN, D=>nx926, CLK=> CLK); ix927 : xor2 port map ( Y=>nx926, A0=>nx922, A1=>nx924); ix923 : oai22 port map ( Y=>nx922, A0=>nx1863, A1=>nx1907, B0=>nx1858, B1 =>nx1891); ix925 : xnor2 port map ( Y=>nx924, A0=>PRI_IN_1(9), A1=>nx1898); REG_8_reg_q_10 : dff port map ( Q=>PRI_OUT_4(10), QB=>OPEN, D=>nx1044, CLK=>CLK); ix1045 : xnor2 port map ( Y=>nx1044, A0=>nx960, A1=>nx1921); ix961 : mux21 port map ( Y=>nx960, A0=>nx1871, A1=>nx1435, S0=>nx1873); ix1015 : ao21 port map ( Y=>nx1437, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_10, B0=>nx990); REG_6_reg_q_10 : dff port map ( Q=>reg_6_q_c_10, QB=>OPEN, D=>nx1004, CLK =>CLK); ix1005 : xnor2 port map ( Y=>nx1004, A0=>nx1928, A1=>nx1002); ix1929 : mux21 port map ( Y=>nx1928, A0=>nx1930, A1=>nx900, S0=>nx902); ix1931 : inv02 port map ( Y=>nx1930, A=>PRI_IN_2(9)); ix1003 : xnor2 port map ( Y=>nx1002, A0=>PRI_IN_2(10), A1=>nx3476); ix991 : nor02 port map ( Y=>nx990, A0=>C_MUX2_4_SEL, A1=>nx1935); ix1936 : mux21 port map ( Y=>nx1935, A0=>reg_5_q_c_10, A1=>PRI_IN_1(10), S0=>C_MUX2_5_SEL); REG_5_reg_q_10 : dff port map ( Q=>reg_5_q_c_10, QB=>OPEN, D=>nx972, CLK =>CLK); ix973 : xor2 port map ( Y=>nx972, A0=>nx1939, A1=>nx1945); ix1940 : aoi22 port map ( Y=>nx1939, A0=>PRI_IN_1(9), A1=>PRI_IN_2(9), B0 =>nx868, B1=>nx870); ix1946 : xnor2 port map ( Y=>nx1945, A0=>PRI_IN_2(10), A1=>PRI_IN_1(10)); REG_3_reg_q_10 : dff port map ( Q=>reg_3_q_c_10, QB=>OPEN, D=>nx1026, CLK =>CLK); ix1027 : xnor2 port map ( Y=>nx1026, A0=>nx1953, A1=>nx1024); ix1954 : aoi22 port map ( Y=>nx1953, A0=>nx1435, A1=>PRI_IN_1(9), B0=> nx922, B1=>nx924); ix1025 : xnor2 port map ( Y=>nx1024, A0=>PRI_IN_1(10), A1=>nx1949); REG_8_reg_q_11 : dff port map ( Q=>PRI_OUT_4(11), QB=>OPEN, D=>nx1144, CLK=>CLK); ix1145 : xor2 port map ( Y=>nx1144, A0=>nx1961, A1=>nx1963); ix1115 : ao21 port map ( Y=>nx1440, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_11, B0=>nx1090); REG_6_reg_q_11 : dff port map ( Q=>reg_6_q_c_11, QB=>OPEN, D=>nx1104, CLK =>CLK); ix1105 : xor2 port map ( Y=>nx1104, A0=>nx1100, A1=>nx1102); ix1101 : mux21 port map ( Y=>nx1100, A0=>PRI_IN_2(10), A1=>nx1928, S0=> nx1002); ix1103 : xnor2 port map ( Y=>nx1102, A0=>PRI_IN_2(11), A1=>nx3478); ix1091 : nor02 port map ( Y=>nx1090, A0=>C_MUX2_4_SEL, A1=>nx1975); ix1976 : mux21 port map ( Y=>nx1975, A0=>reg_5_q_c_11, A1=>PRI_IN_1(11), S0=>C_MUX2_5_SEL); REG_5_reg_q_11 : dff port map ( Q=>reg_5_q_c_11, QB=>OPEN, D=>nx1072, CLK =>CLK); ix1073 : xnor2 port map ( Y=>nx1072, A0=>nx1068, A1=>nx1987); ix1069 : oai22 port map ( Y=>nx1068, A0=>nx1939, A1=>nx1945, B0=>nx1983, B1=>nx1985); ix1984 : inv02 port map ( Y=>nx1983, A=>PRI_IN_1(10)); ix1986 : inv02 port map ( Y=>nx1985, A=>PRI_IN_2(10)); ix1988 : xnor2 port map ( Y=>nx1987, A0=>PRI_IN_2(11), A1=>PRI_IN_1(11)); ix1992 : mux21 port map ( Y=>nx1991, A0=>reg_3_q_c_11, A1=>PRI_IN_3(11), S0=>C_MUX2_3_SEL); REG_3_reg_q_11 : dff port map ( Q=>reg_3_q_c_11, QB=>OPEN, D=>nx1126, CLK =>CLK); ix1127 : xor2 port map ( Y=>nx1126, A0=>nx1122, A1=>nx1124); ix1123 : oai22 port map ( Y=>nx1122, A0=>nx1953, A1=>nx1996, B0=>nx1949, B1=>nx1983); ix1125 : xnor2 port map ( Y=>nx1124, A0=>PRI_IN_1(11), A1=>nx1991); REG_8_reg_q_12 : dff port map ( Q=>PRI_OUT_4(12), QB=>OPEN, D=>nx1244, CLK=>CLK); ix1245 : xnor2 port map ( Y=>nx1244, A0=>nx1160, A1=>nx3469); ix1215 : ao21 port map ( Y=>nx1443, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_12, B0=>nx1190); REG_6_reg_q_12 : dff port map ( Q=>reg_6_q_c_12, QB=>OPEN, D=>nx1204, CLK =>CLK); ix1205 : xnor2 port map ( Y=>nx1204, A0=>nx2018, A1=>nx1202); ix2019 : mux21 port map ( Y=>nx2018, A0=>nx2020, A1=>nx1100, S0=>nx1102); ix2021 : inv02 port map ( Y=>nx2020, A=>PRI_IN_2(11)); ix1203 : xnor2 port map ( Y=>nx1202, A0=>PRI_IN_2(12), A1=>nx1443); ix1191 : nor02 port map ( Y=>nx1190, A0=>C_MUX2_4_SEL, A1=>nx2025); ix2026 : mux21 port map ( Y=>nx2025, A0=>reg_5_q_c_12, A1=>PRI_IN_1(12), S0=>C_MUX2_5_SEL); REG_5_reg_q_12 : dff port map ( Q=>reg_5_q_c_12, QB=>OPEN, D=>nx1172, CLK =>CLK); ix1173 : xor2 port map ( Y=>nx1172, A0=>nx2031, A1=>nx2037); ix2032 : aoi22 port map ( Y=>nx2031, A0=>PRI_IN_1(11), A1=>PRI_IN_2(11), B0=>nx1068, B1=>nx1070); ix2038 : xnor2 port map ( Y=>nx2037, A0=>PRI_IN_2(12), A1=>PRI_IN_1(12)); REG_3_reg_q_12 : dff port map ( Q=>reg_3_q_c_12, QB=>OPEN, D=>nx1226, CLK =>CLK); ix1227 : xnor2 port map ( Y=>nx1226, A0=>nx2047, A1=>nx1224); ix2048 : aoi22 port map ( Y=>nx2047, A0=>nx1441, A1=>PRI_IN_1(11), B0=> nx1122, B1=>nx1124); ix1225 : xnor2 port map ( Y=>nx1224, A0=>PRI_IN_1(12), A1=>nx2041); REG_8_reg_q_13 : dff port map ( Q=>PRI_OUT_4(13), QB=>OPEN, D=>nx1344, CLK=>CLK); ix1345 : xor2 port map ( Y=>nx1344, A0=>nx3466, A1=>nx2059); ix1315 : ao21 port map ( Y=>nx1446, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_13, B0=>nx1290); REG_6_reg_q_13 : dff port map ( Q=>reg_6_q_c_13, QB=>OPEN, D=>nx1304, CLK =>CLK); ix1305 : xor2 port map ( Y=>nx1304, A0=>nx1300, A1=>nx1302); ix1301 : mux21 port map ( Y=>nx1300, A0=>PRI_IN_2(12), A1=>nx2018, S0=> nx1202); ix1303 : xnor2 port map ( Y=>nx1302, A0=>PRI_IN_2(13), A1=>nx3482); ix1291 : nor02 port map ( Y=>nx1290, A0=>C_MUX2_4_SEL, A1=>nx2069); ix2070 : mux21 port map ( Y=>nx2069, A0=>reg_5_q_c_13, A1=>PRI_IN_1(13), S0=>C_MUX2_5_SEL); REG_5_reg_q_13 : dff port map ( Q=>reg_5_q_c_13, QB=>OPEN, D=>nx1272, CLK =>CLK); ix1273 : xnor2 port map ( Y=>nx1272, A0=>nx1268, A1=>nx2079); ix1269 : oai22 port map ( Y=>nx1268, A0=>nx2031, A1=>nx2037, B0=>nx2075, B1=>nx2077); ix2076 : inv02 port map ( Y=>nx2075, A=>PRI_IN_1(12)); ix2078 : inv02 port map ( Y=>nx2077, A=>PRI_IN_2(12)); ix2080 : xnor2 port map ( Y=>nx2079, A0=>PRI_IN_2(13), A1=>PRI_IN_1(13)); ix2083 : mux21 port map ( Y=>nx2082, A0=>reg_3_q_c_13, A1=>PRI_IN_3(13), S0=>C_MUX2_3_SEL); REG_3_reg_q_13 : dff port map ( Q=>reg_3_q_c_13, QB=>OPEN, D=>nx1326, CLK =>CLK); ix1327 : xor2 port map ( Y=>nx1326, A0=>nx1322, A1=>nx1324); ix1323 : oai22 port map ( Y=>nx1322, A0=>nx2047, A1=>nx2087, B0=>nx2041, B1=>nx2075); ix1325 : xnor2 port map ( Y=>nx1324, A0=>PRI_IN_1(13), A1=>nx3480); REG_8_reg_q_14 : dff port map ( Q=>PRI_OUT_4(14), QB=>OPEN, D=>nx1444, CLK=>CLK); ix1445 : xnor2 port map ( Y=>nx1444, A0=>nx1360, A1=>nx3465); ix1415 : ao21 port map ( Y=>nx1448, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_14, B0=>nx1390); REG_6_reg_q_14 : dff port map ( Q=>reg_6_q_c_14, QB=>OPEN, D=>nx1404, CLK =>CLK); ix1405 : xnor2 port map ( Y=>nx1404, A0=>nx2113, A1=>nx1402); ix2114 : mux21 port map ( Y=>nx2113, A0=>nx2115, A1=>nx1300, S0=>nx1302); ix2116 : inv02 port map ( Y=>nx2115, A=>PRI_IN_2(13)); ix1403 : xnor2 port map ( Y=>nx1402, A0=>PRI_IN_2(14), A1=>nx3485); ix1391 : nor02 port map ( Y=>nx1390, A0=>C_MUX2_4_SEL, A1=>nx2121); ix2122 : mux21 port map ( Y=>nx2121, A0=>reg_5_q_c_14, A1=>PRI_IN_1(14), S0=>C_MUX2_5_SEL); REG_5_reg_q_14 : dff port map ( Q=>reg_5_q_c_14, QB=>OPEN, D=>nx1372, CLK =>CLK); ix1373 : xor2 port map ( Y=>nx1372, A0=>nx2126, A1=>nx2131); ix2127 : aoi22 port map ( Y=>nx2126, A0=>PRI_IN_1(13), A1=>PRI_IN_2(13), B0=>nx1268, B1=>nx1270); ix2132 : xnor2 port map ( Y=>nx2131, A0=>PRI_IN_2(14), A1=>PRI_IN_1(14)); REG_3_reg_q_14 : dff port map ( Q=>reg_3_q_c_14, QB=>OPEN, D=>nx1426, CLK =>CLK); ix1427 : xnor2 port map ( Y=>nx1426, A0=>nx2138, A1=>nx1424); ix2139 : aoi22 port map ( Y=>nx2138, A0=>nx1447, A1=>PRI_IN_1(13), B0=> nx1322, B1=>nx1324); ix1425 : xnor2 port map ( Y=>nx1424, A0=>PRI_IN_1(14), A1=>nx2134); REG_8_reg_q_15 : dff port map ( Q=>PRI_OUT_4(15), QB=>OPEN, D=>nx1544, CLK=>CLK); ix1545 : xnor2 port map ( Y=>nx1544, A0=>nx2147, A1=>nx1542); ix1543 : xor2 port map ( Y=>nx1542, A0=>nx1450, A1=>nx2176); ix1515 : ao21 port map ( Y=>nx1450, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_15, B0=>nx1490); REG_6_reg_q_15 : dff port map ( Q=>reg_6_q_c_15, QB=>OPEN, D=>nx1504, CLK =>CLK); ix1505 : xnor2 port map ( Y=>nx1504, A0=>nx1500, A1=>nx2154); ix1501 : mux21 port map ( Y=>nx1500, A0=>PRI_IN_2(14), A1=>nx2113, S0=> nx1402); ix1491 : nor02 port map ( Y=>nx1490, A0=>C_MUX2_4_SEL, A1=>nx2161); ix2162 : mux21 port map ( Y=>nx2161, A0=>reg_5_q_c_15, A1=>PRI_IN_1(15), S0=>C_MUX2_5_SEL); REG_5_reg_q_15 : dff port map ( Q=>reg_5_q_c_15, QB=>OPEN, D=>nx1472, CLK =>CLK); ix1473 : xnor2 port map ( Y=>nx1472, A0=>nx1468, A1=>nx2171); ix1469 : oai22 port map ( Y=>nx1468, A0=>nx2126, A1=>nx2131, B0=>nx2167, B1=>nx2169); ix2168 : inv02 port map ( Y=>nx2167, A=>PRI_IN_1(14)); ix2170 : inv02 port map ( Y=>nx2169, A=>PRI_IN_2(14)); ix2172 : xnor2 port map ( Y=>nx2171, A0=>PRI_IN_2(15), A1=>PRI_IN_1(15)); ix2178 : mux21 port map ( Y=>nx2176, A0=>reg_3_q_c_15, A1=>PRI_IN_3(15), S0=>C_MUX2_3_SEL); REG_3_reg_q_15 : dff port map ( Q=>reg_3_q_c_15, QB=>OPEN, D=>nx1526, CLK =>CLK); ix1527 : xnor2 port map ( Y=>nx1526, A0=>nx1522, A1=>nx2191); ix1523 : oai22 port map ( Y=>nx1522, A0=>nx2138, A1=>nx2185, B0=>nx2134, B1=>nx2167); ix2192 : xor2 port map ( Y=>nx2191, A0=>PRI_IN_1(15), A1=>nx2176); REG_7_reg_q_0 : dff port map ( Q=>PRI_OUT_3(0), QB=>OPEN, D=>nx1562, CLK =>CLK); ix1563 : ao21 port map ( Y=>nx1562, A0=>PRI_IN_4(0), A1=>nx2197, B0=> nx2199); ix2198 : inv02 port map ( Y=>nx2197, A=>PRI_IN_0(0)); ix2200 : nor02 port map ( Y=>nx2199, A0=>nx2197, A1=>PRI_IN_4(0)); REG_7_reg_q_1 : dff port map ( Q=>PRI_OUT_3(1), QB=>OPEN, D=>nx1572, CLK =>CLK); ix1573 : xnor2 port map ( Y=>nx1572, A0=>nx2199, A1=>nx1570); ix1571 : xnor2 port map ( Y=>nx1570, A0=>PRI_IN_4(1), A1=>PRI_IN_0(1)); REG_7_reg_q_2 : dff port map ( Q=>PRI_OUT_3(2), QB=>OPEN, D=>nx1592, CLK =>CLK); ix1593 : xnor2 port map ( Y=>nx1592, A0=>nx2209, A1=>nx1590); ix2210 : aoi22 port map ( Y=>nx2209, A0=>nx2211, A1=>PRI_IN_4(1), B0=> nx1554, B1=>nx1570); ix2212 : inv02 port map ( Y=>nx2211, A=>PRI_IN_0(1)); ix1591 : xnor2 port map ( Y=>nx1590, A0=>PRI_IN_4(2), A1=>PRI_IN_0(2)); REG_7_reg_q_3 : dff port map ( Q=>PRI_OUT_3(3), QB=>OPEN, D=>nx1612, CLK =>CLK); ix1613 : xor2 port map ( Y=>nx1612, A0=>nx1608, A1=>nx1610); ix1609 : mux21 port map ( Y=>nx1608, A0=>PRI_IN_0(2), A1=>nx2209, S0=> nx1590); ix1611 : xnor2 port map ( Y=>nx1610, A0=>PRI_IN_4(3), A1=>PRI_IN_0(3)); REG_7_reg_q_4 : dff port map ( Q=>PRI_OUT_3(4), QB=>OPEN, D=>nx1632, CLK =>CLK); ix1633 : xnor2 port map ( Y=>nx1632, A0=>nx2225, A1=>nx1630); ix2226 : aoi22 port map ( Y=>nx2225, A0=>nx2227, A1=>PRI_IN_4(3), B0=> nx1608, B1=>nx1610); ix2228 : inv02 port map ( Y=>nx2227, A=>PRI_IN_0(3)); ix1631 : xnor2 port map ( Y=>nx1630, A0=>PRI_IN_4(4), A1=>PRI_IN_0(4)); REG_7_reg_q_5 : dff port map ( Q=>PRI_OUT_3(5), QB=>OPEN, D=>nx1652, CLK =>CLK); ix1653 : xor2 port map ( Y=>nx1652, A0=>nx1648, A1=>nx1650); ix1649 : mux21 port map ( Y=>nx1648, A0=>PRI_IN_0(4), A1=>nx2225, S0=> nx1630); ix1651 : xnor2 port map ( Y=>nx1650, A0=>PRI_IN_4(5), A1=>PRI_IN_0(5)); REG_7_reg_q_6 : dff port map ( Q=>PRI_OUT_3(6), QB=>OPEN, D=>nx1672, CLK =>CLK); ix1673 : xnor2 port map ( Y=>nx1672, A0=>nx2243, A1=>nx1670); ix2244 : aoi22 port map ( Y=>nx2243, A0=>nx2245, A1=>PRI_IN_4(5), B0=> nx1648, B1=>nx1650); ix2246 : inv02 port map ( Y=>nx2245, A=>PRI_IN_0(5)); ix1671 : xnor2 port map ( Y=>nx1670, A0=>PRI_IN_4(6), A1=>PRI_IN_0(6)); REG_7_reg_q_7 : dff port map ( Q=>PRI_OUT_3(7), QB=>OPEN, D=>nx1692, CLK =>CLK); ix1693 : xor2 port map ( Y=>nx1692, A0=>nx1688, A1=>nx1690); ix1689 : mux21 port map ( Y=>nx1688, A0=>PRI_IN_0(6), A1=>nx2243, S0=> nx1670); ix1691 : xnor2 port map ( Y=>nx1690, A0=>PRI_IN_4(7), A1=>PRI_IN_0(7)); REG_7_reg_q_8 : dff port map ( Q=>PRI_OUT_3(8), QB=>OPEN, D=>nx1712, CLK =>CLK); ix1713 : xnor2 port map ( Y=>nx1712, A0=>nx2260, A1=>nx1710); ix2261 : aoi22 port map ( Y=>nx2260, A0=>nx2263, A1=>PRI_IN_4(7), B0=> nx1688, B1=>nx1690); ix2264 : inv02 port map ( Y=>nx2263, A=>PRI_IN_0(7)); ix1711 : xnor2 port map ( Y=>nx1710, A0=>PRI_IN_4(8), A1=>PRI_IN_0(8)); REG_7_reg_q_9 : dff port map ( Q=>PRI_OUT_3(9), QB=>OPEN, D=>nx1732, CLK =>CLK); ix1733 : xor2 port map ( Y=>nx1732, A0=>nx1728, A1=>nx1730); ix1729 : mux21 port map ( Y=>nx1728, A0=>PRI_IN_0(8), A1=>nx2260, S0=> nx1710); ix1731 : xnor2 port map ( Y=>nx1730, A0=>PRI_IN_4(9), A1=>PRI_IN_0(9)); REG_7_reg_q_10 : dff port map ( Q=>PRI_OUT_3(10), QB=>OPEN, D=>nx1752, CLK=>CLK); ix1753 : xnor2 port map ( Y=>nx1752, A0=>nx2277, A1=>nx1750); ix2278 : aoi22 port map ( Y=>nx2277, A0=>nx2279, A1=>PRI_IN_4(9), B0=> nx1728, B1=>nx1730); ix2280 : inv02 port map ( Y=>nx2279, A=>PRI_IN_0(9)); ix1751 : xnor2 port map ( Y=>nx1750, A0=>PRI_IN_4(10), A1=>PRI_IN_0(10)); REG_7_reg_q_11 : dff port map ( Q=>PRI_OUT_3(11), QB=>OPEN, D=>nx1772, CLK=>CLK); ix1773 : xor2 port map ( Y=>nx1772, A0=>nx1768, A1=>nx1770); ix1769 : mux21 port map ( Y=>nx1768, A0=>PRI_IN_0(10), A1=>nx2277, S0=> nx1750); ix1771 : xnor2 port map ( Y=>nx1770, A0=>PRI_IN_4(11), A1=>PRI_IN_0(11)); REG_7_reg_q_12 : dff port map ( Q=>PRI_OUT_3(12), QB=>OPEN, D=>nx1792, CLK=>CLK); ix1793 : xnor2 port map ( Y=>nx1792, A0=>nx2291, A1=>nx1790); ix2292 : aoi22 port map ( Y=>nx2291, A0=>nx2293, A1=>PRI_IN_4(11), B0=> nx1768, B1=>nx1770); ix2294 : inv02 port map ( Y=>nx2293, A=>PRI_IN_0(11)); ix1791 : xnor2 port map ( Y=>nx1790, A0=>PRI_IN_4(12), A1=>PRI_IN_0(12)); REG_7_reg_q_13 : dff port map ( Q=>PRI_OUT_3(13), QB=>OPEN, D=>nx1812, CLK=>CLK); ix1813 : xor2 port map ( Y=>nx1812, A0=>nx1808, A1=>nx1810); ix1809 : mux21 port map ( Y=>nx1808, A0=>PRI_IN_0(12), A1=>nx2291, S0=> nx1790); ix1811 : xnor2 port map ( Y=>nx1810, A0=>PRI_IN_4(13), A1=>PRI_IN_0(13)); REG_7_reg_q_14 : dff port map ( Q=>PRI_OUT_3(14), QB=>OPEN, D=>nx1832, CLK=>CLK); ix1833 : xnor2 port map ( Y=>nx1832, A0=>nx2309, A1=>nx1830); ix2310 : aoi22 port map ( Y=>nx2309, A0=>nx2311, A1=>PRI_IN_4(13), B0=> nx1808, B1=>nx1810); ix2312 : inv02 port map ( Y=>nx2311, A=>PRI_IN_0(13)); ix1831 : xnor2 port map ( Y=>nx1830, A0=>PRI_IN_4(14), A1=>PRI_IN_0(14)); REG_7_reg_q_15 : dff port map ( Q=>PRI_OUT_3(15), QB=>OPEN, D=>nx1852, CLK=>CLK); ix1853 : xnor2 port map ( Y=>nx1852, A0=>nx1848, A1=>nx2321); ix1849 : mux21 port map ( Y=>nx1848, A0=>PRI_IN_0(14), A1=>nx2309, S0=> nx1830); ix1899 : ao21 port map ( Y=>PRI_OUT_2_0_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_0, B0=>nx1862); REG_4_reg_q_0 : dff port map ( Q=>reg_4_q_c_0, QB=>OPEN, D=>nx1888, CLK=> CLK); ix1889 : xor2 port map ( Y=>nx1888, A0=>PRI_IN_0(0), A1=>reg_9_q_c_0); REG_9_reg_q_0 : dff port map ( Q=>reg_9_q_c_0, QB=>OPEN, D=>nx1874, CLK=> CLK); ix1875 : ao21 port map ( Y=>nx1874, A0=>PRI_IN_0(0), A1=>nx1487, B0=> nx2333); ix2334 : nor02 port map ( Y=>nx2333, A0=>nx1487, A1=>PRI_IN_0(0)); ix1863 : nor02 port map ( Y=>nx1862, A0=>C_MUX2_1_SEL, A1=>nx1471); REG_4_reg_q_1 : dff port map ( Q=>reg_4_q_c_1, QB=>OPEN, D=>nx1934, CLK=> CLK); ix1935 : xor2 port map ( Y=>nx1934, A0=>nx2343, A1=>nx2345); ix2344 : nand02 port map ( Y=>nx2343, A0=>PRI_IN_0(0), A1=>reg_9_q_c_0); ix2346 : xnor2 port map ( Y=>nx2345, A0=>PRI_IN_0(1), A1=>reg_9_q_c_1); REG_9_reg_q_1 : dff port map ( Q=>reg_9_q_c_1, QB=>OPEN, D=>nx1924, CLK=> CLK); ix1925 : xor2 port map ( Y=>nx1924, A0=>nx2333, A1=>nx2349); ix2350 : xnor2 port map ( Y=>nx2349, A0=>PRI_IN_0(1), A1=>nx1513); ix2011 : ao21 port map ( Y=>PRI_OUT_2_2_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_2, B0=>nx1968); REG_4_reg_q_2 : dff port map ( Q=>reg_4_q_c_2, QB=>OPEN, D=>nx2000, CLK=> CLK); ix2001 : xor2 port map ( Y=>nx2000, A0=>nx2365, A1=>nx2369); ix2366 : aoi32 port map ( Y=>nx2365, A0=>PRI_IN_0(0), A1=>reg_9_q_c_0, A2 =>nx1932, B0=>reg_9_q_c_1, B1=>PRI_IN_0(1)); REG_9_reg_q_2 : dff port map ( Q=>OPEN, QB=>nx2379, D=>nx1990, CLK=>CLK); ix1991 : xnor2 port map ( Y=>nx1990, A0=>nx1986, A1=>nx2377); ix1987 : oai22 port map ( Y=>nx1986, A0=>nx104, A1=>nx2211, B0=>nx2333, B1=>nx2349); ix2378 : xnor2 port map ( Y=>nx2377, A0=>PRI_IN_0(2), A1=>nx1555); ix1969 : nor02 port map ( Y=>nx1968, A0=>C_MUX2_1_SEL, A1=>nx2383); REG_4_reg_q_3 : dff port map ( Q=>reg_4_q_c_3, QB=>OPEN, D=>nx2066, CLK=> CLK); ix2067 : xnor2 port map ( Y=>nx2066, A0=>nx2042, A1=>nx2395); ix2043 : oai22 port map ( Y=>nx2042, A0=>nx2365, A1=>nx2369, B0=>nx2379, B1=>nx2393); ix2394 : inv02 port map ( Y=>nx2393, A=>PRI_IN_0(2)); ix2396 : xnor2 port map ( Y=>nx2395, A0=>PRI_IN_0(3), A1=>reg_9_q_c_3); REG_9_reg_q_3 : dff port map ( Q=>reg_9_q_c_3, QB=>OPEN, D=>nx2056, CLK=> CLK); ix2057 : xor2 port map ( Y=>nx2056, A0=>nx2400, A1=>nx2403); ix2401 : aoi22 port map ( Y=>nx2400, A0=>nx1555, A1=>PRI_IN_0(2), B0=> nx1986, B1=>nx1988); ix2404 : xnor2 port map ( Y=>nx2403, A0=>PRI_IN_0(3), A1=>nx1597); ix2143 : ao21 port map ( Y=>PRI_OUT_2_4_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_4, B0=>nx2100); REG_4_reg_q_4 : dff port map ( Q=>reg_4_q_c_4, QB=>OPEN, D=>nx2132, CLK=> CLK); ix2133 : xor2 port map ( Y=>nx2132, A0=>nx2417, A1=>nx2421); ix2418 : aoi22 port map ( Y=>nx2417, A0=>reg_9_q_c_3, A1=>PRI_IN_0(3), B0 =>nx2042, B1=>nx2064); REG_9_reg_q_4 : dff port map ( Q=>OPEN, QB=>nx2431, D=>nx2122, CLK=>CLK); ix2123 : xnor2 port map ( Y=>nx2122, A0=>nx2118, A1=>nx2429); ix2119 : oai22 port map ( Y=>nx2118, A0=>nx2400, A1=>nx2403, B0=>nx286, B1=>nx2227); ix2430 : xnor2 port map ( Y=>nx2429, A0=>PRI_IN_0(4), A1=>nx1649); ix2101 : nor02 port map ( Y=>nx2100, A0=>C_MUX2_1_SEL, A1=>nx2435); REG_4_reg_q_5 : dff port map ( Q=>reg_4_q_c_5, QB=>OPEN, D=>nx2198, CLK=> CLK); ix2199 : xnor2 port map ( Y=>nx2198, A0=>nx2174, A1=>nx2451); ix2175 : oai22 port map ( Y=>nx2174, A0=>nx2417, A1=>nx2421, B0=>nx2431, B1=>nx2449); ix2450 : inv02 port map ( Y=>nx2449, A=>PRI_IN_0(4)); ix2452 : xnor2 port map ( Y=>nx2451, A0=>PRI_IN_0(5), A1=>reg_9_q_c_5); REG_9_reg_q_5 : dff port map ( Q=>reg_9_q_c_5, QB=>OPEN, D=>nx2188, CLK=> CLK); ix2189 : xor2 port map ( Y=>nx2188, A0=>nx2456, A1=>nx2459); ix2457 : aoi22 port map ( Y=>nx2456, A0=>nx1649, A1=>PRI_IN_0(4), B0=> nx2118, B1=>nx2120); ix2460 : xnor2 port map ( Y=>nx2459, A0=>PRI_IN_0(5), A1=>nx1695); ix2275 : ao21 port map ( Y=>PRI_OUT_2_6_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_6, B0=>nx2232); REG_4_reg_q_6 : dff port map ( Q=>reg_4_q_c_6, QB=>OPEN, D=>nx2264, CLK=> CLK); ix2265 : xor2 port map ( Y=>nx2264, A0=>nx2473, A1=>nx2477); ix2474 : aoi22 port map ( Y=>nx2473, A0=>reg_9_q_c_5, A1=>PRI_IN_0(5), B0 =>nx2174, B1=>nx2196); REG_9_reg_q_6 : dff port map ( Q=>OPEN, QB=>nx2484, D=>nx2254, CLK=>CLK); ix2255 : xnor2 port map ( Y=>nx2254, A0=>nx2250, A1=>nx2482); ix2251 : oai22 port map ( Y=>nx2250, A0=>nx2456, A1=>nx2459, B0=>nx486, B1=>nx2245); ix2483 : xnor2 port map ( Y=>nx2482, A0=>PRI_IN_0(6), A1=>nx1747); ix2233 : nor02 port map ( Y=>nx2232, A0=>C_MUX2_1_SEL, A1=>nx2487); REG_4_reg_q_7 : dff port map ( Q=>reg_4_q_c_7, QB=>OPEN, D=>nx2330, CLK=> CLK); ix2331 : xnor2 port map ( Y=>nx2330, A0=>nx2306, A1=>nx2501); ix2307 : oai22 port map ( Y=>nx2306, A0=>nx2473, A1=>nx2477, B0=>nx2484, B1=>nx2499); ix2500 : inv02 port map ( Y=>nx2499, A=>PRI_IN_0(6)); ix2502 : xnor2 port map ( Y=>nx2501, A0=>PRI_IN_0(7), A1=>reg_9_q_c_7); REG_9_reg_q_7 : dff port map ( Q=>reg_9_q_c_7, QB=>OPEN, D=>nx2320, CLK=> CLK); ix2321 : xor2 port map ( Y=>nx2320, A0=>nx2507, A1=>nx2511); ix2508 : aoi22 port map ( Y=>nx2507, A0=>nx1747, A1=>PRI_IN_0(6), B0=> nx2250, B1=>nx2252); ix2512 : xnor2 port map ( Y=>nx2511, A0=>PRI_IN_0(7), A1=>nx1791); ix2407 : ao21 port map ( Y=>PRI_OUT_2_8_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_8, B0=>nx2364); REG_4_reg_q_8 : dff port map ( Q=>reg_4_q_c_8, QB=>OPEN, D=>nx2396, CLK=> CLK); ix2397 : xor2 port map ( Y=>nx2396, A0=>nx2525, A1=>nx2529); ix2526 : aoi22 port map ( Y=>nx2525, A0=>reg_9_q_c_7, A1=>PRI_IN_0(7), B0 =>nx2306, B1=>nx2328); REG_9_reg_q_8 : dff port map ( Q=>OPEN, QB=>nx2537, D=>nx2386, CLK=>CLK); ix2387 : xnor2 port map ( Y=>nx2386, A0=>nx2382, A1=>nx2534); ix2383 : oai22 port map ( Y=>nx2382, A0=>nx2507, A1=>nx2511, B0=>nx686, B1=>nx2263); ix2535 : xnor2 port map ( Y=>nx2534, A0=>PRI_IN_0(8), A1=>nx1843); ix2365 : nor02 port map ( Y=>nx2364, A0=>C_MUX2_1_SEL, A1=>nx2541); REG_4_reg_q_9 : dff port map ( Q=>reg_4_q_c_9, QB=>OPEN, D=>nx2462, CLK=> CLK); ix2463 : xnor2 port map ( Y=>nx2462, A0=>nx2438, A1=>nx2553); ix2439 : oai22 port map ( Y=>nx2438, A0=>nx2525, A1=>nx2529, B0=>nx2537, B1=>nx2550); ix2552 : inv02 port map ( Y=>nx2550, A=>PRI_IN_0(8)); ix2554 : xnor2 port map ( Y=>nx2553, A0=>PRI_IN_0(9), A1=>reg_9_q_c_9); REG_9_reg_q_9 : dff port map ( Q=>reg_9_q_c_9, QB=>OPEN, D=>nx2452, CLK=> CLK); ix2453 : xor2 port map ( Y=>nx2452, A0=>nx2559, A1=>nx2563); ix2560 : aoi22 port map ( Y=>nx2559, A0=>nx1843, A1=>PRI_IN_0(8), B0=> nx2382, B1=>nx2384); ix2564 : xnor2 port map ( Y=>nx2563, A0=>PRI_IN_0(9), A1=>nx1883); ix2539 : ao21 port map ( Y=>PRI_OUT_2_10_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_10, B0=>nx2496); REG_4_reg_q_10 : dff port map ( Q=>reg_4_q_c_10, QB=>OPEN, D=>nx2528, CLK =>CLK); ix2529 : xor2 port map ( Y=>nx2528, A0=>nx2581, A1=>nx2585); ix2582 : aoi22 port map ( Y=>nx2581, A0=>reg_9_q_c_9, A1=>PRI_IN_0(9), B0 =>nx2438, B1=>nx2460); REG_9_reg_q_10 : dff port map ( Q=>OPEN, QB=>nx2593, D=>nx2518, CLK=>CLK ); ix2519 : xnor2 port map ( Y=>nx2518, A0=>nx2514, A1=>nx2590); ix2515 : oai22 port map ( Y=>nx2514, A0=>nx2559, A1=>nx2563, B0=>nx886, B1=>nx2279); ix2591 : xnor2 port map ( Y=>nx2590, A0=>PRI_IN_0(10), A1=>nx1935); ix2497 : nor02 port map ( Y=>nx2496, A0=>C_MUX2_1_SEL, A1=>nx2597); REG_4_reg_q_11 : dff port map ( Q=>reg_4_q_c_11, QB=>OPEN, D=>nx2594, CLK =>CLK); ix2595 : xnor2 port map ( Y=>nx2594, A0=>nx2570, A1=>nx2609); ix2571 : oai22 port map ( Y=>nx2570, A0=>nx2581, A1=>nx2585, B0=>nx2593, B1=>nx2607); ix2608 : inv02 port map ( Y=>nx2607, A=>PRI_IN_0(10)); ix2610 : xnor2 port map ( Y=>nx2609, A0=>PRI_IN_0(11), A1=>reg_9_q_c_11); REG_9_reg_q_11 : dff port map ( Q=>reg_9_q_c_11, QB=>OPEN, D=>nx2584, CLK =>CLK); ix2585 : xor2 port map ( Y=>nx2584, A0=>nx2613, A1=>nx2616); ix2614 : aoi22 port map ( Y=>nx2613, A0=>nx1935, A1=>PRI_IN_0(10), B0=> nx2514, B1=>nx2516); ix2618 : xnor2 port map ( Y=>nx2616, A0=>PRI_IN_0(11), A1=>nx1975); ix2671 : ao21 port map ( Y=>PRI_OUT_2_12_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_12, B0=>nx2628); REG_4_reg_q_12 : dff port map ( Q=>reg_4_q_c_12, QB=>OPEN, D=>nx2660, CLK =>CLK); ix2661 : xor2 port map ( Y=>nx2660, A0=>nx2633, A1=>nx2637); ix2634 : aoi22 port map ( Y=>nx2633, A0=>reg_9_q_c_11, A1=>PRI_IN_0(11), B0=>nx2570, B1=>nx2592); REG_9_reg_q_12 : dff port map ( Q=>OPEN, QB=>nx2647, D=>nx2650, CLK=>CLK ); ix2651 : xnor2 port map ( Y=>nx2650, A0=>nx2646, A1=>nx2645); ix2647 : oai22 port map ( Y=>nx2646, A0=>nx2613, A1=>nx2616, B0=>nx1086, B1=>nx2293); ix2646 : xnor2 port map ( Y=>nx2645, A0=>PRI_IN_0(12), A1=>nx2025); ix2629 : nor02 port map ( Y=>nx2628, A0=>C_MUX2_1_SEL, A1=>nx2651); REG_4_reg_q_13 : dff port map ( Q=>reg_4_q_c_13, QB=>OPEN, D=>nx2726, CLK =>CLK); ix2727 : xnor2 port map ( Y=>nx2726, A0=>nx2702, A1=>nx2661); ix2703 : oai22 port map ( Y=>nx2702, A0=>nx2633, A1=>nx2637, B0=>nx2647, B1=>nx2659); ix2660 : inv02 port map ( Y=>nx2659, A=>PRI_IN_0(12)); ix2662 : xnor2 port map ( Y=>nx2661, A0=>PRI_IN_0(13), A1=>reg_9_q_c_13); REG_9_reg_q_13 : dff port map ( Q=>reg_9_q_c_13, QB=>OPEN, D=>nx2716, CLK =>CLK); ix2717 : xor2 port map ( Y=>nx2716, A0=>nx2665, A1=>nx2669); ix2666 : aoi22 port map ( Y=>nx2665, A0=>nx2025, A1=>PRI_IN_0(12), B0=> nx2646, B1=>nx2648); ix2670 : xnor2 port map ( Y=>nx2669, A0=>PRI_IN_0(13), A1=>nx2069); ix2803 : ao21 port map ( Y=>PRI_OUT_2_14_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_14, B0=>nx2760); REG_4_reg_q_14 : dff port map ( Q=>reg_4_q_c_14, QB=>OPEN, D=>nx2792, CLK =>CLK); ix2793 : xor2 port map ( Y=>nx2792, A0=>nx2682, A1=>nx2687); ix2684 : aoi22 port map ( Y=>nx2682, A0=>reg_9_q_c_13, A1=>PRI_IN_0(13), B0=>nx2702, B1=>nx2724); REG_9_reg_q_14 : dff port map ( Q=>OPEN, QB=>nx2697, D=>nx2782, CLK=>CLK ); ix2783 : xnor2 port map ( Y=>nx2782, A0=>nx2778, A1=>nx2695); ix2779 : oai22 port map ( Y=>nx2778, A0=>nx2665, A1=>nx2669, B0=>nx1286, B1=>nx2311); ix2696 : xnor2 port map ( Y=>nx2695, A0=>PRI_IN_0(14), A1=>nx2121); ix2761 : nor02 port map ( Y=>nx2760, A0=>C_MUX2_1_SEL, A1=>nx2701); ix2869 : ao21 port map ( Y=>PRI_OUT_2_15_EXMPLR, A0=>C_MUX2_1_SEL, A1=> reg_4_q_c_15, B0=>nx2826); REG_4_reg_q_15 : dff port map ( Q=>reg_4_q_c_15, QB=>OPEN, D=>nx2858, CLK =>CLK); ix2859 : xnor2 port map ( Y=>nx2858, A0=>nx2834, A1=>nx2717); ix2835 : oai22 port map ( Y=>nx2834, A0=>nx2682, A1=>nx2687, B0=>nx2697, B1=>nx2715); ix2716 : inv02 port map ( Y=>nx2715, A=>PRI_IN_0(14)); ix2718 : xnor2 port map ( Y=>nx2717, A0=>PRI_IN_0(15), A1=>reg_9_q_c_15); REG_9_reg_q_15 : dff port map ( Q=>reg_9_q_c_15, QB=>OPEN, D=>nx2848, CLK =>CLK); ix2849 : xnor2 port map ( Y=>nx2848, A0=>nx2721, A1=>nx2846); ix2722 : aoi22 port map ( Y=>nx2721, A0=>nx2121, A1=>PRI_IN_0(14), B0=> nx2778, B1=>nx2780); ix2847 : xor2 port map ( Y=>nx2846, A0=>PRI_IN_0(15), A1=>nx2161); ix2827 : nor02 port map ( Y=>nx2826, A0=>C_MUX2_1_SEL, A1=>nx2157); ix2915 : ao21 port map ( Y=>PRI_OUT_1(0), A0=>nx3188, A1=>reg_2_q_c_0, B0 =>nx2912); ix2731 : inv02 port map ( Y=>nx2730, A=>C_MUX2_2_SEL); REG_2_reg_q_0 : dff port map ( Q=>reg_2_q_c_0, QB=>OPEN, D=>nx2900, CLK=> CLK); REG_10_reg_q_0 : dff port map ( Q=>reg_10_q_c_0, QB=>OPEN, D=>nx2886, CLK =>CLK); ix2913 : nor02 port map ( Y=>nx2912, A0=>nx3188, A1=>nx1489); ix2943 : ao21 port map ( Y=>PRI_OUT_1(1), A0=>nx3188, A1=>reg_2_q_c_1, B0 =>nx2940); REG_2_reg_q_1 : dff port map ( Q=>reg_2_q_c_1, QB=>OPEN, D=>nx2928, CLK=> CLK); ix2929 : xor2 port map ( Y=>nx2928, A0=>nx2745, A1=>nx2747); ix2746 : nand02 port map ( Y=>nx2745, A0=>reg_10_q_c_0, A1=>nx1409); ix2748 : xnor2 port map ( Y=>nx2747, A0=>reg_10_q_c_1, A1=> \[8955__XX0_XREP4\); REG_10_reg_q_1 : dff port map ( Q=>reg_10_q_c_1, QB=>OPEN, D=>nx2918, CLK =>CLK); ix2919 : xor2 port map ( Y=>nx2918, A0=>nx2753, A1=>nx2755); ix2754 : nand02 port map ( Y=>nx2753, A0=>PRI_IN_0(0), A1=>PRI_IN_1(0)); ix2756 : xnor2 port map ( Y=>nx2755, A0=>PRI_IN_0(1), A1=>PRI_IN_1(1)); ix2941 : nor02 port map ( Y=>nx2940, A0=>nx3188, A1=>nx1525); ix2987 : ao21 port map ( Y=>PRI_OUT_1(2), A0=>nx3188, A1=>reg_2_q_c_2, B0 =>nx2984); REG_2_reg_q_2 : dff port map ( Q=>reg_2_q_c_2, QB=>OPEN, D=>nx2972, CLK=> CLK); ix2973 : xor2 port map ( Y=>nx2972, A0=>nx2765, A1=>nx2769); ix2766 : aoi32 port map ( Y=>nx2765, A0=>reg_10_q_c_0, A1=>nx1409, A2=> nx2926, B0=>nx1411, B1=>reg_10_q_c_1); ix2770 : xnor2 port map ( Y=>nx2769, A0=>reg_10_q_c_2, A1=>nx1414); REG_10_reg_q_2 : dff port map ( Q=>reg_10_q_c_2, QB=>OPEN, D=>nx2962, CLK =>CLK); ix2963 : xor2 port map ( Y=>nx2962, A0=>nx2775, A1=>nx2779); ix2776 : aoi32 port map ( Y=>nx2775, A0=>PRI_IN_0(0), A1=>PRI_IN_1(0), A2 =>nx2916, B0=>PRI_IN_1(1), B1=>PRI_IN_0(1)); ix2780 : xnor2 port map ( Y=>nx2779, A0=>PRI_IN_0(2), A1=>PRI_IN_1(2)); ix2985 : nor02 port map ( Y=>nx2984, A0=>nx3191, A1=>nx1568); ix3031 : ao21 port map ( Y=>PRI_OUT_1(3), A0=>nx3191, A1=>reg_2_q_c_3, B0 =>nx3028); REG_2_reg_q_3 : dff port map ( Q=>reg_2_q_c_3, QB=>OPEN, D=>nx3016, CLK=> CLK); ix3017 : xnor2 port map ( Y=>nx3016, A0=>nx2994, A1=>nx2789); ix2995 : mux21 port map ( Y=>nx2994, A0=>nx2765, A1=>nx2383, S0=>nx2769); ix2790 : xnor2 port map ( Y=>nx2789, A0=>reg_10_q_c_3, A1=>nx1416); REG_10_reg_q_3 : dff port map ( Q=>reg_10_q_c_3, QB=>OPEN, D=>nx3006, CLK =>CLK); ix3007 : xnor2 port map ( Y=>nx3006, A0=>nx3002, A1=>nx2796); ix3003 : oai22 port map ( Y=>nx3002, A0=>nx2775, A1=>nx2779, B0=>nx1603, B1=>nx2393); ix2797 : xnor2 port map ( Y=>nx2796, A0=>PRI_IN_0(3), A1=>PRI_IN_1(3)); ix3029 : nor02 port map ( Y=>nx3028, A0=>nx3191, A1=>nx1611); ix3075 : ao21 port map ( Y=>PRI_OUT_1(4), A0=>nx3191, A1=>reg_2_q_c_4, B0 =>nx3072); REG_2_reg_q_4 : dff port map ( Q=>reg_2_q_c_4, QB=>OPEN, D=>nx3060, CLK=> CLK); ix3061 : xor2 port map ( Y=>nx3060, A0=>nx2807, A1=>nx2810); ix2808 : aoi22 port map ( Y=>nx2807, A0=>nx1416, A1=>reg_10_q_c_3, B0=> nx2994, B1=>nx3014); ix2811 : xnor2 port map ( Y=>nx2810, A0=>reg_10_q_c_4, A1=>nx3390); REG_10_reg_q_4 : dff port map ( Q=>reg_10_q_c_4, QB=>OPEN, D=>nx3050, CLK =>CLK); ix3051 : xor2 port map ( Y=>nx3050, A0=>nx2814, A1=>nx2819); ix2816 : aoi22 port map ( Y=>nx2814, A0=>PRI_IN_1(3), A1=>PRI_IN_0(3), B0 =>nx3002, B1=>nx3004); ix2820 : xnor2 port map ( Y=>nx2819, A0=>PRI_IN_0(4), A1=>PRI_IN_1(4)); ix3073 : nor02 port map ( Y=>nx3072, A0=>nx3191, A1=>nx1665); ix3119 : ao21 port map ( Y=>PRI_OUT_1(5), A0=>nx3193, A1=>reg_2_q_c_5, B0 =>nx3116); REG_2_reg_q_5 : dff port map ( Q=>reg_2_q_c_5, QB=>OPEN, D=>nx3104, CLK=> CLK); ix3105 : xnor2 port map ( Y=>nx3104, A0=>nx3082, A1=>nx2831); ix3083 : mux21 port map ( Y=>nx3082, A0=>nx2807, A1=>nx2435, S0=>nx2810); ix2832 : xnor2 port map ( Y=>nx2831, A0=>reg_10_q_c_5, A1=>nx3389); REG_10_reg_q_5 : dff port map ( Q=>reg_10_q_c_5, QB=>OPEN, D=>nx3094, CLK =>CLK); ix3095 : xnor2 port map ( Y=>nx3094, A0=>nx3090, A1=>nx2839); ix3091 : oai22 port map ( Y=>nx3090, A0=>nx2814, A1=>nx2819, B0=>nx1700, B1=>nx2449); ix2840 : xnor2 port map ( Y=>nx2839, A0=>PRI_IN_0(5), A1=>PRI_IN_1(5)); ix3117 : nor02 port map ( Y=>nx3116, A0=>nx3193, A1=>nx1709); ix3163 : ao21 port map ( Y=>PRI_OUT_1(6), A0=>nx3193, A1=>reg_2_q_c_6, B0 =>nx3160); REG_2_reg_q_6 : dff port map ( Q=>reg_2_q_c_6, QB=>OPEN, D=>nx3148, CLK=> CLK); ix3149 : xor2 port map ( Y=>nx3148, A0=>nx2851, A1=>nx2854); ix2852 : aoi22 port map ( Y=>nx2851, A0=>nx3389, A1=>reg_10_q_c_5, B0=> nx3082, B1=>nx3102); ix2855 : xnor2 port map ( Y=>nx2854, A0=>reg_10_q_c_6, A1=>nx1427); REG_10_reg_q_6 : dff port map ( Q=>reg_10_q_c_6, QB=>OPEN, D=>nx3138, CLK =>CLK); ix3139 : xor2 port map ( Y=>nx3138, A0=>nx2859, A1=>nx2862); ix2860 : aoi22 port map ( Y=>nx2859, A0=>PRI_IN_1(5), A1=>PRI_IN_0(5), B0 =>nx3090, B1=>nx3092); ix2863 : xnor2 port map ( Y=>nx2862, A0=>PRI_IN_0(6), A1=>PRI_IN_1(6)); ix3161 : nor02 port map ( Y=>nx3160, A0=>nx3193, A1=>nx1761); ix3207 : ao21 port map ( Y=>PRI_OUT_1(7), A0=>nx3193, A1=>reg_2_q_c_7, B0 =>nx3204); REG_2_reg_q_7 : dff port map ( Q=>reg_2_q_c_7, QB=>OPEN, D=>nx3192, CLK=> CLK); ix3193 : xnor2 port map ( Y=>nx3192, A0=>nx3170, A1=>nx2875); ix3171 : mux21 port map ( Y=>nx3170, A0=>nx2851, A1=>nx2487, S0=>nx2854); ix2876 : xnor2 port map ( Y=>nx2875, A0=>reg_10_q_c_7, A1=>nx1429); REG_10_reg_q_7 : dff port map ( Q=>reg_10_q_c_7, QB=>OPEN, D=>nx3182, CLK =>CLK); ix3183 : xnor2 port map ( Y=>nx3182, A0=>nx3178, A1=>nx2881); ix3179 : oai22 port map ( Y=>nx3178, A0=>nx2859, A1=>nx2862, B0=>nx1797, B1=>nx2499); ix2882 : xnor2 port map ( Y=>nx2881, A0=>PRI_IN_0(7), A1=>PRI_IN_1(7)); ix3205 : nor02 port map ( Y=>nx3204, A0=>nx3195, A1=>nx1805); ix3251 : ao21 port map ( Y=>PRI_OUT_1(8), A0=>nx3195, A1=>reg_2_q_c_8, B0 =>nx3248); REG_2_reg_q_8 : dff port map ( Q=>reg_2_q_c_8, QB=>OPEN, D=>nx3236, CLK=> CLK); ix3237 : xor2 port map ( Y=>nx3236, A0=>nx2891, A1=>nx2895); ix2892 : aoi22 port map ( Y=>nx2891, A0=>nx1429, A1=>reg_10_q_c_7, B0=> nx3170, B1=>nx3190); ix2896 : xnor2 port map ( Y=>nx2895, A0=>reg_10_q_c_8, A1=>nx1431); REG_10_reg_q_8 : dff port map ( Q=>reg_10_q_c_8, QB=>OPEN, D=>nx3226, CLK =>CLK); ix3227 : xor2 port map ( Y=>nx3226, A0=>nx2901, A1=>nx2904); ix2902 : aoi22 port map ( Y=>nx2901, A0=>PRI_IN_1(7), A1=>PRI_IN_0(7), B0 =>nx3178, B1=>nx3180); ix2905 : xnor2 port map ( Y=>nx2904, A0=>PRI_IN_0(8), A1=>PRI_IN_1(8)); ix3249 : nor02 port map ( Y=>nx3248, A0=>nx3195, A1=>nx1858); ix3295 : ao21 port map ( Y=>PRI_OUT_1(9), A0=>nx3195, A1=>reg_2_q_c_9, B0 =>nx3292); REG_2_reg_q_9 : dff port map ( Q=>reg_2_q_c_9, QB=>OPEN, D=>nx3280, CLK=> CLK); ix3281 : xnor2 port map ( Y=>nx3280, A0=>nx3258, A1=>nx2917); ix3259 : mux21 port map ( Y=>nx3258, A0=>nx2891, A1=>nx2541, S0=>nx2895); ix2918 : xnor2 port map ( Y=>nx2917, A0=>reg_10_q_c_9, A1=>nx1433); REG_10_reg_q_9 : dff port map ( Q=>reg_10_q_c_9, QB=>OPEN, D=>nx3270, CLK =>CLK); ix3271 : xnor2 port map ( Y=>nx3270, A0=>nx3266, A1=>nx2923); ix3267 : oai22 port map ( Y=>nx3266, A0=>nx2901, A1=>nx2904, B0=>nx1891, B1=>nx2550); ix2924 : xnor2 port map ( Y=>nx2923, A0=>PRI_IN_0(9), A1=>PRI_IN_1(9)); ix3293 : nor02 port map ( Y=>nx3292, A0=>nx3195, A1=>nx1898); ix3339 : ao21 port map ( Y=>PRI_OUT_1(10), A0=>nx3197, A1=>reg_2_q_c_10, B0=>nx3336); REG_2_reg_q_10 : dff port map ( Q=>reg_2_q_c_10, QB=>OPEN, D=>nx3324, CLK =>CLK); ix3325 : xor2 port map ( Y=>nx3324, A0=>nx2933, A1=>nx2936); ix2934 : aoi22 port map ( Y=>nx2933, A0=>nx1433, A1=>reg_10_q_c_9, B0=> nx3258, B1=>nx3278); ix2937 : xnor2 port map ( Y=>nx2936, A0=>reg_10_q_c_10, A1=>nx3476); REG_10_reg_q_10 : dff port map ( Q=>reg_10_q_c_10, QB=>OPEN, D=>nx3314, CLK=>CLK); ix3315 : xor2 port map ( Y=>nx3314, A0=>nx2941, A1=>nx2945); ix2942 : aoi22 port map ( Y=>nx2941, A0=>PRI_IN_1(9), A1=>PRI_IN_0(9), B0 =>nx3266, B1=>nx3268); ix2946 : xnor2 port map ( Y=>nx2945, A0=>PRI_IN_0(10), A1=>PRI_IN_1(10)); ix3337 : nor02 port map ( Y=>nx3336, A0=>nx3197, A1=>nx1949); ix3383 : ao21 port map ( Y=>PRI_OUT_1(11), A0=>nx3197, A1=>reg_2_q_c_11, B0=>nx3380); REG_2_reg_q_11 : dff port map ( Q=>reg_2_q_c_11, QB=>OPEN, D=>nx3368, CLK =>CLK); ix3369 : xnor2 port map ( Y=>nx3368, A0=>nx3346, A1=>nx2959); ix3347 : mux21 port map ( Y=>nx3346, A0=>nx2933, A1=>nx2597, S0=>nx2936); ix2960 : xnor2 port map ( Y=>nx2959, A0=>reg_10_q_c_11, A1=>nx3478); REG_10_reg_q_11 : dff port map ( Q=>reg_10_q_c_11, QB=>OPEN, D=>nx3358, CLK=>CLK); ix3359 : xnor2 port map ( Y=>nx3358, A0=>nx3354, A1=>nx2966); ix3355 : oai22 port map ( Y=>nx3354, A0=>nx2941, A1=>nx2945, B0=>nx1983, B1=>nx2607); ix2967 : xnor2 port map ( Y=>nx2966, A0=>PRI_IN_0(11), A1=>PRI_IN_1(11)); ix3381 : nor02 port map ( Y=>nx3380, A0=>nx3197, A1=>nx1991); ix3427 : ao21 port map ( Y=>PRI_OUT_1(12), A0=>nx3197, A1=>reg_2_q_c_12, B0=>nx3424); REG_2_reg_q_12 : dff port map ( Q=>reg_2_q_c_12, QB=>OPEN, D=>nx3412, CLK =>CLK); ix3413 : xor2 port map ( Y=>nx3412, A0=>nx2976, A1=>nx2979); ix2977 : aoi22 port map ( Y=>nx2976, A0=>nx3478, A1=>reg_10_q_c_11, B0=> nx3346, B1=>nx3366); ix2980 : xnor2 port map ( Y=>nx2979, A0=>reg_10_q_c_12, A1=>nx1443); REG_10_reg_q_12 : dff port map ( Q=>reg_10_q_c_12, QB=>OPEN, D=>nx3402, CLK=>CLK); ix3403 : xor2 port map ( Y=>nx3402, A0=>nx2983, A1=>nx2987); ix2984 : aoi22 port map ( Y=>nx2983, A0=>PRI_IN_1(11), A1=>PRI_IN_0(11), B0=>nx3354, B1=>nx3356); ix2988 : xnor2 port map ( Y=>nx2987, A0=>PRI_IN_0(12), A1=>PRI_IN_1(12)); ix3425 : nor02 port map ( Y=>nx3424, A0=>nx3199, A1=>nx2041); ix3471 : ao21 port map ( Y=>PRI_OUT_1(13), A0=>nx3199, A1=>reg_2_q_c_13, B0=>nx3468); REG_2_reg_q_13 : dff port map ( Q=>reg_2_q_c_13, QB=>OPEN, D=>nx3456, CLK =>CLK); ix3457 : xnor2 port map ( Y=>nx3456, A0=>nx3434, A1=>nx3001); ix3435 : mux21 port map ( Y=>nx3434, A0=>nx2976, A1=>nx2651, S0=>nx2979); ix3002 : xnor2 port map ( Y=>nx3001, A0=>reg_10_q_c_13, A1=>nx3482); REG_10_reg_q_13 : dff port map ( Q=>reg_10_q_c_13, QB=>OPEN, D=>nx3446, CLK=>CLK); ix3447 : xnor2 port map ( Y=>nx3446, A0=>nx3442, A1=>nx3009); ix3443 : oai22 port map ( Y=>nx3442, A0=>nx2983, A1=>nx2987, B0=>nx2075, B1=>nx2659); ix3010 : xnor2 port map ( Y=>nx3009, A0=>PRI_IN_0(13), A1=>PRI_IN_1(13)); ix3469 : nor02 port map ( Y=>nx3468, A0=>nx3199, A1=>nx3480); ix3515 : ao21 port map ( Y=>PRI_OUT_1(14), A0=>nx3199, A1=>reg_2_q_c_14, B0=>nx3512); REG_2_reg_q_14 : dff port map ( Q=>reg_2_q_c_14, QB=>OPEN, D=>nx3500, CLK =>CLK); ix3501 : xor2 port map ( Y=>nx3500, A0=>nx3019, A1=>nx3022); ix3020 : aoi22 port map ( Y=>nx3019, A0=>nx3482, A1=>reg_10_q_c_13, B0=> nx3434, B1=>nx3454); ix3023 : xnor2 port map ( Y=>nx3022, A0=>reg_10_q_c_14, A1=>nx3485); REG_10_reg_q_14 : dff port map ( Q=>reg_10_q_c_14, QB=>OPEN, D=>nx3490, CLK=>CLK); ix3491 : xor2 port map ( Y=>nx3490, A0=>nx3027, A1=>nx3031); ix3028 : aoi22 port map ( Y=>nx3027, A0=>PRI_IN_1(13), A1=>PRI_IN_0(13), B0=>nx3442, B1=>nx3444); ix3032 : xnor2 port map ( Y=>nx3031, A0=>PRI_IN_0(14), A1=>PRI_IN_1(14)); ix3513 : nor02 port map ( Y=>nx3512, A0=>nx3199, A1=>nx2134); ix3559 : ao21 port map ( Y=>PRI_OUT_1(15), A0=>nx2730, A1=>reg_2_q_c_15, B0=>nx3556); REG_2_reg_q_15 : dff port map ( Q=>reg_2_q_c_15, QB=>OPEN, D=>nx3544, CLK =>CLK); ix3545 : xnor2 port map ( Y=>nx3544, A0=>nx3522, A1=>nx3045); ix3523 : mux21 port map ( Y=>nx3522, A0=>nx3019, A1=>nx2701, S0=>nx3022); ix3046 : xnor2 port map ( Y=>nx3045, A0=>reg_10_q_c_15, A1=>nx1450); REG_10_reg_q_15 : dff port map ( Q=>reg_10_q_c_15, QB=>OPEN, D=>nx3534, CLK=>CLK); ix3535 : xnor2 port map ( Y=>nx3534, A0=>nx3530, A1=>nx3053); ix3531 : oai22 port map ( Y=>nx3530, A0=>nx3027, A1=>nx3031, B0=>nx2167, B1=>nx2715); ix3054 : xnor2 port map ( Y=>nx3053, A0=>PRI_IN_0(15), A1=>PRI_IN_1(15)); ix3557 : nor02 port map ( Y=>nx3556, A0=>nx2730, A1=>nx2176); REG_1_reg_q_0 : dff port map ( Q=>PRI_OUT_0(0), QB=>OPEN, D=>nx1910, CLK =>CLK); ix1911 : oai21 port map ( Y=>nx1910, A0=>nx3061, A1=>PRI_OUT_2_0_EXMPLR, B0=>nx1902); ix3062 : inv02 port map ( Y=>nx3061, A=>PRI_IN_2(0)); ix1903 : nand02 port map ( Y=>nx1902, A0=>PRI_OUT_2_0_EXMPLR, A1=>nx3061 ); REG_1_reg_q_1 : dff port map ( Q=>PRI_OUT_0(1), QB=>OPEN, D=>nx1948, CLK =>CLK); ix1949 : xor2 port map ( Y=>nx1948, A0=>nx1902, A1=>nx1946); REG_1_reg_q_2 : dff port map ( Q=>PRI_OUT_0(2), QB=>OPEN, D=>nx2014, CLK =>CLK); ix2015 : xnor2 port map ( Y=>nx2014, A0=>nx3071, A1=>nx2012); ix3072 : aoi22 port map ( Y=>nx3071, A0=>nx3073, A1=>PRI_IN_2(1), B0=> nx1902, B1=>nx1946); ix3074 : mux21 port map ( Y=>nx3073, A0=>nx1411, A1=>reg_4_q_c_1, S0=> C_MUX2_1_SEL); ix2013 : xnor2 port map ( Y=>nx2012, A0=>PRI_IN_2(2), A1=> PRI_OUT_2_2_EXMPLR); REG_1_reg_q_3 : dff port map ( Q=>PRI_OUT_0(3), QB=>OPEN, D=>nx2080, CLK =>CLK); ix2081 : xor2 port map ( Y=>nx2080, A0=>nx2030, A1=>nx2078); ix2031 : mux21 port map ( Y=>nx2030, A0=>PRI_OUT_2_2_EXMPLR, A1=>nx3071, S0=>nx2012); REG_1_reg_q_4 : dff port map ( Q=>PRI_OUT_0(4), QB=>OPEN, D=>nx2146, CLK =>CLK); ix2147 : xnor2 port map ( Y=>nx2146, A0=>nx3089, A1=>nx2144); ix3090 : aoi22 port map ( Y=>nx3089, A0=>nx3091, A1=>PRI_IN_2(3), B0=> nx2030, B1=>nx2078); ix3092 : mux21 port map ( Y=>nx3091, A0=>nx1416_XX0_XREP11, A1=> reg_4_q_c_3, S0=>C_MUX2_1_SEL); ix2145 : xnor2 port map ( Y=>nx2144, A0=>PRI_IN_2(4), A1=> PRI_OUT_2_4_EXMPLR); REG_1_reg_q_5 : dff port map ( Q=>PRI_OUT_0(5), QB=>OPEN, D=>nx2212, CLK =>CLK); ix2213 : xor2 port map ( Y=>nx2212, A0=>nx2162, A1=>nx2210); ix2163 : mux21 port map ( Y=>nx2162, A0=>PRI_OUT_2_4_EXMPLR, A1=>nx3089, S0=>nx2144); REG_1_reg_q_6 : dff port map ( Q=>PRI_OUT_0(6), QB=>OPEN, D=>nx2278, CLK =>CLK); ix2279 : xnor2 port map ( Y=>nx2278, A0=>nx3103, A1=>nx2276); ix3104 : aoi22 port map ( Y=>nx3103, A0=>nx3105, A1=>PRI_IN_2(5), B0=> nx2162, B1=>nx2210); ix3106 : mux21 port map ( Y=>nx3105, A0=>nx3389, A1=>reg_4_q_c_5, S0=> C_MUX2_1_SEL); ix2277 : xnor2 port map ( Y=>nx2276, A0=>PRI_IN_2(6), A1=> PRI_OUT_2_6_EXMPLR); REG_1_reg_q_7 : dff port map ( Q=>PRI_OUT_0(7), QB=>OPEN, D=>nx2344, CLK =>CLK); ix2345 : xor2 port map ( Y=>nx2344, A0=>nx2294, A1=>nx2342); ix2295 : mux21 port map ( Y=>nx2294, A0=>PRI_OUT_2_6_EXMPLR, A1=>nx3103, S0=>nx2276); REG_1_reg_q_8 : dff port map ( Q=>PRI_OUT_0(8), QB=>OPEN, D=>nx2410, CLK =>CLK); ix2411 : xnor2 port map ( Y=>nx2410, A0=>nx3117, A1=>nx2408); ix3118 : aoi22 port map ( Y=>nx3117, A0=>nx3119, A1=>PRI_IN_2(7), B0=> nx2294, B1=>nx2342); ix3120 : mux21 port map ( Y=>nx3119, A0=>nx1429, A1=>reg_4_q_c_7, S0=> C_MUX2_1_SEL); ix2409 : xnor2 port map ( Y=>nx2408, A0=>PRI_IN_2(8), A1=> PRI_OUT_2_8_EXMPLR); REG_1_reg_q_9 : dff port map ( Q=>PRI_OUT_0(9), QB=>OPEN, D=>nx2476, CLK =>CLK); ix2477 : xor2 port map ( Y=>nx2476, A0=>nx2426, A1=>nx2474); ix2427 : mux21 port map ( Y=>nx2426, A0=>PRI_OUT_2_8_EXMPLR, A1=>nx3117, S0=>nx2408); REG_1_reg_q_10 : dff port map ( Q=>PRI_OUT_0(10), QB=>OPEN, D=>nx2542, CLK=>CLK); ix2543 : xnor2 port map ( Y=>nx2542, A0=>nx3135, A1=>nx2540); ix3136 : aoi22 port map ( Y=>nx3135, A0=>nx3137, A1=>PRI_IN_2(9), B0=> nx2426, B1=>nx2474); ix3138 : mux21 port map ( Y=>nx3137, A0=>nx1433, A1=>reg_4_q_c_9, S0=> C_MUX2_1_SEL); ix2541 : xnor2 port map ( Y=>nx2540, A0=>PRI_IN_2(10), A1=> PRI_OUT_2_10_EXMPLR); REG_1_reg_q_11 : dff port map ( Q=>PRI_OUT_0(11), QB=>OPEN, D=>nx2608, CLK=>CLK); ix2609 : xor2 port map ( Y=>nx2608, A0=>nx2558, A1=>nx2606); ix2559 : mux21 port map ( Y=>nx2558, A0=>PRI_OUT_2_10_EXMPLR, A1=>nx3135, S0=>nx2540); REG_1_reg_q_12 : dff port map ( Q=>PRI_OUT_0(12), QB=>OPEN, D=>nx2674, CLK=>CLK); ix2675 : xnor2 port map ( Y=>nx2674, A0=>nx3151, A1=>nx2672); ix2673 : xnor2 port map ( Y=>nx2672, A0=>PRI_IN_2(12), A1=> PRI_OUT_2_12_EXMPLR); REG_1_reg_q_13 : dff port map ( Q=>PRI_OUT_0(13), QB=>OPEN, D=>nx2740, CLK=>CLK); ix2741 : xor2 port map ( Y=>nx2740, A0=>nx2690, A1=>nx2738); REG_1_reg_q_14 : dff port map ( Q=>PRI_OUT_0(14), QB=>OPEN, D=>nx2806, CLK=>CLK); ix2807 : xnor2 port map ( Y=>nx2806, A0=>nx3167, A1=>nx2804); ix2805 : xnor2 port map ( Y=>nx2804, A0=>PRI_IN_2(14), A1=> PRI_OUT_2_14_EXMPLR); REG_1_reg_q_15 : dff port map ( Q=>PRI_OUT_0(15), QB=>OPEN, D=>nx2872, CLK=>CLK); ix3180 : xor2 port map ( Y=>nx3179, A0=>PRI_IN_2(15), A1=> PRI_OUT_2_15_EXMPLR); ix3455 : inv02 port map ( Y=>nx3454, A=>nx3001); ix3445 : inv02 port map ( Y=>nx3444, A=>nx3009); ix3367 : inv02 port map ( Y=>nx3366, A=>nx2959); ix3357 : inv02 port map ( Y=>nx3356, A=>nx2966); ix3279 : inv02 port map ( Y=>nx3278, A=>nx2917); ix3269 : inv02 port map ( Y=>nx3268, A=>nx2923); ix3191 : inv02 port map ( Y=>nx3190, A=>nx2875); ix3181 : inv02 port map ( Y=>nx3180, A=>nx2881); ix3103 : inv02 port map ( Y=>nx3102, A=>nx2831); ix3093 : inv02 port map ( Y=>nx3092, A=>nx2839); ix3015 : inv02 port map ( Y=>nx3014, A=>nx2789); ix3005 : inv02 port map ( Y=>nx3004, A=>nx2796); ix2927 : inv02 port map ( Y=>nx2926, A=>nx2747); ix2917 : inv02 port map ( Y=>nx2916, A=>nx2755); ix2781 : inv02 port map ( Y=>nx2780, A=>nx2695); ix2725 : inv02 port map ( Y=>nx2724, A=>nx2661); ix2649 : inv02 port map ( Y=>nx2648, A=>nx2645); ix2593 : inv02 port map ( Y=>nx2592, A=>nx2609); ix2517 : inv02 port map ( Y=>nx2516, A=>nx2590); ix2461 : inv02 port map ( Y=>nx2460, A=>nx2553); ix2385 : inv02 port map ( Y=>nx2384, A=>nx2534); ix2329 : inv02 port map ( Y=>nx2328, A=>nx2501); ix2253 : inv02 port map ( Y=>nx2252, A=>nx2482); ix2197 : inv02 port map ( Y=>nx2196, A=>nx2451); ix2121 : inv02 port map ( Y=>nx2120, A=>nx2429); ix2065 : inv02 port map ( Y=>nx2064, A=>nx2395); ix1989 : inv02 port map ( Y=>nx1988, A=>nx2377); ix1933 : inv02 port map ( Y=>nx1932, A=>nx2345); ix1555 : inv02 port map ( Y=>nx1554, A=>nx2199); ix2158 : inv02 port map ( Y=>nx2157, A=>nx1450); ix2186 : inv02 port map ( Y=>nx2185, A=>nx1424); ix2702 : inv02 port map ( Y=>nx2701, A=>nx3485); ix1287 : inv02 port map ( Y=>nx1286, A=>nx2069); ix1271 : inv02 port map ( Y=>nx1270, A=>nx2079); ix2088 : inv02 port map ( Y=>nx2087, A=>nx1224); ix2652 : inv02 port map ( Y=>nx2651, A=>nx1443); ix1087 : inv02 port map ( Y=>nx1086, A=>nx1975); ix1071 : inv02 port map ( Y=>nx1070, A=>nx1987); ix1997 : inv02 port map ( Y=>nx1996, A=>nx1024); ix2598 : inv02 port map ( Y=>nx2597, A=>nx3476); ix941 : inv02 port map ( Y=>nx1435, A=>nx1898); ix887 : inv02 port map ( Y=>nx886, A=>nx1883); ix871 : inv02 port map ( Y=>nx870, A=>nx1895); ix1908 : inv02 port map ( Y=>nx1907, A=>nx824); ix2542 : inv02 port map ( Y=>nx2541, A=>nx1431); ix741 : inv02 port map ( Y=>nx1430, A=>nx1805); ix687 : inv02 port map ( Y=>nx686, A=>nx1791); ix671 : inv02 port map ( Y=>nx670, A=>nx1801); ix1814 : inv02 port map ( Y=>nx1813, A=>nx624); ix2488 : inv02 port map ( Y=>nx2487, A=>nx1427); ix541 : inv02 port map ( Y=>nx1425, A=>nx1709); ix487 : inv02 port map ( Y=>nx486, A=>nx1695); ix471 : inv02 port map ( Y=>nx470, A=>nx1705); ix1717 : inv02 port map ( Y=>nx1716, A=>nx424); ix2436 : inv02 port map ( Y=>nx2435, A=>nx1419); ix341 : inv02 port map ( Y=>nx1417, A=>nx1611); ix287 : inv02 port map ( Y=>nx286, A=>nx1597); ix271 : inv02 port map ( Y=>nx270, A=>nx1607); ix1618 : inv02 port map ( Y=>nx1617, A=>nx224); ix2384 : inv02 port map ( Y=>nx2383, A=>nx1414_XX0_XREP13); ix141 : inv02 port map ( Y=>nx1413, A=>nx1525); ix105 : inv02 port map ( Y=>nx104, A=>nx1513); ix89 : inv02 port map ( Y=>nx88, A=>nx1521); ix1472 : inv02 port map ( Y=>nx1471, A=>nx1409_XX0_XREP17); ix1945 : inv02 port map ( Y=>PRI_OUT_2(1), A=>nx3073); ix2077 : inv02 port map ( Y=>PRI_OUT_2(3), A=>nx3091); ix2209 : inv02 port map ( Y=>PRI_OUT_2(5), A=>nx3105); ix2341 : inv02 port map ( Y=>PRI_OUT_2(7), A=>nx3119); ix2473 : inv02 port map ( Y=>PRI_OUT_2(9), A=>nx3137); ix2605 : inv02 port map ( Y=>PRI_OUT_2(11), A=>nx3153); ix2737 : inv02 port map ( Y=>PRI_OUT_2(13), A=>nx3169); ix3187 : inv02 port map ( Y=>nx3188, A=>C_MUX2_2_SEL); ix3189 : inv02 port map ( Y=>nx3191, A=>C_MUX2_2_SEL); ix3192 : inv02 port map ( Y=>nx3193, A=>C_MUX2_2_SEL); ix3194 : inv02 port map ( Y=>nx3195, A=>C_MUX2_2_SEL); ix3196 : inv02 port map ( Y=>nx3197, A=>C_MUX2_2_SEL); ix3198 : inv02 port map ( Y=>nx3199, A=>C_MUX2_2_SEL); ix7 : xor2 port map ( Y=>nx6, A0=>PRI_IN_2(0), A1=>PRI_IN_1(0)); ix2156 : xor2 port map ( Y=>nx2154, A0=>PRI_IN_2(15), A1=>nx1450); ix2322 : xor2 port map ( Y=>nx2321, A0=>PRI_IN_4(15), A1=>PRI_IN_0(15)); ix2370 : xor2 port map ( Y=>nx2369, A0=>PRI_IN_0(2), A1=>nx2379); ix2422 : xor2 port map ( Y=>nx2421, A0=>PRI_IN_0(4), A1=>nx2431); ix2478 : xor2 port map ( Y=>nx2477, A0=>PRI_IN_0(6), A1=>nx2484); ix2530 : xor2 port map ( Y=>nx2529, A0=>PRI_IN_0(8), A1=>nx2537); ix2586 : xor2 port map ( Y=>nx2585, A0=>PRI_IN_0(10), A1=>nx2593); ix2638 : xor2 port map ( Y=>nx2637, A0=>PRI_IN_0(12), A1=>nx2647); ix2688 : xor2 port map ( Y=>nx2687, A0=>PRI_IN_0(14), A1=>nx2697); ix2901 : xor2 port map ( Y=>nx2900, A0=>reg_10_q_c_0, A1=>nx1409); ix2887 : xor2 port map ( Y=>nx2886, A0=>PRI_IN_0(0), A1=>PRI_IN_1(0)); ix1947 : xor2 port map ( Y=>nx1946, A0=>PRI_IN_2(1), A1=>nx3073); ix2079 : xor2 port map ( Y=>nx2078, A0=>PRI_IN_2(3), A1=>nx3091); ix2211 : xor2 port map ( Y=>nx2210, A0=>PRI_IN_2(5), A1=>nx3105); ix2343 : xor2 port map ( Y=>nx2342, A0=>PRI_IN_2(7), A1=>nx3119); ix2475 : xor2 port map ( Y=>nx2474, A0=>PRI_IN_2(9), A1=>nx3137); ix1569 : mux21 port map ( Y=>nx1568, A0=>reg_3_q_c_2, A1=>PRI_IN_3(2), S0 =>C_MUX2_3_SEL); REG_3_reg_q_2 : dff port map ( Q=>reg_3_q_c_2, QB=>OPEN, D=>nx226, CLK=> CLK); ix1569_0_XREP1 : mux21 port map ( Y=>nx1568_XX0_XREP1, A0=>reg_3_q_c_2, A1=>PRI_IN_3(2), S0=>C_MUX2_3_SEL); ix1526 : mux21 port map ( Y=>nx1525, A0=>reg_3_q_c_1, A1=>PRI_IN_3(1), S0 =>C_MUX2_3_SEL); REG_3_reg_q_1 : dff port map ( Q=>reg_3_q_c_1, QB=>OPEN, D=>nx126, CLK=> CLK); ix1526_0_XREP3 : mux21 port map ( Y=>nx1525_XX0_XREP3, A0=>reg_3_q_c_1, A1=>PRI_IN_3(1), S0=>C_MUX2_3_SEL); ix1490 : mux21 port map ( Y=>nx1489, A0=>reg_3_q_c_0, A1=>PRI_IN_3(0), S0 =>C_MUX2_3_SEL); REG_3_reg_q_0 : dff port map ( Q=>reg_3_q_c_0, QB=>OPEN, D=>nx54, CLK=> CLK); ix1490_0_XREP5 : mux21 port map ( Y=>nx1489_XX0_XREP5, A0=>reg_3_q_c_0, A1=>PRI_IN_3(0), S0=>C_MUX2_3_SEL); ix515 : ao21 port map ( Y=>nx1423, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_5, B0 =>nx490); REG_6_reg_q_5 : dff port map ( Q=>reg_6_q_c_5, QB=>OPEN, D=>nx504, CLK=> CLK); ix491 : nor02 port map ( Y=>nx490, A0=>C_MUX2_4_SEL, A1=>nx1695); ix415 : ao21 port map ( Y=>nx1419, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_4, B0 =>nx390); REG_6_reg_q_4 : dff port map ( Q=>reg_6_q_c_4, QB=>OPEN, D=>nx404, CLK=> CLK); ix391 : nor02 port map ( Y=>nx390, A0=>C_MUX2_4_SEL, A1=>nx1649); ix315 : ao21 port map ( Y=>nx1416, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_3, B0 =>nx290); REG_6_reg_q_3 : dff port map ( Q=>reg_6_q_c_3, QB=>OPEN, D=>nx304, CLK=> CLK); ix291 : nor02 port map ( Y=>nx290, A0=>C_MUX2_4_SEL, A1=>nx1597); ix315_0_XREP11 : ao21 port map ( Y=>nx1416_XX0_XREP11, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_3, B0=>nx290); ix215 : ao21 port map ( Y=>nx1414, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_2, B0 =>nx190); REG_6_reg_q_2 : dff port map ( Q=>reg_6_q_c_2, QB=>OPEN, D=>nx204, CLK=> CLK); ix191 : nor02 port map ( Y=>nx190, A0=>C_MUX2_4_SEL, A1=>nx1555); ix215_0_XREP13 : ao21 port map ( Y=>nx1414_XX0_XREP13, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_2, B0=>nx190); ix123 : ao21 port map ( Y=>nx1411, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_1, B0 =>nx108); REG_6_reg_q_1 : dff port map ( Q=>reg_6_q_c_1, QB=>OPEN, D=>nx112, CLK=> CLK); ix109 : nor02 port map ( Y=>nx108, A0=>C_MUX2_4_SEL, A1=>nx1513); ix47 : ao21 port map ( Y=>nx1409, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_0, B0=> nx24); REG_6_reg_q_0 : dff port map ( Q=>reg_6_q_c_0, QB=>OPEN, D=>nx36, CLK=> CLK); ix25 : nor02 port map ( Y=>nx24, A0=>C_MUX2_4_SEL, A1=>nx1487); ix47_0_XREP17 : ao21 port map ( Y=>nx1409_XX0_XREP17, A0=>C_MUX2_4_SEL, A1=>reg_6_q_c_0, B0=>nx24); ix3487 : buf04 port map ( Y=>nx3389, A=>nx1423); ix3488 : buf04 port map ( Y=>nx3390, A=>nx1419); ix3489 : buf04 port map ( Y=>nx3391, A=>nx1411); \[8955__XX0_XREP4\ : buf04 port map ( Y=>\[8955__XX0_XREP4\, A=>nx1411); ix3490 : inv02 port map ( Y=>nx3392, A=>C_MUX2_1_SEL); ix3492 : inv02 port map ( Y=>nx3393, A=>PRI_IN_2(13)); ix3493 : ao221 port map ( Y=>nx3394, A0=>reg_4_q_c_13, A1=>C_MUX2_1_SEL, B0=>nx3482, B1=>nx3423, C0=>nx3393); ix3494 : inv02 port map ( Y=>nx3395, A=>PRI_IN_2(11)); ix3495 : oai221 port map ( Y=>nx3396, A0=>C_MUX2_1_SEL, A1=>nx3426, B0=> nx3423, B1=>nx3428, C0=>nx3430); ix3496 : inv01 port map ( Y=>nx3397, A=>nx2672); ix3497 : inv01 port map ( Y=>nx3398, A=>PRI_OUT_2_12_EXMPLR); ix3498 : oai33 port map ( Y=>nx3399, A0=>nx3430, A1=>nx3423, A2=>nx3428, B0=>nx3430, B1=>C_MUX2_1_SEL, B2=>nx3426); ix3499 : aoi322 port map ( Y=>nx3400, A0=>nx2558, A1=>nx2672, A2=>nx3396, B0=>nx3397, B1=>nx3398, C0=>nx2672, C1=>nx3399); ix3500 : ao22 port map ( Y=>nx3401, A0=>nx3483, A1=>nx3423, B0=> reg_4_q_c_13, B1=>C_MUX2_1_SEL); ix3502 : aoi22 port map ( Y=>nx3403, A0=>nx3394, A1=>nx3400, B0=>nx3401, B1=>nx3393); ix3503 : inv02 port map ( Y=>nx3404, A=>nx2804); ix3504 : or02 port map ( Y=>nx3405, A0=>nx3404, A1=>nx3179); ix3505 : inv02 port map ( Y=>nx3406, A=>PRI_OUT_2_14_EXMPLR); ix3506 : inv02 port map ( Y=>nx3407, A=>nx3179); ix3507 : and02 port map ( Y=>nx3408, A0=>nx3179, A1=>nx2804); ix3508 : aoi332 port map ( Y=>nx3409, A0=>nx3179, A1=>nx3404, A2=>nx3406, B0=>nx3407, B1=>PRI_OUT_2_14_EXMPLR, B2=>nx3404, C0=>nx3403, C1=> nx3408); nx2872_EXMPLR : oai21 port map ( Y=>nx2872, A0=>nx3403, A1=>nx3405, B0=> nx3409); nx3167_EXMPLR : inv01 port map ( Y=>nx3167, A=>nx3403); nx3169_EXMPLR : oai22 port map ( Y=>nx3169, A0=>C_MUX2_1_SEL, A1=>nx3483, B0=>nx3425, B1=>reg_4_q_c_13); nx2690_EXMPLR : inv01 port map ( Y=>nx2690, A=>nx3400); ix3509 : inv02 port map ( Y=>nx3410, A=>reg_4_q_c_13); ix3510 : aoi22 port map ( Y=>nx3411, A0=>PRI_IN_2(13), A1=>reg_4_q_c_13, B0=>nx3393, B1=>nx3410); ix3511 : inv02 port map ( Y=>nx3413, A=>nx3483); ix3512 : aoi22 port map ( Y=>nx3414, A0=>PRI_IN_2(13), A1=>nx3484, B0=> nx3393, B1=>nx3413); nx2738_EXMPLR : oai22 port map ( Y=>nx2738, A0=>nx3425, A1=>nx3411, B0=> nx3414, B1=>C_MUX2_1_SEL); ix3514 : aoi221 port map ( Y=>nx3415, A0=>nx3426, A1=>nx3425, B0=> C_MUX2_1_SEL, B1=>nx3428, C0=>nx3431); ix3516 : and02 port map ( Y=>nx3416, A0=>C_MUX2_1_SEL, A1=>nx3429); ix3517 : and02 port map ( Y=>nx3417, A0=>nx3478, A1=>nx3425); ix3518 : oai21 port map ( Y=>nx3418, A0=>nx3416, A1=>nx3417, B0=>nx3431); nx3151_EXMPLR : oai21 port map ( Y=>nx3151, A0=>nx3415, A1=>nx2558, B0=> nx3418); nx3153_EXMPLR : oai22 port map ( Y=>nx3153, A0=>C_MUX2_1_SEL, A1=>nx3478, B0=>nx3425, B1=>nx3429); ix3519 : inv02 port map ( Y=>nx3419, A=>nx3429); ix3520 : aoi22 port map ( Y=>nx3420, A0=>PRI_IN_2(11), A1=>nx3429, B0=> nx3431, B1=>nx3419); ix3521 : inv02 port map ( Y=>nx3421, A=>nx3479); ix3522 : aoi22 port map ( Y=>nx3422, A0=>PRI_IN_2(11), A1=>nx3479, B0=> nx3431, B1=>nx3421); nx2606_EXMPLR : oai22 port map ( Y=>nx2606, A0=>nx3425, A1=>nx3420, B0=> nx3422, B1=>C_MUX2_1_SEL); ix3524 : buf04 port map ( Y=>nx3423, A=>nx3392); ix3525 : buf04 port map ( Y=>nx3425, A=>nx3392); ix3526 : buf04 port map ( Y=>nx3426, A=>nx1440); ix3527 : buf04 port map ( Y=>nx3427, A=>nx1440); ix3528 : buf04 port map ( Y=>nx3428, A=>reg_4_q_c_11); ix3529 : buf04 port map ( Y=>nx3429, A=>reg_4_q_c_11); ix3530 : buf04 port map ( Y=>nx3430, A=>nx3395); ix3532 : buf04 port map ( Y=>nx3431, A=>nx3395); ix3533 : inv02 port map ( Y=>nx3432, A=>C_MUX2_3_SEL); ix3534 : aoi22 port map ( Y=>nx3433, A0=>reg_3_q_c_10, A1=>nx3474, B0=> C_MUX2_3_SEL, B1=>PRI_IN_3(10)); ix3536 : aoi21 port map ( Y=>nx3435, A0=>nx3477, A1=>nx3433, B0=>nx960); ix3537 : nor02 port map ( Y=>nx3436, A0=>nx3433, A1=>nx3477); ix3538 : nor02 port map ( Y=>nx3437, A0=>nx3435, A1=>nx3436); nx1441_EXMPLR : inv02 port map ( Y=>nx1441, A=>nx1991); ix3539 : inv02 port map ( Y=>nx3438, A=>nx3479); ix3540 : inv02 port map ( Y=>nx3439, A=>nx1443); ix3541 : inv02 port map ( Y=>nx3440, A=>reg_3_q_c_12); ix3542 : inv02 port map ( Y=>nx3441, A=>PRI_IN_3(12)); ix3543 : aoi22 port map ( Y=>nx3443, A0=>nx3474, A1=>nx3440, B0=> C_MUX2_3_SEL, B1=>nx3441); ix3544 : aoi22 port map ( Y=>nx3445, A0=>reg_3_q_c_12, A1=>nx3474, B0=> C_MUX2_3_SEL, B1=>PRI_IN_3(12)); nx2011_EXMPLR : oai22 port map ( Y=>nx2011, A0=>nx3439, A1=>nx3443, B0=> nx3445, B1=>nx1443); ix3546 : inv02 port map ( Y=>nx3447, A=>nx2011); ix3547 : oai21 port map ( Y=>nx3448, A0=>nx1441, A1=>nx3438, B0=>nx3447); ix3548 : nand03 port map ( Y=>nx3449, A0=>nx3447, A1=>nx1441, A2=>nx3438 ); nx2057_EXMPLR : oai221 port map ( Y=>nx2057, A0=>nx3437, A1=>nx3448, B0=> nx3447, B1=>nx3445, C0=>nx3449); ix3549 : inv01 port map ( Y=>nx3450, A=>nx2057); ix3550 : inv02 port map ( Y=>nx3451, A=>nx3486); ix3551 : inv02 port map ( Y=>nx3452, A=>reg_3_q_c_14); ix3552 : inv02 port map ( Y=>nx3453, A=>PRI_IN_3(14)); ix3553 : aoi22 port map ( Y=>nx3455, A0=>nx3474, A1=>nx3452, B0=> C_MUX2_3_SEL, B1=>nx3453); ix3554 : aoi22 port map ( Y=>nx3457, A0=>reg_3_q_c_14, A1=>nx3475, B0=> PRI_IN_3(14), B1=>C_MUX2_3_SEL); nx1447_EXMPLR : inv02 port map ( Y=>nx1447, A=>nx3481); ix3555 : inv02 port map ( Y=>nx3458, A=>nx3484); ix3556 : oai222 port map ( Y=>nx3459, A0=>nx3451, A1=>nx3455, B0=>nx3457, B1=>nx3486, C0=>nx1447, C1=>nx3458); nx2105_EXMPLR : oai22 port map ( Y=>nx2105, A0=>nx3451, A1=>nx3455, B0=> nx3457, B1=>nx3486); ix3558 : inv02 port map ( Y=>nx3460, A=>nx2105); ix3560 : nor02 port map ( Y=>nx3461, A0=>nx3481, A1=>nx3484); ix3561 : oai221 port map ( Y=>nx3462, A0=>nx3457, A1=>nx3486, B0=>nx3451, B1=>nx3455, C0=>nx3461); nx2147_EXMPLR : oai221 port map ( Y=>nx2147, A0=>nx3450, A1=>nx3459, B0=> nx3460, B1=>nx3457, C0=>nx3462); ix3562 : or02 port map ( Y=>nx3463, A0=>nx3481, A1=>nx3484); ix3563 : and02 port map ( Y=>nx3464, A0=>nx3481, A1=>nx3484); nx1360_EXMPLR : ao21 port map ( Y=>nx1360, A0=>nx3463, A1=>nx3450, B0=> nx3464); nx2134_EXMPLR : oai22 port map ( Y=>nx2134, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_14, B0=>nx3475, B1=>PRI_IN_3(14)); ix3564 : inv02 port map ( Y=>nx3465, A=>nx3460); ix3565 : inv01 port map ( Y=>nx3466, A=>nx3450); nx2059_EXMPLR : oai22 port map ( Y=>nx2059, A0=>nx3481, A1=>nx3484, B0=> nx1447, B1=>nx3458); ix3566 : nor02 port map ( Y=>nx3467, A0=>nx1991, A1=>nx3479); nx1160_EXMPLR : oai32 port map ( Y=>nx1160, A0=>nx3467, A1=>nx3435, A2=> nx3436, B0=>nx1441, B1=>nx3438); nx2041_EXMPLR : oai22 port map ( Y=>nx2041, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_12, B0=>nx3475, B1=>PRI_IN_3(12)); ix3567 : inv02 port map ( Y=>nx3469, A=>nx3447); nx1961_EXMPLR : inv01 port map ( Y=>nx1961, A=>nx3437); nx1963_EXMPLR : oai22 port map ( Y=>nx1963, A0=>nx1991, A1=>nx3479, B0=> nx1441, B1=>nx3438); nx1949_EXMPLR : oai22 port map ( Y=>nx1949, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_10, B0=>nx3475, B1=>PRI_IN_3(10)); ix3568 : inv02 port map ( Y=>nx3470, A=>nx3477); ix3569 : inv02 port map ( Y=>nx3471, A=>reg_3_q_c_10); ix3570 : inv02 port map ( Y=>nx3472, A=>PRI_IN_3(10)); ix3571 : aoi22 port map ( Y=>nx3473, A0=>nx3475, A1=>nx3471, B0=> C_MUX2_3_SEL, B1=>nx3472); nx1921_EXMPLR : oai22 port map ( Y=>nx1921, A0=>nx3470, A1=>nx3473, B0=> nx3433, B1=>nx3477); ix3572 : buf04 port map ( Y=>nx3474, A=>nx3432); ix3573 : buf04 port map ( Y=>nx3475, A=>nx3432); ix3574 : buf16 port map ( Y=>nx3476, A=>nx1437); ix3575 : buf16 port map ( Y=>nx3477, A=>nx1437); ix3576 : buf16 port map ( Y=>nx3478, A=>nx3427); ix3577 : buf16 port map ( Y=>nx3479, A=>nx3427); ix3578 : buf16 port map ( Y=>nx3480, A=>nx2082); ix3579 : buf16 port map ( Y=>nx3481, A=>nx2082); ix3580 : buf16 port map ( Y=>nx3482, A=>nx1446); ix3581 : buf16 port map ( Y=>nx3483, A=>nx1446); ix3582 : buf16 port map ( Y=>nx3484, A=>nx1446); ix3583 : buf16 port map ( Y=>nx3485, A=>nx1448); ix3584 : buf16 port map ( Y=>nx3486, A=>nx1448); end CIRCUIT_arch ;