-- -- Definition of CIRCUIT -- -- 03/18/06 23:02:18 -- -- LeonardoSpectrum Level 3, 2005a.82 -- library IEEE; use IEEE.STD_LOGIC_1164.all; entity CIRCUIT is port ( PRI_IN_0 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_1 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_2 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_3 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_4 : IN std_logic_vector (15 DOWNTO 0) ; PRI_OUT_0 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_1 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_2 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_3 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_4 : OUT std_logic_vector (15 DOWNTO 0) ; C_MUX2_1_SEL : IN std_logic ; C_MUX2_2_SEL : IN std_logic ; C_MUX2_3_SEL : IN std_logic ; C_MUX2_4_SEL : IN std_logic ; C_MUX2_5_SEL : IN std_logic ; CLK : IN std_logic) ; end CIRCUIT ; architecture CIRCUIT_arch of CIRCUIT is signal PRI_OUT_0_15_EXMPLR, PRI_OUT_0_14_EXMPLR, PRI_OUT_0_13_EXMPLR, PRI_OUT_0_12_EXMPLR, PRI_OUT_0_11_EXMPLR, PRI_OUT_0_10_EXMPLR, PRI_OUT_0_9_EXMPLR, PRI_OUT_0_8_EXMPLR, PRI_OUT_0_7_EXMPLR, PRI_OUT_0_6_EXMPLR, PRI_OUT_0_5_EXMPLR, PRI_OUT_0_4_EXMPLR, PRI_OUT_0_3_EXMPLR, PRI_OUT_0_2_EXMPLR, PRI_OUT_0_1_EXMPLR, PRI_OUT_0_0_EXMPLR, PRI_OUT_4_15_EXMPLR, PRI_OUT_4_14_EXMPLR, PRI_OUT_4_13_EXMPLR, PRI_OUT_4_12_EXMPLR, PRI_OUT_4_11_EXMPLR, PRI_OUT_4_10_EXMPLR, PRI_OUT_4_9_EXMPLR, PRI_OUT_4_8_EXMPLR, PRI_OUT_4_7_EXMPLR, PRI_OUT_4_6_EXMPLR, PRI_OUT_4_5_EXMPLR, PRI_OUT_4_4_EXMPLR, PRI_OUT_4_3_EXMPLR, PRI_OUT_4_2_EXMPLR, PRI_OUT_4_1_EXMPLR, PRI_OUT_4_0_EXMPLR, nx2, nx10, nx18, nx20, nx38, nx40, nx56, nx58, nx60, nx78, nx80, nx96, nx98, nx100, nx118, nx120, nx136, nx138, nx140, nx158, nx160, nx176, nx178, nx180, nx198, nx200, nx216, nx218, nx220, nx238, nx240, nx256, nx258, nx260, nx278, nx280, nx296, nx300, nx310, nx318, nx326, nx328, nx346, nx348, nx364, nx366, nx368, nx386, nx388, nx404, nx406, nx408, nx426, nx428, nx444, nx446, nx448, nx466, nx468, nx484, nx486, nx488, nx506, nx508, nx524, nx526, nx528, nx546, nx548, nx564, nx566, nx568, nx586, nx588, nx604, nx608, reg_3_q_c_0, nx622, nx636, reg_4_q_c_0, nx650, nx660, nx670, reg_1_q_c_0, nx678, nx696, reg_3_q_c_1, nx704, nx706, reg_4_q_c_1, nx1411, nx720, nx736, reg_1_q_c_1, nx738, nx740, nx752, nx754, reg_3_q_c_2, nx780, reg_4_q_c_2, nx800, nx802, nx804, nx820, reg_1_q_c_2, nx832, nx846, nx858, nx860, reg_3_q_c_3, nx868, nx870, nx872, reg_4_q_c_3, nx1414, nx896, nx912, reg_1_q_c_3, nx920, nx922, nx924, nx936, nx938, reg_3_q_c_4, nx964, reg_4_q_c_4, nx984, nx986, nx988, nx1004, reg_1_q_c_4, nx1016, nx1030, nx1042, nx1044, reg_3_q_c_5, nx1052, nx1054, nx1056, reg_4_q_c_5, nx1417, nx1080, nx1096, reg_1_q_c_5, nx1104, nx1106, nx1108, nx1120, nx1122, reg_3_q_c_6, nx1148, reg_4_q_c_6, nx1168, nx1170, nx1172, nx1188, reg_1_q_c_6, nx1200, nx1214, nx1226, nx1228, reg_3_q_c_7, nx1236, nx1238, nx1240, reg_4_q_c_7, nx1421, nx1264, nx1280, reg_1_q_c_7, nx1288, nx1290, nx1292, nx1304, nx1306, reg_3_q_c_8, nx1332, reg_4_q_c_8, nx1352, nx1354, nx1356, nx1372, reg_1_q_c_8, nx1384, nx1398, nx1410, nx1412, reg_3_q_c_9, nx1420, nx1422, nx1424, reg_4_q_c_9, nx1425, nx1448, nx1464, reg_1_q_c_9, nx1472, nx1474, nx1476, nx1488, nx1490, reg_3_q_c_10, nx1516, reg_4_q_c_10, nx1536, nx1538, nx1540, nx1556, reg_1_q_c_10, nx1568, nx1582, nx1594, nx1596, reg_3_q_c_11, nx1604, nx1606, nx1608, reg_4_q_c_11, nx1427, nx1632, nx1648, reg_1_q_c_11, nx1656, nx1658, nx1660, nx1672, nx1674, reg_3_q_c_12, nx1700, reg_4_q_c_12, nx1720, nx1722, nx1724, nx1740, reg_1_q_c_12, nx1752, nx1766, nx1778, nx1780, reg_3_q_c_13, nx1788, nx1790, nx1792, reg_4_q_c_13, nx1429, nx1816, nx1832, reg_1_q_c_13, nx1840, nx1842, nx1844, nx1856, nx1858, reg_3_q_c_14, nx1884, reg_4_q_c_14, nx1904, nx1906, nx1908, nx1924, reg_1_q_c_14, nx1936, nx1950, nx1962, nx1964, reg_3_q_c_15, nx1972, nx1976, reg_4_q_c_15, nx1998, nx2000, nx2016, reg_1_q_c_15, nx2024, nx2028, nx2042, reg_7_q_c_0, reg_6_q_c_0, nx2056, nx2066, nx2074, reg_5_q_c_0, nx2092, nx2100, nx2112, nx2116, reg_7_q_c_1, reg_6_q_c_1, nx2120, nx2122, nx2130, nx2132, reg_5_q_c_1, nx2144, nx2146, nx2156, reg_7_q_c_2, reg_6_q_c_2, nx2180, nx2188, nx2190, reg_5_q_c_2, nx2212, nx2214, nx2224, reg_7_q_c_3, nx2236, reg_6_q_c_3, nx2244, nx2246, nx2248, nx2256, nx2258, reg_5_q_c_3, nx2278, nx2280, nx2282, nx2292, reg_7_q_c_4, reg_6_q_c_4, nx2316, nx2324, nx2326, reg_5_q_c_4, nx2348, nx2350, nx2360, reg_7_q_c_5, nx2372, reg_6_q_c_5, nx2380, nx2382, nx2384, nx2392, nx2394, reg_5_q_c_5, nx2414, nx2416, nx2418, nx2428, reg_7_q_c_6, reg_6_q_c_6, nx2452, nx2460, nx2462, reg_5_q_c_6, nx2484, nx2486, nx2496, reg_7_q_c_7, nx2508, reg_6_q_c_7, nx2516, nx2518, nx2520, nx2528, nx2530, reg_5_q_c_7, nx2550, nx2552, nx2554, nx2564, reg_7_q_c_8, reg_6_q_c_8, nx2588, nx2596, nx2598, reg_5_q_c_8, nx2620, nx2622, nx2632, reg_7_q_c_9, nx2644, reg_6_q_c_9, nx2652, nx2654, nx2656, nx2664, nx2666, reg_5_q_c_9, nx2686, nx2688, nx2690, nx2700, reg_7_q_c_10, reg_6_q_c_10, nx2724, nx2732, nx2734, reg_5_q_c_10, nx2756, nx2758, nx2768, reg_7_q_c_11, nx2780, reg_6_q_c_11, nx2788, nx2790, nx2792, nx2800, nx2802, reg_5_q_c_11, nx2822, nx2824, nx2826, nx2836, reg_7_q_c_12, reg_6_q_c_12, nx2860, nx2868, nx2870, reg_5_q_c_12, nx2892, nx2894, nx2904, reg_7_q_c_13, nx2916, reg_6_q_c_13, nx2924, nx2926, nx2928, nx2936, nx2938, reg_5_q_c_13, nx2958, nx2960, nx2962, nx2972, reg_7_q_c_14, reg_6_q_c_14, nx2996, nx3004, nx3006, reg_5_q_c_14, nx3028, nx3030, nx3040, reg_7_q_c_15, nx3052, reg_6_q_c_15, nx3060, nx3064, nx3074, reg_5_q_c_15, nx3094, nx3098, nx3108, nx1455, nx1461, nx1469, nx1473, nx1479, nx1481, nx1487, nx1489, nx1493, nx1497, nx1499, nx1505, nx1513, nx1517, nx1522, nx1527, nx1529, nx1531, nx1537, nx1541, nx1543, nx1553, nx1565, nx1573, nx1575, nx1577, nx1581, nx1587, nx1589, nx1595, nx1599, nx1607, nx1611, nx1617, nx1623, nx1625, nx1627, nx1633, nx1636, nx1638, nx1649, nx1661, nx1667, nx1669, nx1671, nx1675, nx1680, nx1682, nx1689, nx1693, nx1701, nx1704, nx1709, nx1715, nx1717, nx1719, nx1725, nx1728, nx1730, nx1741, nx1753, nx1759, nx1761, nx1763, nx1767, nx1772, nx1774, nx1781, nx1785, nx1793, nx1796, nx1801, nx1807, nx1809, nx1811, nx1817, nx1820, nx1822, nx1833, nx1845, nx1851, nx1853, nx1855, nx1859, nx1864, nx1866, nx1873, nx1877, nx1885, nx1888, nx1893, nx1899, nx1901, nx1903, nx1909, nx1912, nx1914, nx1925, nx1937, nx1943, nx1945, nx1947, nx1951, nx1956, nx1958, nx1965, nx1969, nx1977, nx1980, nx1985, nx1991, nx1993, nx1995, nx2001, nx2004, nx2006, nx2017, nx2029, nx2035, nx2037, nx2039, nx2043, nx2048, nx2051, nx2057, nx2060, nx2067, nx2071, nx2078, nx2083, nx2085, nx2087, nx2093, nx2097, nx2099, nx2107, nx2119, nx2127, nx2129, nx2131, nx2135, nx2141, nx2143, nx2149, nx2159, nx2171, nx2189, nx2203, nx2218, nx2233, nx2249, nx2261, nx2269, nx2275, nx2288, nx2291, nx2307, nx2309, nx2323, nx2325, nx2339, nx2341, nx2356, nx2359, nx2375, nx2377, nx2391, nx2393, nx2401, nx2409, nx2413, nx2417, nx2435, nx2437, nx2439, nx2455, nx2461, nx2465, nx2467, nx2473, nx2475, nx2492, nx2495, nx2505, nx2515, nx2523, nx2526, nx2529, nx2535, nx2537, nx2557, nx2559, nx2567, nx2577, nx2585, nx2589, nx2591, nx2597, nx2599, nx2615, nx2617, nx2626, nx2635, nx2643, nx2647, nx2649, nx2657, nx2659, nx2673, nx2675, nx2685, nx2694, nx2699, nx2703, nx2705, nx2713, nx2715, nx2731, nx2733, nx2740, nx2749, nx2757, nx2761, nx2763, nx2769, nx2771, nx2791, nx2793, nx2799, nx2807, nx2813, nx2817, nx2819, nx2827, nx2829, nx2839, nx2841, nx2847, nx2859, nx2861, nx2869, nx2871, nx2873, nx2875, nx2877, nx2879, nx2881, nx2883, nx2885, nx2887, nx2889, nx2891: std_logic ; begin PRI_OUT_0(15) <= PRI_OUT_0_15_EXMPLR ; PRI_OUT_0(14) <= PRI_OUT_0_14_EXMPLR ; PRI_OUT_0(13) <= PRI_OUT_0_13_EXMPLR ; PRI_OUT_0(12) <= PRI_OUT_0_12_EXMPLR ; PRI_OUT_0(11) <= PRI_OUT_0_11_EXMPLR ; PRI_OUT_0(10) <= PRI_OUT_0_10_EXMPLR ; PRI_OUT_0(9) <= PRI_OUT_0_9_EXMPLR ; PRI_OUT_0(8) <= PRI_OUT_0_8_EXMPLR ; PRI_OUT_0(7) <= PRI_OUT_0_7_EXMPLR ; PRI_OUT_0(6) <= PRI_OUT_0_6_EXMPLR ; PRI_OUT_0(5) <= PRI_OUT_0_5_EXMPLR ; PRI_OUT_0(4) <= PRI_OUT_0_4_EXMPLR ; PRI_OUT_0(3) <= PRI_OUT_0_3_EXMPLR ; PRI_OUT_0(2) <= PRI_OUT_0_2_EXMPLR ; PRI_OUT_0(1) <= PRI_OUT_0_1_EXMPLR ; PRI_OUT_0(0) <= PRI_OUT_0_0_EXMPLR ; PRI_OUT_4(15) <= PRI_OUT_4_15_EXMPLR ; PRI_OUT_4(14) <= PRI_OUT_4_14_EXMPLR ; PRI_OUT_4(13) <= PRI_OUT_4_13_EXMPLR ; PRI_OUT_4(12) <= PRI_OUT_4_12_EXMPLR ; PRI_OUT_4(11) <= PRI_OUT_4_11_EXMPLR ; PRI_OUT_4(10) <= PRI_OUT_4_10_EXMPLR ; PRI_OUT_4(9) <= PRI_OUT_4_9_EXMPLR ; PRI_OUT_4(8) <= PRI_OUT_4_8_EXMPLR ; PRI_OUT_4(7) <= PRI_OUT_4_7_EXMPLR ; PRI_OUT_4(6) <= PRI_OUT_4_6_EXMPLR ; PRI_OUT_4(5) <= PRI_OUT_4_5_EXMPLR ; PRI_OUT_4(4) <= PRI_OUT_4_4_EXMPLR ; PRI_OUT_4(3) <= PRI_OUT_4_3_EXMPLR ; PRI_OUT_4(2) <= PRI_OUT_4_2_EXMPLR ; PRI_OUT_4(1) <= PRI_OUT_4_1_EXMPLR ; PRI_OUT_4(0) <= PRI_OUT_4_0_EXMPLR ; REG_2_reg_q_0 : dff port map ( Q=>PRI_OUT_4_0_EXMPLR, QB=>OPEN, D=>nx696, CLK=>CLK); ix697 : xor2 port map ( Y=>nx696, A0=>PRI_IN_1(0), A1=>PRI_OUT_0_0_EXMPLR ); ix689 : ao21 port map ( Y=>PRI_OUT_0_0_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_0, B0=>nx670); REG_1_reg_q_0 : dff port map ( Q=>reg_1_q_c_0, QB=>OPEN, D=>nx678, CLK=> CLK); ix671 : nor02 port map ( Y=>nx670, A0=>C_MUX2_3_SEL, A1=>nx1455); ix1456 : aoi222 port map ( Y=>nx1455, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_0, B0=>PRI_OUT_4_0_EXMPLR, B1=>nx2869, C0=>reg_4_q_c_0, C1=>nx2875); REG_3_reg_q_0 : dff port map ( Q=>reg_3_q_c_0, QB=>OPEN, D=>nx622, CLK=> CLK); ix1462 : inv02 port map ( Y=>nx1461, A=>PRI_IN_2(0)); ix637 : nor02 port map ( Y=>nx636, A0=>C_MUX2_5_SEL, A1=>C_MUX2_1_SEL); REG_4_reg_q_0 : dff port map ( Q=>reg_4_q_c_0, QB=>OPEN, D=>nx650, CLK=> CLK); ix651 : ao21 port map ( Y=>nx650, A0=>PRI_IN_2(0), A1=>nx1455, B0=>nx1469 ); ix1470 : nor02 port map ( Y=>nx1469, A0=>nx1455, A1=>PRI_IN_2(0)); ix661 : and02 port map ( Y=>nx660, A0=>C_MUX2_5_SEL, A1=>nx1473); ix1474 : inv02 port map ( Y=>nx1473, A=>C_MUX2_1_SEL); REG_2_reg_q_1 : dff port map ( Q=>PRI_OUT_4_1_EXMPLR, QB=>OPEN, D=>nx754, CLK=>CLK); ix755 : xor2 port map ( Y=>nx754, A0=>nx1479, A1=>nx1481); ix1480 : nand02 port map ( Y=>nx1479, A0=>PRI_IN_1(0), A1=> PRI_OUT_0_0_EXMPLR); ix1482 : xnor2 port map ( Y=>nx1481, A0=>PRI_IN_1(1), A1=> PRI_OUT_0_1_EXMPLR); ix751 : ao21 port map ( Y=>PRI_OUT_0_1_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_1, B0=>nx736); REG_1_reg_q_1 : dff port map ( Q=>reg_1_q_c_1, QB=>OPEN, D=>nx740, CLK=> CLK); ix741 : xor2 port map ( Y=>nx740, A0=>nx1487, A1=>nx1489); ix1488 : nand02 port map ( Y=>nx1487, A0=>PRI_IN_4(0), A1=>PRI_IN_0(0)); ix1490 : xnor2 port map ( Y=>nx1489, A0=>PRI_IN_4(1), A1=>PRI_IN_0(1)); ix737 : nor02 port map ( Y=>nx736, A0=>C_MUX2_3_SEL, A1=>nx1493); ix1494 : aoi222 port map ( Y=>nx1493, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_1, B0=>PRI_OUT_4_1_EXMPLR, B1=>nx2869, C0=>reg_4_q_c_1, C1=>nx2875); REG_3_reg_q_1 : dff port map ( Q=>reg_3_q_c_1, QB=>OPEN, D=>nx706, CLK=> CLK); ix707 : xor2 port map ( Y=>nx706, A0=>nx1497, A1=>nx1499); ix1498 : nand02 port map ( Y=>nx1497, A0=>PRI_IN_0(0), A1=>PRI_IN_2(0)); ix1500 : xnor2 port map ( Y=>nx1499, A0=>PRI_IN_0(1), A1=>PRI_IN_2(1)); REG_4_reg_q_1 : dff port map ( Q=>reg_4_q_c_1, QB=>OPEN, D=>nx720, CLK=> CLK); ix721 : xor2 port map ( Y=>nx720, A0=>nx1469, A1=>nx1505); ix1506 : xnor2 port map ( Y=>nx1505, A0=>PRI_IN_2(1), A1=>nx1493); REG_2_reg_q_2 : dff port map ( Q=>PRI_OUT_4_2_EXMPLR, QB=>OPEN, D=>nx846, CLK=>CLK); ix847 : xor2 port map ( Y=>nx846, A0=>nx1513, A1=>nx1517); ix1514 : aoi32 port map ( Y=>nx1513, A0=>PRI_IN_1(0), A1=> PRI_OUT_0_0_EXMPLR, A2=>nx752, B0=>PRI_OUT_0_1_EXMPLR, B1=>PRI_IN_1(1) ); ix1518 : xnor2 port map ( Y=>nx1517, A0=>PRI_IN_1(2), A1=> PRI_OUT_0_2_EXMPLR); ix843 : ao21 port map ( Y=>PRI_OUT_0_2_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_2, B0=>nx820); REG_1_reg_q_2 : dff port map ( Q=>reg_1_q_c_2, QB=>nx1529, D=>nx832, CLK =>CLK); ix833 : xor2 port map ( Y=>nx832, A0=>nx1522, A1=>nx1527); ix1523 : aoi32 port map ( Y=>nx1522, A0=>PRI_IN_4(0), A1=>PRI_IN_0(0), A2 =>nx738, B0=>PRI_IN_0(1), B1=>PRI_IN_4(1)); ix1528 : xnor2 port map ( Y=>nx1527, A0=>PRI_IN_4(2), A1=>PRI_IN_0(2)); ix821 : nor02 port map ( Y=>nx820, A0=>C_MUX2_3_SEL, A1=>nx1531); ix1532 : aoi222 port map ( Y=>nx1531, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_2, B0=>PRI_OUT_4_2_EXMPLR, B1=>nx2869, C0=>reg_4_q_c_2, C1=>nx2875); REG_3_reg_q_2 : dff port map ( Q=>reg_3_q_c_2, QB=>OPEN, D=>nx780, CLK=> CLK); ix781 : xor2 port map ( Y=>nx780, A0=>nx1537, A1=>nx1543); ix1538 : aoi32 port map ( Y=>nx1537, A0=>PRI_IN_0(0), A1=>PRI_IN_2(0), A2 =>nx704, B0=>PRI_IN_2(1), B1=>PRI_IN_0(1)); ix1542 : inv02 port map ( Y=>nx1541, A=>PRI_IN_2(1)); ix1544 : xnor2 port map ( Y=>nx1543, A0=>PRI_IN_0(2), A1=>PRI_IN_2(2)); REG_4_reg_q_2 : dff port map ( Q=>reg_4_q_c_2, QB=>OPEN, D=>nx804, CLK=> CLK); ix805 : xnor2 port map ( Y=>nx804, A0=>nx800, A1=>nx1553); ix801 : oai22 port map ( Y=>nx800, A0=>nx1411, A1=>nx1541, B0=>nx1469, B1 =>nx1505); ix1554 : xnor2 port map ( Y=>nx1553, A0=>PRI_IN_2(2), A1=>nx1531); REG_2_reg_q_3 : dff port map ( Q=>PRI_OUT_4_3_EXMPLR, QB=>OPEN, D=>nx938, CLK=>CLK); ix939 : xnor2 port map ( Y=>nx938, A0=>nx860, A1=>nx1565); ix861 : ao21 port map ( Y=>nx860, A0=>PRI_OUT_0_2_EXMPLR, A1=>PRI_IN_1(2), B0=>nx858); ix859 : nor02 port map ( Y=>nx858, A0=>nx1513, A1=>nx1517); ix1566 : xnor2 port map ( Y=>nx1565, A0=>PRI_IN_1(3), A1=> PRI_OUT_0_3_EXMPLR); ix935 : ao21 port map ( Y=>PRI_OUT_0_3_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_3, B0=>nx912); REG_1_reg_q_3 : dff port map ( Q=>reg_1_q_c_3, QB=>OPEN, D=>nx924, CLK=> CLK); ix925 : xnor2 port map ( Y=>nx924, A0=>nx920, A1=>nx1577); ix921 : oai22 port map ( Y=>nx920, A0=>nx1522, A1=>nx1527, B0=>nx1573, B1 =>nx1575); ix1574 : inv02 port map ( Y=>nx1573, A=>PRI_IN_0(2)); ix1576 : inv02 port map ( Y=>nx1575, A=>PRI_IN_4(2)); ix1578 : xnor2 port map ( Y=>nx1577, A0=>PRI_IN_4(3), A1=>PRI_IN_0(3)); ix913 : nor02 port map ( Y=>nx912, A0=>C_MUX2_3_SEL, A1=>nx1581); ix1582 : aoi222 port map ( Y=>nx1581, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_3, B0=>PRI_OUT_4_3_EXMPLR, B1=>nx2869, C0=>reg_4_q_c_3, C1=>nx2875); REG_3_reg_q_3 : dff port map ( Q=>reg_3_q_c_3, QB=>OPEN, D=>nx872, CLK=> CLK); ix873 : xnor2 port map ( Y=>nx872, A0=>nx868, A1=>nx1589); ix869 : oai22 port map ( Y=>nx868, A0=>nx1537, A1=>nx1543, B0=>nx1587, B1 =>nx1573); ix1588 : inv02 port map ( Y=>nx1587, A=>PRI_IN_2(2)); ix1590 : xnor2 port map ( Y=>nx1589, A0=>PRI_IN_0(3), A1=>PRI_IN_2(3)); REG_4_reg_q_3 : dff port map ( Q=>reg_4_q_c_3, QB=>OPEN, D=>nx896, CLK=> CLK); ix897 : xor2 port map ( Y=>nx896, A0=>nx1595, A1=>nx1599); ix1596 : aoi22 port map ( Y=>nx1595, A0=>nx1531, A1=>PRI_IN_2(2), B0=> nx800, B1=>nx802); ix1600 : xnor2 port map ( Y=>nx1599, A0=>PRI_IN_2(3), A1=>nx1581); REG_2_reg_q_4 : dff port map ( Q=>PRI_OUT_4_4_EXMPLR, QB=>OPEN, D=>nx1030, CLK=>CLK); ix1031 : xor2 port map ( Y=>nx1030, A0=>nx1607, A1=>nx1611); ix1608 : aoi22 port map ( Y=>nx1607, A0=>PRI_OUT_0_3_EXMPLR, A1=> PRI_IN_1(3), B0=>nx860, B1=>nx936); ix1612 : xnor2 port map ( Y=>nx1611, A0=>PRI_IN_1(4), A1=> PRI_OUT_0_4_EXMPLR); ix1027 : ao21 port map ( Y=>PRI_OUT_0_4_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_4, B0=>nx1004); REG_1_reg_q_4 : dff port map ( Q=>reg_1_q_c_4, QB=>nx1625, D=>nx1016, CLK =>CLK); ix1017 : xor2 port map ( Y=>nx1016, A0=>nx1617, A1=>nx1623); ix1618 : aoi22 port map ( Y=>nx1617, A0=>PRI_IN_0(3), A1=>PRI_IN_4(3), B0 =>nx920, B1=>nx922); ix1624 : xnor2 port map ( Y=>nx1623, A0=>PRI_IN_4(4), A1=>PRI_IN_0(4)); ix1005 : nor02 port map ( Y=>nx1004, A0=>C_MUX2_3_SEL, A1=>nx1627); ix1628 : aoi222 port map ( Y=>nx1627, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_4, B0=>PRI_OUT_4_4_EXMPLR, B1=>nx2869, C0=>reg_4_q_c_4, C1=>nx2875); REG_3_reg_q_4 : dff port map ( Q=>reg_3_q_c_4, QB=>OPEN, D=>nx964, CLK=> CLK); ix965 : xor2 port map ( Y=>nx964, A0=>nx1633, A1=>nx1638); ix1634 : aoi22 port map ( Y=>nx1633, A0=>PRI_IN_2(3), A1=>PRI_IN_0(3), B0 =>nx868, B1=>nx870); ix1637 : inv02 port map ( Y=>nx1636, A=>PRI_IN_2(3)); ix1639 : xnor2 port map ( Y=>nx1638, A0=>PRI_IN_0(4), A1=>PRI_IN_2(4)); REG_4_reg_q_4 : dff port map ( Q=>reg_4_q_c_4, QB=>OPEN, D=>nx988, CLK=> CLK); ix989 : xnor2 port map ( Y=>nx988, A0=>nx984, A1=>nx1649); ix985 : oai22 port map ( Y=>nx984, A0=>nx1595, A1=>nx1599, B0=>nx1414, B1 =>nx1636); ix1650 : xnor2 port map ( Y=>nx1649, A0=>PRI_IN_2(4), A1=>nx1627); REG_2_reg_q_5 : dff port map ( Q=>PRI_OUT_4_5_EXMPLR, QB=>OPEN, D=>nx1122, CLK=>CLK); ix1123 : xnor2 port map ( Y=>nx1122, A0=>nx1044, A1=>nx1661); ix1045 : ao21 port map ( Y=>nx1044, A0=>PRI_OUT_0_4_EXMPLR, A1=> PRI_IN_1(4), B0=>nx1042); ix1043 : nor02 port map ( Y=>nx1042, A0=>nx1607, A1=>nx1611); ix1662 : xnor2 port map ( Y=>nx1661, A0=>PRI_IN_1(5), A1=> PRI_OUT_0_5_EXMPLR); ix1119 : ao21 port map ( Y=>PRI_OUT_0_5_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_5, B0=>nx1096); REG_1_reg_q_5 : dff port map ( Q=>reg_1_q_c_5, QB=>OPEN, D=>nx1108, CLK=> CLK); ix1109 : xnor2 port map ( Y=>nx1108, A0=>nx1104, A1=>nx1671); ix1105 : oai22 port map ( Y=>nx1104, A0=>nx1617, A1=>nx1623, B0=>nx1667, B1=>nx1669); ix1668 : inv02 port map ( Y=>nx1667, A=>PRI_IN_0(4)); ix1670 : inv02 port map ( Y=>nx1669, A=>PRI_IN_4(4)); ix1672 : xnor2 port map ( Y=>nx1671, A0=>PRI_IN_4(5), A1=>PRI_IN_0(5)); ix1097 : nor02 port map ( Y=>nx1096, A0=>C_MUX2_3_SEL, A1=>nx1675); ix1676 : aoi222 port map ( Y=>nx1675, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_5, B0=>PRI_OUT_4_5_EXMPLR, B1=>nx2871, C0=>reg_4_q_c_5, C1=>nx2877); REG_3_reg_q_5 : dff port map ( Q=>reg_3_q_c_5, QB=>OPEN, D=>nx1056, CLK=> CLK); ix1057 : xnor2 port map ( Y=>nx1056, A0=>nx1052, A1=>nx1682); ix1053 : oai22 port map ( Y=>nx1052, A0=>nx1633, A1=>nx1638, B0=>nx1680, B1=>nx1667); ix1681 : inv02 port map ( Y=>nx1680, A=>PRI_IN_2(4)); ix1684 : xnor2 port map ( Y=>nx1682, A0=>PRI_IN_0(5), A1=>PRI_IN_2(5)); REG_4_reg_q_5 : dff port map ( Q=>reg_4_q_c_5, QB=>OPEN, D=>nx1080, CLK=> CLK); ix1081 : xor2 port map ( Y=>nx1080, A0=>nx1689, A1=>nx1693); ix1690 : aoi22 port map ( Y=>nx1689, A0=>nx1627, A1=>PRI_IN_2(4), B0=> nx984, B1=>nx986); ix1694 : xnor2 port map ( Y=>nx1693, A0=>PRI_IN_2(5), A1=>nx1675); REG_2_reg_q_6 : dff port map ( Q=>PRI_OUT_4_6_EXMPLR, QB=>OPEN, D=>nx1214, CLK=>CLK); ix1215 : xor2 port map ( Y=>nx1214, A0=>nx1701, A1=>nx1704); ix1702 : aoi22 port map ( Y=>nx1701, A0=>PRI_OUT_0_5_EXMPLR, A1=> PRI_IN_1(5), B0=>nx1044, B1=>nx1120); ix1705 : xnor2 port map ( Y=>nx1704, A0=>PRI_IN_1(6), A1=> PRI_OUT_0_6_EXMPLR); ix1211 : ao21 port map ( Y=>PRI_OUT_0_6_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_6, B0=>nx1188); REG_1_reg_q_6 : dff port map ( Q=>reg_1_q_c_6, QB=>nx1717, D=>nx1200, CLK =>CLK); ix1201 : xor2 port map ( Y=>nx1200, A0=>nx1709, A1=>nx1715); ix1710 : aoi22 port map ( Y=>nx1709, A0=>PRI_IN_0(5), A1=>PRI_IN_4(5), B0 =>nx1104, B1=>nx1106); ix1716 : xnor2 port map ( Y=>nx1715, A0=>PRI_IN_4(6), A1=>PRI_IN_0(6)); ix1189 : nor02 port map ( Y=>nx1188, A0=>C_MUX2_3_SEL, A1=>nx1719); ix1720 : aoi222 port map ( Y=>nx1719, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_6, B0=>PRI_OUT_4_6_EXMPLR, B1=>nx2871, C0=>reg_4_q_c_6, C1=>nx2877); REG_3_reg_q_6 : dff port map ( Q=>reg_3_q_c_6, QB=>OPEN, D=>nx1148, CLK=> CLK); ix1149 : xor2 port map ( Y=>nx1148, A0=>nx1725, A1=>nx1730); ix1726 : aoi22 port map ( Y=>nx1725, A0=>PRI_IN_2(5), A1=>PRI_IN_0(5), B0 =>nx1052, B1=>nx1054); ix1729 : inv02 port map ( Y=>nx1728, A=>PRI_IN_2(5)); ix1731 : xnor2 port map ( Y=>nx1730, A0=>PRI_IN_0(6), A1=>PRI_IN_2(6)); REG_4_reg_q_6 : dff port map ( Q=>reg_4_q_c_6, QB=>OPEN, D=>nx1172, CLK=> CLK); ix1173 : xnor2 port map ( Y=>nx1172, A0=>nx1168, A1=>nx1741); ix1169 : oai22 port map ( Y=>nx1168, A0=>nx1689, A1=>nx1693, B0=>nx1417, B1=>nx1728); ix1742 : xnor2 port map ( Y=>nx1741, A0=>PRI_IN_2(6), A1=>nx1719); REG_2_reg_q_7 : dff port map ( Q=>PRI_OUT_4_7_EXMPLR, QB=>OPEN, D=>nx1306, CLK=>CLK); ix1307 : xnor2 port map ( Y=>nx1306, A0=>nx1228, A1=>nx1753); ix1229 : ao21 port map ( Y=>nx1228, A0=>PRI_OUT_0_6_EXMPLR, A1=> PRI_IN_1(6), B0=>nx1226); ix1227 : nor02 port map ( Y=>nx1226, A0=>nx1701, A1=>nx1704); ix1754 : xnor2 port map ( Y=>nx1753, A0=>PRI_IN_1(7), A1=> PRI_OUT_0_7_EXMPLR); ix1303 : ao21 port map ( Y=>PRI_OUT_0_7_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_7, B0=>nx1280); REG_1_reg_q_7 : dff port map ( Q=>reg_1_q_c_7, QB=>OPEN, D=>nx1292, CLK=> CLK); ix1293 : xnor2 port map ( Y=>nx1292, A0=>nx1288, A1=>nx1763); ix1289 : oai22 port map ( Y=>nx1288, A0=>nx1709, A1=>nx1715, B0=>nx1759, B1=>nx1761); ix1760 : inv02 port map ( Y=>nx1759, A=>PRI_IN_0(6)); ix1762 : inv02 port map ( Y=>nx1761, A=>PRI_IN_4(6)); ix1764 : xnor2 port map ( Y=>nx1763, A0=>PRI_IN_4(7), A1=>PRI_IN_0(7)); ix1281 : nor02 port map ( Y=>nx1280, A0=>C_MUX2_3_SEL, A1=>nx1767); ix1768 : aoi222 port map ( Y=>nx1767, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_7, B0=>PRI_OUT_4_7_EXMPLR, B1=>nx2871, C0=>reg_4_q_c_7, C1=>nx2877); REG_3_reg_q_7 : dff port map ( Q=>reg_3_q_c_7, QB=>OPEN, D=>nx1240, CLK=> CLK); ix1241 : xnor2 port map ( Y=>nx1240, A0=>nx1236, A1=>nx1774); ix1237 : oai22 port map ( Y=>nx1236, A0=>nx1725, A1=>nx1730, B0=>nx1772, B1=>nx1759); ix1773 : inv02 port map ( Y=>nx1772, A=>PRI_IN_2(6)); ix1776 : xnor2 port map ( Y=>nx1774, A0=>PRI_IN_0(7), A1=>PRI_IN_2(7)); REG_4_reg_q_7 : dff port map ( Q=>reg_4_q_c_7, QB=>OPEN, D=>nx1264, CLK=> CLK); ix1265 : xor2 port map ( Y=>nx1264, A0=>nx1781, A1=>nx1785); ix1782 : aoi22 port map ( Y=>nx1781, A0=>nx1719, A1=>PRI_IN_2(6), B0=> nx1168, B1=>nx1170); ix1786 : xnor2 port map ( Y=>nx1785, A0=>PRI_IN_2(7), A1=>nx1767); REG_2_reg_q_8 : dff port map ( Q=>PRI_OUT_4_8_EXMPLR, QB=>OPEN, D=>nx1398, CLK=>CLK); ix1399 : xor2 port map ( Y=>nx1398, A0=>nx1793, A1=>nx1796); ix1794 : aoi22 port map ( Y=>nx1793, A0=>PRI_OUT_0_7_EXMPLR, A1=> PRI_IN_1(7), B0=>nx1228, B1=>nx1304); ix1797 : xnor2 port map ( Y=>nx1796, A0=>PRI_IN_1(8), A1=> PRI_OUT_0_8_EXMPLR); ix1395 : ao21 port map ( Y=>PRI_OUT_0_8_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_8, B0=>nx1372); REG_1_reg_q_8 : dff port map ( Q=>reg_1_q_c_8, QB=>nx1809, D=>nx1384, CLK =>CLK); ix1385 : xor2 port map ( Y=>nx1384, A0=>nx1801, A1=>nx1807); ix1802 : aoi22 port map ( Y=>nx1801, A0=>PRI_IN_0(7), A1=>PRI_IN_4(7), B0 =>nx1288, B1=>nx1290); ix1808 : xnor2 port map ( Y=>nx1807, A0=>PRI_IN_4(8), A1=>PRI_IN_0(8)); ix1373 : nor02 port map ( Y=>nx1372, A0=>C_MUX2_3_SEL, A1=>nx1811); ix1812 : aoi222 port map ( Y=>nx1811, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_8, B0=>PRI_OUT_4_8_EXMPLR, B1=>nx2871, C0=>reg_4_q_c_8, C1=>nx2877); REG_3_reg_q_8 : dff port map ( Q=>reg_3_q_c_8, QB=>OPEN, D=>nx1332, CLK=> CLK); ix1333 : xor2 port map ( Y=>nx1332, A0=>nx1817, A1=>nx1822); ix1818 : aoi22 port map ( Y=>nx1817, A0=>PRI_IN_2(7), A1=>PRI_IN_0(7), B0 =>nx1236, B1=>nx1238); ix1821 : inv02 port map ( Y=>nx1820, A=>PRI_IN_2(7)); ix1823 : xnor2 port map ( Y=>nx1822, A0=>PRI_IN_0(8), A1=>PRI_IN_2(8)); REG_4_reg_q_8 : dff port map ( Q=>reg_4_q_c_8, QB=>OPEN, D=>nx1356, CLK=> CLK); ix1357 : xnor2 port map ( Y=>nx1356, A0=>nx1352, A1=>nx1833); ix1353 : oai22 port map ( Y=>nx1352, A0=>nx1781, A1=>nx1785, B0=>nx1421, B1=>nx1820); ix1834 : xnor2 port map ( Y=>nx1833, A0=>PRI_IN_2(8), A1=>nx1811); REG_2_reg_q_9 : dff port map ( Q=>PRI_OUT_4_9_EXMPLR, QB=>OPEN, D=>nx1490, CLK=>CLK); ix1491 : xnor2 port map ( Y=>nx1490, A0=>nx1412, A1=>nx1845); ix1413 : ao21 port map ( Y=>nx1412, A0=>PRI_OUT_0_8_EXMPLR, A1=> PRI_IN_1(8), B0=>nx1410); ix1411 : nor02 port map ( Y=>nx1410, A0=>nx1793, A1=>nx1796); ix1846 : xnor2 port map ( Y=>nx1845, A0=>PRI_IN_1(9), A1=> PRI_OUT_0_9_EXMPLR); ix1487 : ao21 port map ( Y=>PRI_OUT_0_9_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_9, B0=>nx1464); REG_1_reg_q_9 : dff port map ( Q=>reg_1_q_c_9, QB=>OPEN, D=>nx1476, CLK=> CLK); ix1477 : xnor2 port map ( Y=>nx1476, A0=>nx1472, A1=>nx1855); ix1473 : oai22 port map ( Y=>nx1472, A0=>nx1801, A1=>nx1807, B0=>nx1851, B1=>nx1853); ix1852 : inv02 port map ( Y=>nx1851, A=>PRI_IN_0(8)); ix1854 : inv02 port map ( Y=>nx1853, A=>PRI_IN_4(8)); ix1856 : xnor2 port map ( Y=>nx1855, A0=>PRI_IN_4(9), A1=>PRI_IN_0(9)); ix1465 : nor02 port map ( Y=>nx1464, A0=>C_MUX2_3_SEL, A1=>nx1859); ix1860 : aoi222 port map ( Y=>nx1859, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_9, B0=>PRI_OUT_4_9_EXMPLR, B1=>nx2871, C0=>reg_4_q_c_9, C1=>nx2877); REG_3_reg_q_9 : dff port map ( Q=>reg_3_q_c_9, QB=>OPEN, D=>nx1424, CLK=> CLK); ix1425 : xnor2 port map ( Y=>nx1424, A0=>nx1420, A1=>nx1866); ix1421 : oai22 port map ( Y=>nx1420, A0=>nx1817, A1=>nx1822, B0=>nx1864, B1=>nx1851); ix1865 : inv02 port map ( Y=>nx1864, A=>PRI_IN_2(8)); ix1868 : xnor2 port map ( Y=>nx1866, A0=>PRI_IN_0(9), A1=>PRI_IN_2(9)); REG_4_reg_q_9 : dff port map ( Q=>reg_4_q_c_9, QB=>OPEN, D=>nx1448, CLK=> CLK); ix1449 : xor2 port map ( Y=>nx1448, A0=>nx1873, A1=>nx1877); ix1874 : aoi22 port map ( Y=>nx1873, A0=>nx1811, A1=>PRI_IN_2(8), B0=> nx1352, B1=>nx1354); ix1878 : xnor2 port map ( Y=>nx1877, A0=>PRI_IN_2(9), A1=>nx1859); REG_2_reg_q_10 : dff port map ( Q=>PRI_OUT_4_10_EXMPLR, QB=>OPEN, D=> nx1582, CLK=>CLK); ix1583 : xor2 port map ( Y=>nx1582, A0=>nx1885, A1=>nx1888); ix1886 : aoi22 port map ( Y=>nx1885, A0=>PRI_OUT_0_9_EXMPLR, A1=> PRI_IN_1(9), B0=>nx1412, B1=>nx1488); ix1889 : xnor2 port map ( Y=>nx1888, A0=>PRI_IN_1(10), A1=> PRI_OUT_0_10_EXMPLR); ix1579 : ao21 port map ( Y=>PRI_OUT_0_10_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_10, B0=>nx1556); REG_1_reg_q_10 : dff port map ( Q=>reg_1_q_c_10, QB=>nx1901, D=>nx1568, CLK=>CLK); ix1569 : xor2 port map ( Y=>nx1568, A0=>nx1893, A1=>nx1899); ix1894 : aoi22 port map ( Y=>nx1893, A0=>PRI_IN_0(9), A1=>PRI_IN_4(9), B0 =>nx1472, B1=>nx1474); ix1900 : xnor2 port map ( Y=>nx1899, A0=>PRI_IN_4(10), A1=>PRI_IN_0(10)); ix1557 : nor02 port map ( Y=>nx1556, A0=>C_MUX2_3_SEL, A1=>nx1903); ix1904 : aoi222 port map ( Y=>nx1903, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_10, B0=>PRI_OUT_4_10_EXMPLR, B1=>nx2873, C0=>reg_4_q_c_10, C1=>nx2879); REG_3_reg_q_10 : dff port map ( Q=>reg_3_q_c_10, QB=>OPEN, D=>nx1516, CLK =>CLK); ix1517 : xor2 port map ( Y=>nx1516, A0=>nx1909, A1=>nx1914); ix1910 : aoi22 port map ( Y=>nx1909, A0=>PRI_IN_2(9), A1=>PRI_IN_0(9), B0 =>nx1420, B1=>nx1422); ix1913 : inv02 port map ( Y=>nx1912, A=>PRI_IN_2(9)); ix1915 : xnor2 port map ( Y=>nx1914, A0=>PRI_IN_0(10), A1=>PRI_IN_2(10)); REG_4_reg_q_10 : dff port map ( Q=>reg_4_q_c_10, QB=>OPEN, D=>nx1540, CLK =>CLK); ix1541 : xnor2 port map ( Y=>nx1540, A0=>nx1536, A1=>nx1925); ix1537 : oai22 port map ( Y=>nx1536, A0=>nx1873, A1=>nx1877, B0=>nx1425, B1=>nx1912); ix1926 : xnor2 port map ( Y=>nx1925, A0=>PRI_IN_2(10), A1=>nx1903); REG_2_reg_q_11 : dff port map ( Q=>PRI_OUT_4_11_EXMPLR, QB=>OPEN, D=> nx1674, CLK=>CLK); ix1675 : xnor2 port map ( Y=>nx1674, A0=>nx1596, A1=>nx1937); ix1597 : ao21 port map ( Y=>nx1596, A0=>PRI_OUT_0_10_EXMPLR, A1=> PRI_IN_1(10), B0=>nx1594); ix1595 : nor02 port map ( Y=>nx1594, A0=>nx1885, A1=>nx1888); ix1938 : xnor2 port map ( Y=>nx1937, A0=>PRI_IN_1(11), A1=> PRI_OUT_0_11_EXMPLR); ix1671 : ao21 port map ( Y=>PRI_OUT_0_11_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_11, B0=>nx1648); REG_1_reg_q_11 : dff port map ( Q=>reg_1_q_c_11, QB=>OPEN, D=>nx1660, CLK =>CLK); ix1661 : xnor2 port map ( Y=>nx1660, A0=>nx1656, A1=>nx1947); ix1657 : oai22 port map ( Y=>nx1656, A0=>nx1893, A1=>nx1899, B0=>nx1943, B1=>nx1945); ix1944 : inv02 port map ( Y=>nx1943, A=>PRI_IN_0(10)); ix1946 : inv02 port map ( Y=>nx1945, A=>PRI_IN_4(10)); ix1948 : xnor2 port map ( Y=>nx1947, A0=>PRI_IN_4(11), A1=>PRI_IN_0(11)); ix1649 : nor02 port map ( Y=>nx1648, A0=>C_MUX2_3_SEL, A1=>nx1951); ix1952 : aoi222 port map ( Y=>nx1951, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_11, B0=>PRI_OUT_4_11_EXMPLR, B1=>nx2873, C0=>reg_4_q_c_11, C1=>nx2879); REG_3_reg_q_11 : dff port map ( Q=>reg_3_q_c_11, QB=>OPEN, D=>nx1608, CLK =>CLK); ix1609 : xnor2 port map ( Y=>nx1608, A0=>nx1604, A1=>nx1958); ix1605 : oai22 port map ( Y=>nx1604, A0=>nx1909, A1=>nx1914, B0=>nx1956, B1=>nx1943); ix1957 : inv02 port map ( Y=>nx1956, A=>PRI_IN_2(10)); ix1960 : xnor2 port map ( Y=>nx1958, A0=>PRI_IN_0(11), A1=>PRI_IN_2(11)); REG_4_reg_q_11 : dff port map ( Q=>reg_4_q_c_11, QB=>OPEN, D=>nx1632, CLK =>CLK); ix1633 : xor2 port map ( Y=>nx1632, A0=>nx1965, A1=>nx1969); ix1966 : aoi22 port map ( Y=>nx1965, A0=>nx1903, A1=>PRI_IN_2(10), B0=> nx1536, B1=>nx1538); ix1970 : xnor2 port map ( Y=>nx1969, A0=>PRI_IN_2(11), A1=>nx1951); REG_2_reg_q_12 : dff port map ( Q=>PRI_OUT_4_12_EXMPLR, QB=>OPEN, D=> nx1766, CLK=>CLK); ix1767 : xor2 port map ( Y=>nx1766, A0=>nx1977, A1=>nx1980); ix1978 : aoi22 port map ( Y=>nx1977, A0=>PRI_OUT_0_11_EXMPLR, A1=> PRI_IN_1(11), B0=>nx1596, B1=>nx1672); ix1981 : xnor2 port map ( Y=>nx1980, A0=>PRI_IN_1(12), A1=> PRI_OUT_0_12_EXMPLR); ix1763 : ao21 port map ( Y=>PRI_OUT_0_12_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_12, B0=>nx1740); REG_1_reg_q_12 : dff port map ( Q=>reg_1_q_c_12, QB=>nx1993, D=>nx1752, CLK=>CLK); ix1753 : xor2 port map ( Y=>nx1752, A0=>nx1985, A1=>nx1991); ix1986 : aoi22 port map ( Y=>nx1985, A0=>PRI_IN_0(11), A1=>PRI_IN_4(11), B0=>nx1656, B1=>nx1658); ix1992 : xnor2 port map ( Y=>nx1991, A0=>PRI_IN_4(12), A1=>PRI_IN_0(12)); ix1741 : nor02 port map ( Y=>nx1740, A0=>C_MUX2_3_SEL, A1=>nx1995); ix1996 : aoi222 port map ( Y=>nx1995, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_12, B0=>PRI_OUT_4_12_EXMPLR, B1=>nx2873, C0=>reg_4_q_c_12, C1=>nx2879); REG_3_reg_q_12 : dff port map ( Q=>reg_3_q_c_12, QB=>OPEN, D=>nx1700, CLK =>CLK); ix1701 : xor2 port map ( Y=>nx1700, A0=>nx2001, A1=>nx2006); ix2002 : aoi22 port map ( Y=>nx2001, A0=>PRI_IN_2(11), A1=>PRI_IN_0(11), B0=>nx1604, B1=>nx1606); ix2005 : inv02 port map ( Y=>nx2004, A=>PRI_IN_2(11)); ix2007 : xnor2 port map ( Y=>nx2006, A0=>PRI_IN_0(12), A1=>PRI_IN_2(12)); REG_4_reg_q_12 : dff port map ( Q=>reg_4_q_c_12, QB=>OPEN, D=>nx1724, CLK =>CLK); ix1725 : xnor2 port map ( Y=>nx1724, A0=>nx1720, A1=>nx2017); ix1721 : oai22 port map ( Y=>nx1720, A0=>nx1965, A1=>nx1969, B0=>nx1427, B1=>nx2004); ix2018 : xnor2 port map ( Y=>nx2017, A0=>PRI_IN_2(12), A1=>nx1995); REG_2_reg_q_13 : dff port map ( Q=>PRI_OUT_4_13_EXMPLR, QB=>OPEN, D=> nx1858, CLK=>CLK); ix1859 : xnor2 port map ( Y=>nx1858, A0=>nx1780, A1=>nx2029); ix1781 : ao21 port map ( Y=>nx1780, A0=>PRI_OUT_0_12_EXMPLR, A1=> PRI_IN_1(12), B0=>nx1778); ix1779 : nor02 port map ( Y=>nx1778, A0=>nx1977, A1=>nx1980); ix2030 : xnor2 port map ( Y=>nx2029, A0=>PRI_IN_1(13), A1=> PRI_OUT_0_13_EXMPLR); ix1855 : ao21 port map ( Y=>PRI_OUT_0_13_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_13, B0=>nx1832); REG_1_reg_q_13 : dff port map ( Q=>reg_1_q_c_13, QB=>OPEN, D=>nx1844, CLK =>CLK); ix1845 : xnor2 port map ( Y=>nx1844, A0=>nx1840, A1=>nx2039); ix1841 : oai22 port map ( Y=>nx1840, A0=>nx1985, A1=>nx1991, B0=>nx2035, B1=>nx2037); ix2036 : inv02 port map ( Y=>nx2035, A=>PRI_IN_0(12)); ix2038 : inv02 port map ( Y=>nx2037, A=>PRI_IN_4(12)); ix2040 : xnor2 port map ( Y=>nx2039, A0=>PRI_IN_4(13), A1=>PRI_IN_0(13)); ix1833 : nor02 port map ( Y=>nx1832, A0=>C_MUX2_3_SEL, A1=>nx2043); ix2044 : aoi222 port map ( Y=>nx2043, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_13, B0=>PRI_OUT_4_13_EXMPLR, B1=>nx2873, C0=>reg_4_q_c_13, C1=>nx2879); REG_3_reg_q_13 : dff port map ( Q=>reg_3_q_c_13, QB=>OPEN, D=>nx1792, CLK =>CLK); ix1793 : xnor2 port map ( Y=>nx1792, A0=>nx1788, A1=>nx2051); ix1789 : oai22 port map ( Y=>nx1788, A0=>nx2001, A1=>nx2006, B0=>nx2048, B1=>nx2035); ix2049 : inv02 port map ( Y=>nx2048, A=>PRI_IN_2(12)); ix2052 : xnor2 port map ( Y=>nx2051, A0=>PRI_IN_0(13), A1=>PRI_IN_2(13)); REG_4_reg_q_13 : dff port map ( Q=>reg_4_q_c_13, QB=>OPEN, D=>nx1816, CLK =>CLK); ix1817 : xor2 port map ( Y=>nx1816, A0=>nx2057, A1=>nx2060); ix2058 : aoi22 port map ( Y=>nx2057, A0=>nx1995, A1=>PRI_IN_2(12), B0=> nx1720, B1=>nx1722); ix2061 : xnor2 port map ( Y=>nx2060, A0=>PRI_IN_2(13), A1=>nx2043); REG_2_reg_q_14 : dff port map ( Q=>PRI_OUT_4_14_EXMPLR, QB=>OPEN, D=> nx1950, CLK=>CLK); ix1951 : xor2 port map ( Y=>nx1950, A0=>nx2067, A1=>nx2071); ix2068 : aoi22 port map ( Y=>nx2067, A0=>PRI_OUT_0_13_EXMPLR, A1=> PRI_IN_1(13), B0=>nx1780, B1=>nx1856); ix2072 : xnor2 port map ( Y=>nx2071, A0=>PRI_IN_1(14), A1=> PRI_OUT_0_14_EXMPLR); ix1947 : ao21 port map ( Y=>PRI_OUT_0_14_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_14, B0=>nx1924); REG_1_reg_q_14 : dff port map ( Q=>reg_1_q_c_14, QB=>nx2085, D=>nx1936, CLK=>CLK); ix1937 : xor2 port map ( Y=>nx1936, A0=>nx2078, A1=>nx2083); ix2079 : aoi22 port map ( Y=>nx2078, A0=>PRI_IN_0(13), A1=>PRI_IN_4(13), B0=>nx1840, B1=>nx1842); ix2084 : xnor2 port map ( Y=>nx2083, A0=>PRI_IN_4(14), A1=>PRI_IN_0(14)); ix1925 : nor02 port map ( Y=>nx1924, A0=>C_MUX2_3_SEL, A1=>nx2087); ix2088 : aoi222 port map ( Y=>nx2087, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_14, B0=>PRI_OUT_4_14_EXMPLR, B1=>nx2873, C0=>reg_4_q_c_14, C1=>nx2879); REG_3_reg_q_14 : dff port map ( Q=>reg_3_q_c_14, QB=>OPEN, D=>nx1884, CLK =>CLK); ix1885 : xor2 port map ( Y=>nx1884, A0=>nx2093, A1=>nx2099); ix2094 : aoi22 port map ( Y=>nx2093, A0=>PRI_IN_2(13), A1=>PRI_IN_0(13), B0=>nx1788, B1=>nx1790); ix2098 : inv02 port map ( Y=>nx2097, A=>PRI_IN_2(13)); ix2100 : xnor2 port map ( Y=>nx2099, A0=>PRI_IN_0(14), A1=>PRI_IN_2(14)); REG_4_reg_q_14 : dff port map ( Q=>reg_4_q_c_14, QB=>OPEN, D=>nx1908, CLK =>CLK); ix1909 : xnor2 port map ( Y=>nx1908, A0=>nx1904, A1=>nx2107); ix1905 : oai22 port map ( Y=>nx1904, A0=>nx2057, A1=>nx2060, B0=>nx1429, B1=>nx2097); ix2108 : xnor2 port map ( Y=>nx2107, A0=>PRI_IN_2(14), A1=>nx2087); REG_2_reg_q_15 : dff port map ( Q=>PRI_OUT_4_15_EXMPLR, QB=>OPEN, D=> nx2042, CLK=>CLK); ix2043 : xnor2 port map ( Y=>nx2042, A0=>nx1964, A1=>nx2119); ix1965 : ao21 port map ( Y=>nx1964, A0=>PRI_OUT_0_14_EXMPLR, A1=> PRI_IN_1(14), B0=>nx1962); ix1963 : nor02 port map ( Y=>nx1962, A0=>nx2067, A1=>nx2071); ix2120 : xnor2 port map ( Y=>nx2119, A0=>PRI_IN_1(15), A1=> PRI_OUT_0_15_EXMPLR); ix2039 : ao21 port map ( Y=>PRI_OUT_0_15_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_1_q_c_15, B0=>nx2016); REG_1_reg_q_15 : dff port map ( Q=>reg_1_q_c_15, QB=>OPEN, D=>nx2028, CLK =>CLK); ix2029 : xnor2 port map ( Y=>nx2028, A0=>nx2024, A1=>nx2131); ix2025 : oai22 port map ( Y=>nx2024, A0=>nx2078, A1=>nx2083, B0=>nx2127, B1=>nx2129); ix2128 : inv02 port map ( Y=>nx2127, A=>PRI_IN_0(14)); ix2130 : inv02 port map ( Y=>nx2129, A=>PRI_IN_4(14)); ix2132 : xnor2 port map ( Y=>nx2131, A0=>PRI_IN_4(15), A1=>PRI_IN_0(15)); ix2017 : nor02 port map ( Y=>nx2016, A0=>C_MUX2_3_SEL, A1=>nx2135); ix2136 : aoi222 port map ( Y=>nx2135, A0=>C_MUX2_1_SEL, A1=>reg_3_q_c_15, B0=>PRI_OUT_4_15_EXMPLR, B1=>nx636, C0=>reg_4_q_c_15, C1=>nx660); REG_3_reg_q_15 : dff port map ( Q=>reg_3_q_c_15, QB=>OPEN, D=>nx1976, CLK =>CLK); ix1977 : xnor2 port map ( Y=>nx1976, A0=>nx1972, A1=>nx2143); ix1973 : oai22 port map ( Y=>nx1972, A0=>nx2093, A1=>nx2099, B0=>nx2141, B1=>nx2127); ix2142 : inv02 port map ( Y=>nx2141, A=>PRI_IN_2(14)); ix2144 : xnor2 port map ( Y=>nx2143, A0=>PRI_IN_0(15), A1=>PRI_IN_2(15)); REG_4_reg_q_15 : dff port map ( Q=>reg_4_q_c_15, QB=>OPEN, D=>nx2000, CLK =>CLK); ix2001 : xnor2 port map ( Y=>nx2000, A0=>nx2149, A1=>nx1998); ix2150 : aoi22 port map ( Y=>nx2149, A0=>nx2087, A1=>PRI_IN_2(14), B0=> nx1904, B1=>nx1906); ix1999 : xor2 port map ( Y=>nx1998, A0=>PRI_IN_2(15), A1=>nx2135); REG_9_reg_q_0 : dff port map ( Q=>PRI_OUT_3(0), QB=>OPEN, D=>nx10, CLK=> CLK); ix11 : ao21 port map ( Y=>nx10, A0=>PRI_IN_1(0), A1=>nx1461, B0=>nx2159); ix2160 : nor02 port map ( Y=>nx2159, A0=>nx1461, A1=>PRI_IN_1(0)); REG_9_reg_q_1 : dff port map ( Q=>PRI_OUT_3(1), QB=>OPEN, D=>nx20, CLK=> CLK); ix21 : xnor2 port map ( Y=>nx20, A0=>nx2159, A1=>nx18); ix19 : xnor2 port map ( Y=>nx18, A0=>PRI_IN_1(1), A1=>PRI_IN_2(1)); REG_9_reg_q_2 : dff port map ( Q=>PRI_OUT_3(2), QB=>OPEN, D=>nx40, CLK=> CLK); ix41 : xnor2 port map ( Y=>nx40, A0=>nx2171, A1=>nx38); ix2172 : aoi22 port map ( Y=>nx2171, A0=>nx1541, A1=>PRI_IN_1(1), B0=>nx2, B1=>nx18); ix39 : xnor2 port map ( Y=>nx38, A0=>PRI_IN_1(2), A1=>PRI_IN_2(2)); REG_9_reg_q_3 : dff port map ( Q=>PRI_OUT_3(3), QB=>OPEN, D=>nx60, CLK=> CLK); ix61 : xor2 port map ( Y=>nx60, A0=>nx56, A1=>nx58); ix57 : mux21 port map ( Y=>nx56, A0=>PRI_IN_2(2), A1=>nx2171, S0=>nx38); ix59 : xnor2 port map ( Y=>nx58, A0=>PRI_IN_1(3), A1=>PRI_IN_2(3)); REG_9_reg_q_4 : dff port map ( Q=>PRI_OUT_3(4), QB=>OPEN, D=>nx80, CLK=> CLK); ix81 : xnor2 port map ( Y=>nx80, A0=>nx2189, A1=>nx78); ix2190 : aoi22 port map ( Y=>nx2189, A0=>nx1636, A1=>PRI_IN_1(3), B0=> nx56, B1=>nx58); ix79 : xnor2 port map ( Y=>nx78, A0=>PRI_IN_1(4), A1=>PRI_IN_2(4)); REG_9_reg_q_5 : dff port map ( Q=>PRI_OUT_3(5), QB=>OPEN, D=>nx100, CLK=> CLK); ix101 : xor2 port map ( Y=>nx100, A0=>nx96, A1=>nx98); ix97 : mux21 port map ( Y=>nx96, A0=>PRI_IN_2(4), A1=>nx2189, S0=>nx78); ix99 : xnor2 port map ( Y=>nx98, A0=>PRI_IN_1(5), A1=>PRI_IN_2(5)); REG_9_reg_q_6 : dff port map ( Q=>PRI_OUT_3(6), QB=>OPEN, D=>nx120, CLK=> CLK); ix121 : xnor2 port map ( Y=>nx120, A0=>nx2203, A1=>nx118); ix2204 : aoi22 port map ( Y=>nx2203, A0=>nx1728, A1=>PRI_IN_1(5), B0=> nx96, B1=>nx98); ix119 : xnor2 port map ( Y=>nx118, A0=>PRI_IN_1(6), A1=>PRI_IN_2(6)); REG_9_reg_q_7 : dff port map ( Q=>PRI_OUT_3(7), QB=>OPEN, D=>nx140, CLK=> CLK); ix141 : xor2 port map ( Y=>nx140, A0=>nx136, A1=>nx138); ix137 : mux21 port map ( Y=>nx136, A0=>PRI_IN_2(6), A1=>nx2203, S0=>nx118 ); ix139 : xnor2 port map ( Y=>nx138, A0=>PRI_IN_1(7), A1=>PRI_IN_2(7)); REG_9_reg_q_8 : dff port map ( Q=>PRI_OUT_3(8), QB=>OPEN, D=>nx160, CLK=> CLK); ix161 : xnor2 port map ( Y=>nx160, A0=>nx2218, A1=>nx158); ix2219 : aoi22 port map ( Y=>nx2218, A0=>nx1820, A1=>PRI_IN_1(7), B0=> nx136, B1=>nx138); ix159 : xnor2 port map ( Y=>nx158, A0=>PRI_IN_1(8), A1=>PRI_IN_2(8)); REG_9_reg_q_9 : dff port map ( Q=>PRI_OUT_3(9), QB=>OPEN, D=>nx180, CLK=> CLK); ix181 : xor2 port map ( Y=>nx180, A0=>nx176, A1=>nx178); ix177 : mux21 port map ( Y=>nx176, A0=>PRI_IN_2(8), A1=>nx2218, S0=>nx158 ); ix179 : xnor2 port map ( Y=>nx178, A0=>PRI_IN_1(9), A1=>PRI_IN_2(9)); REG_9_reg_q_10 : dff port map ( Q=>PRI_OUT_3(10), QB=>OPEN, D=>nx200, CLK =>CLK); ix201 : xnor2 port map ( Y=>nx200, A0=>nx2233, A1=>nx198); ix2234 : aoi22 port map ( Y=>nx2233, A0=>nx1912, A1=>PRI_IN_1(9), B0=> nx176, B1=>nx178); ix199 : xnor2 port map ( Y=>nx198, A0=>PRI_IN_1(10), A1=>PRI_IN_2(10)); REG_9_reg_q_11 : dff port map ( Q=>PRI_OUT_3(11), QB=>OPEN, D=>nx220, CLK =>CLK); ix221 : xor2 port map ( Y=>nx220, A0=>nx216, A1=>nx218); ix217 : mux21 port map ( Y=>nx216, A0=>PRI_IN_2(10), A1=>nx2233, S0=> nx198); ix219 : xnor2 port map ( Y=>nx218, A0=>PRI_IN_1(11), A1=>PRI_IN_2(11)); REG_9_reg_q_12 : dff port map ( Q=>PRI_OUT_3(12), QB=>OPEN, D=>nx240, CLK =>CLK); ix241 : xnor2 port map ( Y=>nx240, A0=>nx2249, A1=>nx238); ix2250 : aoi22 port map ( Y=>nx2249, A0=>nx2004, A1=>PRI_IN_1(11), B0=> nx216, B1=>nx218); ix239 : xnor2 port map ( Y=>nx238, A0=>PRI_IN_1(12), A1=>PRI_IN_2(12)); REG_9_reg_q_13 : dff port map ( Q=>PRI_OUT_3(13), QB=>OPEN, D=>nx260, CLK =>CLK); ix261 : xor2 port map ( Y=>nx260, A0=>nx256, A1=>nx258); ix257 : mux21 port map ( Y=>nx256, A0=>PRI_IN_2(12), A1=>nx2249, S0=> nx238); ix259 : xnor2 port map ( Y=>nx258, A0=>PRI_IN_1(13), A1=>PRI_IN_2(13)); REG_9_reg_q_14 : dff port map ( Q=>PRI_OUT_3(14), QB=>OPEN, D=>nx280, CLK =>CLK); ix281 : xnor2 port map ( Y=>nx280, A0=>nx2261, A1=>nx278); ix2262 : aoi22 port map ( Y=>nx2261, A0=>nx2097, A1=>PRI_IN_1(13), B0=> nx256, B1=>nx258); ix279 : xnor2 port map ( Y=>nx278, A0=>PRI_IN_1(14), A1=>PRI_IN_2(14)); REG_9_reg_q_15 : dff port map ( Q=>PRI_OUT_3(15), QB=>OPEN, D=>nx300, CLK =>CLK); ix301 : xnor2 port map ( Y=>nx300, A0=>nx296, A1=>nx2269); ix297 : mux21 port map ( Y=>nx296, A0=>PRI_IN_2(14), A1=>nx2261, S0=> nx278); ix2270 : xor2 port map ( Y=>nx2269, A0=>PRI_IN_1(15), A1=>PRI_IN_2(15)); REG_8_reg_q_0 : dff port map ( Q=>PRI_OUT_2(0), QB=>OPEN, D=>nx318, CLK=> CLK); ix319 : oai21 port map ( Y=>nx318, A0=>PRI_IN_4(0), A1=>nx2275, B0=>nx310 ); ix2276 : inv02 port map ( Y=>nx2275, A=>PRI_IN_3(0)); ix311 : nand02 port map ( Y=>nx310, A0=>nx2275, A1=>PRI_IN_4(0)); REG_8_reg_q_1 : dff port map ( Q=>PRI_OUT_2(1), QB=>OPEN, D=>nx328, CLK=> CLK); ix329 : xor2 port map ( Y=>nx328, A0=>nx310, A1=>nx326); ix327 : xnor2 port map ( Y=>nx326, A0=>PRI_IN_4(1), A1=>PRI_IN_3(1)); REG_8_reg_q_2 : dff port map ( Q=>PRI_OUT_2(2), QB=>OPEN, D=>nx348, CLK=> CLK); ix349 : xnor2 port map ( Y=>nx348, A0=>nx2288, A1=>nx346); ix2289 : aoi22 port map ( Y=>nx2288, A0=>nx2291, A1=>PRI_IN_3(1), B0=> nx310, B1=>nx326); ix2292 : inv02 port map ( Y=>nx2291, A=>PRI_IN_4(1)); ix347 : xnor2 port map ( Y=>nx346, A0=>PRI_IN_4(2), A1=>PRI_IN_3(2)); REG_8_reg_q_3 : dff port map ( Q=>PRI_OUT_2(3), QB=>OPEN, D=>nx368, CLK=> CLK); ix369 : xor2 port map ( Y=>nx368, A0=>nx364, A1=>nx366); ix365 : mux21 port map ( Y=>nx364, A0=>PRI_IN_4(2), A1=>nx2288, S0=>nx346 ); ix367 : xnor2 port map ( Y=>nx366, A0=>PRI_IN_4(3), A1=>PRI_IN_3(3)); REG_8_reg_q_4 : dff port map ( Q=>PRI_OUT_2(4), QB=>OPEN, D=>nx388, CLK=> CLK); ix389 : xnor2 port map ( Y=>nx388, A0=>nx2307, A1=>nx386); ix2308 : aoi22 port map ( Y=>nx2307, A0=>nx2309, A1=>PRI_IN_3(3), B0=> nx364, B1=>nx366); ix2310 : inv02 port map ( Y=>nx2309, A=>PRI_IN_4(3)); ix387 : xnor2 port map ( Y=>nx386, A0=>PRI_IN_4(4), A1=>PRI_IN_3(4)); REG_8_reg_q_5 : dff port map ( Q=>PRI_OUT_2(5), QB=>OPEN, D=>nx408, CLK=> CLK); ix409 : xor2 port map ( Y=>nx408, A0=>nx404, A1=>nx406); ix405 : mux21 port map ( Y=>nx404, A0=>PRI_IN_4(4), A1=>nx2307, S0=>nx386 ); ix407 : xnor2 port map ( Y=>nx406, A0=>PRI_IN_4(5), A1=>PRI_IN_3(5)); REG_8_reg_q_6 : dff port map ( Q=>PRI_OUT_2(6), QB=>OPEN, D=>nx428, CLK=> CLK); ix429 : xnor2 port map ( Y=>nx428, A0=>nx2323, A1=>nx426); ix2324 : aoi22 port map ( Y=>nx2323, A0=>nx2325, A1=>PRI_IN_3(5), B0=> nx404, B1=>nx406); ix2326 : inv02 port map ( Y=>nx2325, A=>PRI_IN_4(5)); ix427 : xnor2 port map ( Y=>nx426, A0=>PRI_IN_4(6), A1=>PRI_IN_3(6)); REG_8_reg_q_7 : dff port map ( Q=>PRI_OUT_2(7), QB=>OPEN, D=>nx448, CLK=> CLK); ix449 : xor2 port map ( Y=>nx448, A0=>nx444, A1=>nx446); ix445 : mux21 port map ( Y=>nx444, A0=>PRI_IN_4(6), A1=>nx2323, S0=>nx426 ); ix447 : xnor2 port map ( Y=>nx446, A0=>PRI_IN_4(7), A1=>PRI_IN_3(7)); REG_8_reg_q_8 : dff port map ( Q=>PRI_OUT_2(8), QB=>OPEN, D=>nx468, CLK=> CLK); ix469 : xnor2 port map ( Y=>nx468, A0=>nx2339, A1=>nx466); ix2340 : aoi22 port map ( Y=>nx2339, A0=>nx2341, A1=>PRI_IN_3(7), B0=> nx444, B1=>nx446); ix2342 : inv02 port map ( Y=>nx2341, A=>PRI_IN_4(7)); ix467 : xnor2 port map ( Y=>nx466, A0=>PRI_IN_4(8), A1=>PRI_IN_3(8)); REG_8_reg_q_9 : dff port map ( Q=>PRI_OUT_2(9), QB=>OPEN, D=>nx488, CLK=> CLK); ix489 : xor2 port map ( Y=>nx488, A0=>nx484, A1=>nx486); ix485 : mux21 port map ( Y=>nx484, A0=>PRI_IN_4(8), A1=>nx2339, S0=>nx466 ); ix487 : xnor2 port map ( Y=>nx486, A0=>PRI_IN_4(9), A1=>PRI_IN_3(9)); REG_8_reg_q_10 : dff port map ( Q=>PRI_OUT_2(10), QB=>OPEN, D=>nx508, CLK =>CLK); ix509 : xnor2 port map ( Y=>nx508, A0=>nx2356, A1=>nx506); ix2357 : aoi22 port map ( Y=>nx2356, A0=>nx2359, A1=>PRI_IN_3(9), B0=> nx484, B1=>nx486); ix2360 : inv02 port map ( Y=>nx2359, A=>PRI_IN_4(9)); ix507 : xnor2 port map ( Y=>nx506, A0=>PRI_IN_4(10), A1=>PRI_IN_3(10)); REG_8_reg_q_11 : dff port map ( Q=>PRI_OUT_2(11), QB=>OPEN, D=>nx528, CLK =>CLK); ix529 : xor2 port map ( Y=>nx528, A0=>nx524, A1=>nx526); ix525 : mux21 port map ( Y=>nx524, A0=>PRI_IN_4(10), A1=>nx2356, S0=> nx506); ix527 : xnor2 port map ( Y=>nx526, A0=>PRI_IN_4(11), A1=>PRI_IN_3(11)); REG_8_reg_q_12 : dff port map ( Q=>PRI_OUT_2(12), QB=>OPEN, D=>nx548, CLK =>CLK); ix549 : xnor2 port map ( Y=>nx548, A0=>nx2375, A1=>nx546); ix2376 : aoi22 port map ( Y=>nx2375, A0=>nx2377, A1=>PRI_IN_3(11), B0=> nx524, B1=>nx526); ix2378 : inv02 port map ( Y=>nx2377, A=>PRI_IN_4(11)); ix547 : xnor2 port map ( Y=>nx546, A0=>PRI_IN_4(12), A1=>PRI_IN_3(12)); REG_8_reg_q_13 : dff port map ( Q=>PRI_OUT_2(13), QB=>OPEN, D=>nx568, CLK =>CLK); ix569 : xor2 port map ( Y=>nx568, A0=>nx564, A1=>nx566); ix565 : mux21 port map ( Y=>nx564, A0=>PRI_IN_4(12), A1=>nx2375, S0=> nx546); ix567 : xnor2 port map ( Y=>nx566, A0=>PRI_IN_4(13), A1=>PRI_IN_3(13)); REG_8_reg_q_14 : dff port map ( Q=>PRI_OUT_2(14), QB=>OPEN, D=>nx588, CLK =>CLK); ix589 : xnor2 port map ( Y=>nx588, A0=>nx2391, A1=>nx586); ix2392 : aoi22 port map ( Y=>nx2391, A0=>nx2393, A1=>PRI_IN_3(13), B0=> nx564, B1=>nx566); ix2394 : inv02 port map ( Y=>nx2393, A=>PRI_IN_4(13)); ix587 : xnor2 port map ( Y=>nx586, A0=>PRI_IN_4(14), A1=>PRI_IN_3(14)); REG_8_reg_q_15 : dff port map ( Q=>PRI_OUT_2(15), QB=>OPEN, D=>nx608, CLK =>CLK); ix609 : xnor2 port map ( Y=>nx608, A0=>nx604, A1=>nx2401); ix605 : mux21 port map ( Y=>nx604, A0=>PRI_IN_4(14), A1=>nx2391, S0=> nx586); ix2402 : xor2 port map ( Y=>nx2401, A0=>PRI_IN_4(15), A1=>PRI_IN_3(15)); ix2119 : ao21 port map ( Y=>PRI_OUT_1(0), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_0, B0=>nx2116); REG_7_reg_q_0 : dff port map ( Q=>reg_7_q_c_0, QB=>OPEN, D=>nx2074, CLK=> CLK); ix2075 : ao21 port map ( Y=>nx2074, A0=>PRI_IN_0(0), A1=>nx2409, B0=> nx2413); REG_6_reg_q_0 : dff port map ( Q=>reg_6_q_c_0, QB=>nx2409, D=>nx2056, CLK =>CLK); ix2414 : nor02 port map ( Y=>nx2413, A0=>nx2409, A1=>PRI_IN_0(0)); ix2117 : ao32 port map ( Y=>nx2116, A0=>reg_6_q_c_0, A1=>nx2887, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_0, B1=>nx2881); ix2418 : inv02 port map ( Y=>nx2417, A=>C_MUX2_4_SEL); REG_5_reg_q_0 : dff port map ( Q=>reg_5_q_c_0, QB=>OPEN, D=>nx2100, CLK=> CLK); ix2101 : oai21 port map ( Y=>nx2100, A0=>PRI_IN_3(0), A1=>nx2409, B0=> nx2092); ix2093 : nand02 port map ( Y=>nx2092, A0=>nx2409, A1=>PRI_IN_3(0)); ix2113 : nor02 port map ( Y=>nx2112, A0=>C_MUX2_4_SEL, A1=>C_MUX2_2_SEL); ix2159 : ao21 port map ( Y=>PRI_OUT_1(1), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_1, B0=>nx2156); REG_7_reg_q_1 : dff port map ( Q=>reg_7_q_c_1, QB=>OPEN, D=>nx2132, CLK=> CLK); ix2133 : xnor2 port map ( Y=>nx2132, A0=>nx2413, A1=>nx2130); REG_6_reg_q_1 : dff port map ( Q=>reg_6_q_c_1, QB=>nx2439, D=>nx2122, CLK =>CLK); ix2123 : xor2 port map ( Y=>nx2122, A0=>nx2435, A1=>nx2437); ix2436 : nand02 port map ( Y=>nx2435, A0=>reg_1_q_c_0, A1=>reg_6_q_c_0); ix2157 : ao32 port map ( Y=>nx2156, A0=>reg_6_q_c_1, A1=>nx2887, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_1, B1=>nx2881); REG_5_reg_q_1 : dff port map ( Q=>reg_5_q_c_1, QB=>OPEN, D=>nx2146, CLK=> CLK); ix2147 : xor2 port map ( Y=>nx2146, A0=>nx2092, A1=>nx2144); ix2227 : ao21 port map ( Y=>PRI_OUT_1(2), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_2, B0=>nx2224); REG_7_reg_q_2 : dff port map ( Q=>reg_7_q_c_2, QB=>OPEN, D=>nx2190, CLK=> CLK); ix2191 : xnor2 port map ( Y=>nx2190, A0=>nx2455, A1=>nx2188); ix2456 : aoi22 port map ( Y=>nx2455, A0=>nx2439, A1=>PRI_IN_0(1), B0=> nx2066, B1=>nx2130); REG_6_reg_q_2 : dff port map ( Q=>reg_6_q_c_2, QB=>nx2467, D=>nx2180, CLK =>CLK); ix2181 : xor2 port map ( Y=>nx2180, A0=>nx2461, A1=>nx2465); ix2462 : aoi32 port map ( Y=>nx2461, A0=>reg_1_q_c_0, A1=>reg_6_q_c_0, A2 =>nx2120, B0=>reg_6_q_c_1, B1=>reg_1_q_c_1); ix2225 : ao32 port map ( Y=>nx2224, A0=>reg_6_q_c_2, A1=>nx2887, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_2, B1=>nx2881); REG_5_reg_q_2 : dff port map ( Q=>reg_5_q_c_2, QB=>OPEN, D=>nx2214, CLK=> CLK); ix2215 : xnor2 port map ( Y=>nx2214, A0=>nx2473, A1=>nx2212); ix2474 : aoi22 port map ( Y=>nx2473, A0=>nx2475, A1=>reg_6_q_c_1, B0=> nx2092, B1=>nx2144); ix2476 : inv02 port map ( Y=>nx2475, A=>PRI_IN_3(1)); ix2295 : ao21 port map ( Y=>PRI_OUT_1(3), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_3, B0=>nx2292); REG_7_reg_q_3 : dff port map ( Q=>reg_7_q_c_3, QB=>OPEN, D=>nx2258, CLK=> CLK); ix2259 : xor2 port map ( Y=>nx2258, A0=>nx2236, A1=>nx2256); ix2237 : mux21 port map ( Y=>nx2236, A0=>reg_6_q_c_2, A1=>nx2455, S0=> nx2188); REG_6_reg_q_3 : dff port map ( Q=>reg_6_q_c_3, QB=>nx2495, D=>nx2248, CLK =>CLK); ix2249 : xnor2 port map ( Y=>nx2248, A0=>nx2244, A1=>nx2492); ix2245 : oai22 port map ( Y=>nx2244, A0=>nx2461, A1=>nx2465, B0=>nx2467, B1=>nx1529); ix2293 : ao32 port map ( Y=>nx2292, A0=>reg_6_q_c_3, A1=>nx2887, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_3, B1=>nx2881); REG_5_reg_q_3 : dff port map ( Q=>reg_5_q_c_3, QB=>OPEN, D=>nx2282, CLK=> CLK); ix2283 : xor2 port map ( Y=>nx2282, A0=>nx2278, A1=>nx2280); ix2279 : oai22 port map ( Y=>nx2278, A0=>nx2473, A1=>nx2505, B0=> PRI_IN_3(2), B1=>nx2467); ix2363 : ao21 port map ( Y=>PRI_OUT_1(4), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_4, B0=>nx2360); REG_7_reg_q_4 : dff port map ( Q=>reg_7_q_c_4, QB=>OPEN, D=>nx2326, CLK=> CLK); ix2327 : xnor2 port map ( Y=>nx2326, A0=>nx2515, A1=>nx2324); ix2516 : aoi22 port map ( Y=>nx2515, A0=>nx2495, A1=>PRI_IN_0(3), B0=> nx2236, B1=>nx2256); REG_6_reg_q_4 : dff port map ( Q=>reg_6_q_c_4, QB=>nx2529, D=>nx2316, CLK =>CLK); ix2317 : xor2 port map ( Y=>nx2316, A0=>nx2523, A1=>nx2526); ix2524 : aoi22 port map ( Y=>nx2523, A0=>reg_6_q_c_3, A1=>reg_1_q_c_3, B0 =>nx2244, B1=>nx2246); ix2361 : ao32 port map ( Y=>nx2360, A0=>reg_6_q_c_4, A1=>nx2887, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_4, B1=>nx2881); REG_5_reg_q_4 : dff port map ( Q=>reg_5_q_c_4, QB=>OPEN, D=>nx2350, CLK=> CLK); ix2351 : xnor2 port map ( Y=>nx2350, A0=>nx2535, A1=>nx2348); ix2536 : aoi22 port map ( Y=>nx2535, A0=>nx2537, A1=>reg_6_q_c_3, B0=> nx2278, B1=>nx2280); ix2538 : inv02 port map ( Y=>nx2537, A=>PRI_IN_3(3)); ix2431 : ao21 port map ( Y=>PRI_OUT_1(5), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_5, B0=>nx2428); REG_7_reg_q_5 : dff port map ( Q=>reg_7_q_c_5, QB=>OPEN, D=>nx2394, CLK=> CLK); ix2395 : xor2 port map ( Y=>nx2394, A0=>nx2372, A1=>nx2392); ix2373 : mux21 port map ( Y=>nx2372, A0=>reg_6_q_c_4, A1=>nx2515, S0=> nx2324); REG_6_reg_q_5 : dff port map ( Q=>reg_6_q_c_5, QB=>nx2559, D=>nx2384, CLK =>CLK); ix2385 : xnor2 port map ( Y=>nx2384, A0=>nx2380, A1=>nx2557); ix2381 : oai22 port map ( Y=>nx2380, A0=>nx2523, A1=>nx2526, B0=>nx2529, B1=>nx1625); ix2429 : ao32 port map ( Y=>nx2428, A0=>reg_6_q_c_5, A1=>nx2889, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_5, B1=>nx2883); REG_5_reg_q_5 : dff port map ( Q=>reg_5_q_c_5, QB=>OPEN, D=>nx2418, CLK=> CLK); ix2419 : xor2 port map ( Y=>nx2418, A0=>nx2414, A1=>nx2416); ix2415 : oai22 port map ( Y=>nx2414, A0=>nx2535, A1=>nx2567, B0=> PRI_IN_3(4), B1=>nx2529); ix2499 : ao21 port map ( Y=>PRI_OUT_1(6), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_6, B0=>nx2496); REG_7_reg_q_6 : dff port map ( Q=>reg_7_q_c_6, QB=>OPEN, D=>nx2462, CLK=> CLK); ix2463 : xnor2 port map ( Y=>nx2462, A0=>nx2577, A1=>nx2460); ix2578 : aoi22 port map ( Y=>nx2577, A0=>nx2559, A1=>PRI_IN_0(5), B0=> nx2372, B1=>nx2392); REG_6_reg_q_6 : dff port map ( Q=>reg_6_q_c_6, QB=>nx2591, D=>nx2452, CLK =>CLK); ix2453 : xor2 port map ( Y=>nx2452, A0=>nx2585, A1=>nx2589); ix2586 : aoi22 port map ( Y=>nx2585, A0=>reg_6_q_c_5, A1=>reg_1_q_c_5, B0 =>nx2380, B1=>nx2382); ix2497 : ao32 port map ( Y=>nx2496, A0=>reg_6_q_c_6, A1=>nx2889, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_6, B1=>nx2883); REG_5_reg_q_6 : dff port map ( Q=>reg_5_q_c_6, QB=>OPEN, D=>nx2486, CLK=> CLK); ix2487 : xnor2 port map ( Y=>nx2486, A0=>nx2597, A1=>nx2484); ix2598 : aoi22 port map ( Y=>nx2597, A0=>nx2599, A1=>reg_6_q_c_5, B0=> nx2414, B1=>nx2416); ix2600 : inv02 port map ( Y=>nx2599, A=>PRI_IN_3(5)); ix2567 : ao21 port map ( Y=>PRI_OUT_1(7), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_7, B0=>nx2564); REG_7_reg_q_7 : dff port map ( Q=>reg_7_q_c_7, QB=>OPEN, D=>nx2530, CLK=> CLK); ix2531 : xor2 port map ( Y=>nx2530, A0=>nx2508, A1=>nx2528); ix2509 : mux21 port map ( Y=>nx2508, A0=>reg_6_q_c_6, A1=>nx2577, S0=> nx2460); REG_6_reg_q_7 : dff port map ( Q=>reg_6_q_c_7, QB=>nx2617, D=>nx2520, CLK =>CLK); ix2521 : xnor2 port map ( Y=>nx2520, A0=>nx2516, A1=>nx2615); ix2517 : oai22 port map ( Y=>nx2516, A0=>nx2585, A1=>nx2589, B0=>nx2591, B1=>nx1717); ix2565 : ao32 port map ( Y=>nx2564, A0=>reg_6_q_c_7, A1=>nx2889, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_7, B1=>nx2883); REG_5_reg_q_7 : dff port map ( Q=>reg_5_q_c_7, QB=>OPEN, D=>nx2554, CLK=> CLK); ix2555 : xor2 port map ( Y=>nx2554, A0=>nx2550, A1=>nx2552); ix2551 : oai22 port map ( Y=>nx2550, A0=>nx2597, A1=>nx2626, B0=> PRI_IN_3(6), B1=>nx2591); ix2635 : ao21 port map ( Y=>PRI_OUT_1(8), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_8, B0=>nx2632); REG_7_reg_q_8 : dff port map ( Q=>reg_7_q_c_8, QB=>OPEN, D=>nx2598, CLK=> CLK); ix2599 : xnor2 port map ( Y=>nx2598, A0=>nx2635, A1=>nx2596); ix2636 : aoi22 port map ( Y=>nx2635, A0=>nx2617, A1=>PRI_IN_0(7), B0=> nx2508, B1=>nx2528); REG_6_reg_q_8 : dff port map ( Q=>reg_6_q_c_8, QB=>nx2649, D=>nx2588, CLK =>CLK); ix2589 : xor2 port map ( Y=>nx2588, A0=>nx2643, A1=>nx2647); ix2644 : aoi22 port map ( Y=>nx2643, A0=>reg_6_q_c_7, A1=>reg_1_q_c_7, B0 =>nx2516, B1=>nx2518); ix2633 : ao32 port map ( Y=>nx2632, A0=>reg_6_q_c_8, A1=>nx2889, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_8, B1=>nx2883); REG_5_reg_q_8 : dff port map ( Q=>reg_5_q_c_8, QB=>OPEN, D=>nx2622, CLK=> CLK); ix2623 : xnor2 port map ( Y=>nx2622, A0=>nx2657, A1=>nx2620); ix2658 : aoi22 port map ( Y=>nx2657, A0=>nx2659, A1=>reg_6_q_c_7, B0=> nx2550, B1=>nx2552); ix2660 : inv02 port map ( Y=>nx2659, A=>PRI_IN_3(7)); ix2703 : ao21 port map ( Y=>PRI_OUT_1(9), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_9, B0=>nx2700); REG_7_reg_q_9 : dff port map ( Q=>reg_7_q_c_9, QB=>OPEN, D=>nx2666, CLK=> CLK); ix2667 : xor2 port map ( Y=>nx2666, A0=>nx2644, A1=>nx2664); ix2645 : mux21 port map ( Y=>nx2644, A0=>reg_6_q_c_8, A1=>nx2635, S0=> nx2596); REG_6_reg_q_9 : dff port map ( Q=>reg_6_q_c_9, QB=>nx2675, D=>nx2656, CLK =>CLK); ix2657 : xnor2 port map ( Y=>nx2656, A0=>nx2652, A1=>nx2673); ix2653 : oai22 port map ( Y=>nx2652, A0=>nx2643, A1=>nx2647, B0=>nx2649, B1=>nx1809); ix2701 : ao32 port map ( Y=>nx2700, A0=>reg_6_q_c_9, A1=>nx2889, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_9, B1=>nx2883); REG_5_reg_q_9 : dff port map ( Q=>reg_5_q_c_9, QB=>OPEN, D=>nx2690, CLK=> CLK); ix2691 : xor2 port map ( Y=>nx2690, A0=>nx2686, A1=>nx2688); ix2687 : oai22 port map ( Y=>nx2686, A0=>nx2657, A1=>nx2685, B0=> PRI_IN_3(8), B1=>nx2649); ix2771 : ao21 port map ( Y=>PRI_OUT_1(10), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_10, B0=>nx2768); REG_7_reg_q_10 : dff port map ( Q=>reg_7_q_c_10, QB=>OPEN, D=>nx2734, CLK =>CLK); ix2735 : xnor2 port map ( Y=>nx2734, A0=>nx2694, A1=>nx2732); ix2695 : aoi22 port map ( Y=>nx2694, A0=>nx2675, A1=>PRI_IN_0(9), B0=> nx2644, B1=>nx2664); REG_6_reg_q_10 : dff port map ( Q=>reg_6_q_c_10, QB=>nx2705, D=>nx2724, CLK=>CLK); ix2725 : xor2 port map ( Y=>nx2724, A0=>nx2699, A1=>nx2703); ix2700 : aoi22 port map ( Y=>nx2699, A0=>reg_6_q_c_9, A1=>reg_1_q_c_9, B0 =>nx2652, B1=>nx2654); ix2769 : ao32 port map ( Y=>nx2768, A0=>reg_6_q_c_10, A1=>nx2891, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_10, B1=>nx2885); REG_5_reg_q_10 : dff port map ( Q=>reg_5_q_c_10, QB=>OPEN, D=>nx2758, CLK =>CLK); ix2759 : xnor2 port map ( Y=>nx2758, A0=>nx2713, A1=>nx2756); ix2714 : aoi22 port map ( Y=>nx2713, A0=>nx2715, A1=>reg_6_q_c_9, B0=> nx2686, B1=>nx2688); ix2716 : inv02 port map ( Y=>nx2715, A=>PRI_IN_3(9)); ix2839 : ao21 port map ( Y=>PRI_OUT_1(11), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_11, B0=>nx2836); REG_7_reg_q_11 : dff port map ( Q=>reg_7_q_c_11, QB=>OPEN, D=>nx2802, CLK =>CLK); ix2803 : xor2 port map ( Y=>nx2802, A0=>nx2780, A1=>nx2800); ix2781 : mux21 port map ( Y=>nx2780, A0=>reg_6_q_c_10, A1=>nx2694, S0=> nx2732); REG_6_reg_q_11 : dff port map ( Q=>reg_6_q_c_11, QB=>nx2733, D=>nx2792, CLK=>CLK); ix2793 : xnor2 port map ( Y=>nx2792, A0=>nx2788, A1=>nx2731); ix2789 : oai22 port map ( Y=>nx2788, A0=>nx2699, A1=>nx2703, B0=>nx2705, B1=>nx1901); ix2837 : ao32 port map ( Y=>nx2836, A0=>reg_6_q_c_11, A1=>nx2891, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_11, B1=>nx2885); REG_5_reg_q_11 : dff port map ( Q=>reg_5_q_c_11, QB=>OPEN, D=>nx2826, CLK =>CLK); ix2827 : xor2 port map ( Y=>nx2826, A0=>nx2822, A1=>nx2824); ix2823 : oai22 port map ( Y=>nx2822, A0=>nx2713, A1=>nx2740, B0=> PRI_IN_3(10), B1=>nx2705); ix2907 : ao21 port map ( Y=>PRI_OUT_1(12), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_12, B0=>nx2904); REG_7_reg_q_12 : dff port map ( Q=>reg_7_q_c_12, QB=>OPEN, D=>nx2870, CLK =>CLK); ix2871 : xnor2 port map ( Y=>nx2870, A0=>nx2749, A1=>nx2868); ix2750 : aoi22 port map ( Y=>nx2749, A0=>nx2733, A1=>PRI_IN_0(11), B0=> nx2780, B1=>nx2800); REG_6_reg_q_12 : dff port map ( Q=>reg_6_q_c_12, QB=>nx2763, D=>nx2860, CLK=>CLK); ix2861 : xor2 port map ( Y=>nx2860, A0=>nx2757, A1=>nx2761); ix2758 : aoi22 port map ( Y=>nx2757, A0=>reg_6_q_c_11, A1=>reg_1_q_c_11, B0=>nx2788, B1=>nx2790); ix2905 : ao32 port map ( Y=>nx2904, A0=>reg_6_q_c_12, A1=>nx2891, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_12, B1=>nx2885); REG_5_reg_q_12 : dff port map ( Q=>reg_5_q_c_12, QB=>OPEN, D=>nx2894, CLK =>CLK); ix2895 : xnor2 port map ( Y=>nx2894, A0=>nx2769, A1=>nx2892); ix2770 : aoi22 port map ( Y=>nx2769, A0=>nx2771, A1=>reg_6_q_c_11, B0=> nx2822, B1=>nx2824); ix2772 : inv02 port map ( Y=>nx2771, A=>PRI_IN_3(11)); ix2975 : ao21 port map ( Y=>PRI_OUT_1(13), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_13, B0=>nx2972); REG_7_reg_q_13 : dff port map ( Q=>reg_7_q_c_13, QB=>OPEN, D=>nx2938, CLK =>CLK); ix2939 : xor2 port map ( Y=>nx2938, A0=>nx2916, A1=>nx2936); ix2917 : mux21 port map ( Y=>nx2916, A0=>reg_6_q_c_12, A1=>nx2749, S0=> nx2868); REG_6_reg_q_13 : dff port map ( Q=>reg_6_q_c_13, QB=>nx2793, D=>nx2928, CLK=>CLK); ix2929 : xnor2 port map ( Y=>nx2928, A0=>nx2924, A1=>nx2791); ix2925 : oai22 port map ( Y=>nx2924, A0=>nx2757, A1=>nx2761, B0=>nx2763, B1=>nx1993); ix2973 : ao32 port map ( Y=>nx2972, A0=>reg_6_q_c_13, A1=>nx2891, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_13, B1=>nx2885); REG_5_reg_q_13 : dff port map ( Q=>reg_5_q_c_13, QB=>OPEN, D=>nx2962, CLK =>CLK); ix2963 : xor2 port map ( Y=>nx2962, A0=>nx2958, A1=>nx2960); ix2959 : oai22 port map ( Y=>nx2958, A0=>nx2769, A1=>nx2799, B0=> PRI_IN_3(12), B1=>nx2763); ix3043 : ao21 port map ( Y=>PRI_OUT_1(14), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_14, B0=>nx3040); REG_7_reg_q_14 : dff port map ( Q=>reg_7_q_c_14, QB=>OPEN, D=>nx3006, CLK =>CLK); ix3007 : xnor2 port map ( Y=>nx3006, A0=>nx2807, A1=>nx3004); ix2808 : aoi22 port map ( Y=>nx2807, A0=>nx2793, A1=>PRI_IN_0(13), B0=> nx2916, B1=>nx2936); REG_6_reg_q_14 : dff port map ( Q=>reg_6_q_c_14, QB=>nx2819, D=>nx2996, CLK=>CLK); ix2997 : xor2 port map ( Y=>nx2996, A0=>nx2813, A1=>nx2817); ix2814 : aoi22 port map ( Y=>nx2813, A0=>reg_6_q_c_13, A1=>reg_1_q_c_13, B0=>nx2924, B1=>nx2926); ix3041 : ao32 port map ( Y=>nx3040, A0=>reg_6_q_c_14, A1=>nx2891, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_14, B1=>nx2885); REG_5_reg_q_14 : dff port map ( Q=>reg_5_q_c_14, QB=>OPEN, D=>nx3030, CLK =>CLK); ix3031 : xnor2 port map ( Y=>nx3030, A0=>nx2827, A1=>nx3028); ix2828 : aoi22 port map ( Y=>nx2827, A0=>nx2829, A1=>reg_6_q_c_13, B0=> nx2958, B1=>nx2960); ix2830 : inv02 port map ( Y=>nx2829, A=>PRI_IN_3(13)); ix3111 : ao21 port map ( Y=>PRI_OUT_1(15), A0=>C_MUX2_4_SEL, A1=> reg_7_q_c_15, B0=>nx3108); REG_7_reg_q_15 : dff port map ( Q=>reg_7_q_c_15, QB=>OPEN, D=>nx3074, CLK =>CLK); ix3075 : xnor2 port map ( Y=>nx3074, A0=>nx3052, A1=>nx2839); ix3053 : mux21 port map ( Y=>nx3052, A0=>reg_6_q_c_14, A1=>nx2807, S0=> nx3004); ix3065 : xnor2 port map ( Y=>nx3064, A0=>nx3060, A1=>nx2847); ix3061 : oai22 port map ( Y=>nx3060, A0=>nx2813, A1=>nx2817, B0=>nx2819, B1=>nx2085); REG_6_reg_q_15 : dff port map ( Q=>reg_6_q_c_15, QB=>nx2841, D=>nx3064, CLK=>CLK); ix3109 : ao32 port map ( Y=>nx3108, A0=>reg_6_q_c_15, A1=>nx2417, A2=> C_MUX2_2_SEL, B0=>reg_5_q_c_15, B1=>nx2112); REG_5_reg_q_15 : dff port map ( Q=>reg_5_q_c_15, QB=>OPEN, D=>nx3098, CLK =>CLK); ix3099 : xnor2 port map ( Y=>nx3098, A0=>nx3094, A1=>nx2861); ix3095 : oai22 port map ( Y=>nx3094, A0=>nx2827, A1=>nx2859, B0=> PRI_IN_3(14), B1=>nx2819); ix2860 : inv02 port map ( Y=>nx2859, A=>nx3028); ix2927 : inv02 port map ( Y=>nx2926, A=>nx2791); ix2800 : inv02 port map ( Y=>nx2799, A=>nx2892); ix2791 : inv02 port map ( Y=>nx2790, A=>nx2731); ix2741 : inv02 port map ( Y=>nx2740, A=>nx2756); ix2655 : inv02 port map ( Y=>nx2654, A=>nx2673); ix2686 : inv02 port map ( Y=>nx2685, A=>nx2620); ix2519 : inv02 port map ( Y=>nx2518, A=>nx2615); ix2627 : inv02 port map ( Y=>nx2626, A=>nx2484); ix2383 : inv02 port map ( Y=>nx2382, A=>nx2557); ix2568 : inv02 port map ( Y=>nx2567, A=>nx2348); ix2247 : inv02 port map ( Y=>nx2246, A=>nx2492); ix2506 : inv02 port map ( Y=>nx2505, A=>nx2212); ix2121 : inv02 port map ( Y=>nx2120, A=>nx2437); ix2067 : inv02 port map ( Y=>nx2066, A=>nx2413); ix1907 : inv02 port map ( Y=>nx1906, A=>nx2107); ix1857 : inv02 port map ( Y=>nx1856, A=>nx2029); ix1843 : inv02 port map ( Y=>nx1842, A=>nx2039); ix1829 : inv02 port map ( Y=>nx1429, A=>nx2043); ix1791 : inv02 port map ( Y=>nx1790, A=>nx2051); ix1723 : inv02 port map ( Y=>nx1722, A=>nx2017); ix1673 : inv02 port map ( Y=>nx1672, A=>nx1937); ix1659 : inv02 port map ( Y=>nx1658, A=>nx1947); ix1645 : inv02 port map ( Y=>nx1427, A=>nx1951); ix1607 : inv02 port map ( Y=>nx1606, A=>nx1958); ix1539 : inv02 port map ( Y=>nx1538, A=>nx1925); ix1489 : inv02 port map ( Y=>nx1488, A=>nx1845); ix1475 : inv02 port map ( Y=>nx1474, A=>nx1855); ix1461 : inv02 port map ( Y=>nx1425, A=>nx1859); ix1423 : inv02 port map ( Y=>nx1422, A=>nx1866); ix1355 : inv02 port map ( Y=>nx1354, A=>nx1833); ix1305 : inv02 port map ( Y=>nx1304, A=>nx1753); ix1291 : inv02 port map ( Y=>nx1290, A=>nx1763); ix1277 : inv02 port map ( Y=>nx1421, A=>nx1767); ix1239 : inv02 port map ( Y=>nx1238, A=>nx1774); ix1171 : inv02 port map ( Y=>nx1170, A=>nx1741); ix1121 : inv02 port map ( Y=>nx1120, A=>nx1661); ix1107 : inv02 port map ( Y=>nx1106, A=>nx1671); ix1093 : inv02 port map ( Y=>nx1417, A=>nx1675); ix1055 : inv02 port map ( Y=>nx1054, A=>nx1682); ix987 : inv02 port map ( Y=>nx986, A=>nx1649); ix937 : inv02 port map ( Y=>nx936, A=>nx1565); ix923 : inv02 port map ( Y=>nx922, A=>nx1577); ix909 : inv02 port map ( Y=>nx1414, A=>nx1581); ix871 : inv02 port map ( Y=>nx870, A=>nx1589); ix803 : inv02 port map ( Y=>nx802, A=>nx1553); ix753 : inv02 port map ( Y=>nx752, A=>nx1481); ix739 : inv02 port map ( Y=>nx738, A=>nx1489); ix733 : inv02 port map ( Y=>nx1411, A=>nx1493); ix705 : inv02 port map ( Y=>nx704, A=>nx1499); ix3 : inv02 port map ( Y=>nx2, A=>nx2159); ix2868 : nor02 port map ( Y=>nx2869, A0=>C_MUX2_5_SEL, A1=>C_MUX2_1_SEL); ix2870 : nor02 port map ( Y=>nx2871, A0=>C_MUX2_5_SEL, A1=>C_MUX2_1_SEL); ix2872 : nor02 port map ( Y=>nx2873, A0=>C_MUX2_5_SEL, A1=>C_MUX2_1_SEL); ix2874 : and02 port map ( Y=>nx2875, A0=>C_MUX2_5_SEL, A1=>nx1473); ix2876 : and02 port map ( Y=>nx2877, A0=>C_MUX2_5_SEL, A1=>nx1473); ix2878 : and02 port map ( Y=>nx2879, A0=>C_MUX2_5_SEL, A1=>nx1473); ix2880 : nor02 port map ( Y=>nx2881, A0=>C_MUX2_4_SEL, A1=>C_MUX2_2_SEL); ix2882 : nor02 port map ( Y=>nx2883, A0=>C_MUX2_4_SEL, A1=>C_MUX2_2_SEL); ix2884 : nor02 port map ( Y=>nx2885, A0=>C_MUX2_4_SEL, A1=>C_MUX2_2_SEL); ix2886 : inv02 port map ( Y=>nx2887, A=>C_MUX2_4_SEL); ix2888 : inv02 port map ( Y=>nx2889, A=>C_MUX2_4_SEL); ix2890 : inv02 port map ( Y=>nx2891, A=>C_MUX2_4_SEL); ix679 : xor2 port map ( Y=>nx678, A0=>PRI_IN_4(0), A1=>PRI_IN_0(0)); ix623 : xor2 port map ( Y=>nx622, A0=>PRI_IN_0(0), A1=>PRI_IN_2(0)); ix2057 : xor2 port map ( Y=>nx2056, A0=>reg_1_q_c_0, A1=>reg_6_q_c_0); ix2131 : xor2 port map ( Y=>nx2130, A0=>PRI_IN_0(1), A1=>nx2439); ix2438 : xor2 port map ( Y=>nx2437, A0=>reg_1_q_c_1, A1=>nx2439); ix2145 : xor2 port map ( Y=>nx2144, A0=>PRI_IN_3(1), A1=>nx2439); ix2189 : xor2 port map ( Y=>nx2188, A0=>PRI_IN_0(2), A1=>nx2467); ix2466 : xnor2 port map ( Y=>nx2465, A0=>nx1529, A1=>nx2467); ix2213 : xor2 port map ( Y=>nx2212, A0=>PRI_IN_3(2), A1=>nx2467); ix2257 : xor2 port map ( Y=>nx2256, A0=>PRI_IN_0(3), A1=>nx2495); ix2493 : xor2 port map ( Y=>nx2492, A0=>reg_1_q_c_3, A1=>nx2495); ix2281 : xor2 port map ( Y=>nx2280, A0=>PRI_IN_3(3), A1=>nx2495); ix2325 : xor2 port map ( Y=>nx2324, A0=>PRI_IN_0(4), A1=>nx2529); ix2527 : xnor2 port map ( Y=>nx2526, A0=>nx1625, A1=>nx2529); ix2349 : xor2 port map ( Y=>nx2348, A0=>PRI_IN_3(4), A1=>nx2529); ix2393 : xor2 port map ( Y=>nx2392, A0=>PRI_IN_0(5), A1=>nx2559); ix2558 : xor2 port map ( Y=>nx2557, A0=>reg_1_q_c_5, A1=>nx2559); ix2417 : xor2 port map ( Y=>nx2416, A0=>PRI_IN_3(5), A1=>nx2559); ix2461 : xor2 port map ( Y=>nx2460, A0=>PRI_IN_0(6), A1=>nx2591); ix2590 : xnor2 port map ( Y=>nx2589, A0=>nx1717, A1=>nx2591); ix2485 : xor2 port map ( Y=>nx2484, A0=>PRI_IN_3(6), A1=>nx2591); ix2529 : xor2 port map ( Y=>nx2528, A0=>PRI_IN_0(7), A1=>nx2617); ix2616 : xor2 port map ( Y=>nx2615, A0=>reg_1_q_c_7, A1=>nx2617); ix2553 : xor2 port map ( Y=>nx2552, A0=>PRI_IN_3(7), A1=>nx2617); ix2597 : xor2 port map ( Y=>nx2596, A0=>PRI_IN_0(8), A1=>nx2649); ix2648 : xnor2 port map ( Y=>nx2647, A0=>nx1809, A1=>nx2649); ix2621 : xor2 port map ( Y=>nx2620, A0=>PRI_IN_3(8), A1=>nx2649); ix2665 : xor2 port map ( Y=>nx2664, A0=>PRI_IN_0(9), A1=>nx2675); ix2674 : xor2 port map ( Y=>nx2673, A0=>reg_1_q_c_9, A1=>nx2675); ix2689 : xor2 port map ( Y=>nx2688, A0=>PRI_IN_3(9), A1=>nx2675); ix2733 : xor2 port map ( Y=>nx2732, A0=>PRI_IN_0(10), A1=>nx2705); ix2704 : xnor2 port map ( Y=>nx2703, A0=>nx1901, A1=>nx2705); ix2757 : xor2 port map ( Y=>nx2756, A0=>PRI_IN_3(10), A1=>nx2705); ix2801 : xor2 port map ( Y=>nx2800, A0=>PRI_IN_0(11), A1=>nx2733); ix2732 : xor2 port map ( Y=>nx2731, A0=>reg_1_q_c_11, A1=>nx2733); ix2825 : xor2 port map ( Y=>nx2824, A0=>PRI_IN_3(11), A1=>nx2733); ix2869 : xor2 port map ( Y=>nx2868, A0=>PRI_IN_0(12), A1=>nx2763); ix2762 : xnor2 port map ( Y=>nx2761, A0=>nx1993, A1=>nx2763); ix2893 : xor2 port map ( Y=>nx2892, A0=>PRI_IN_3(12), A1=>nx2763); ix2937 : xor2 port map ( Y=>nx2936, A0=>PRI_IN_0(13), A1=>nx2793); ix2792 : xor2 port map ( Y=>nx2791, A0=>reg_1_q_c_13, A1=>nx2793); ix2961 : xor2 port map ( Y=>nx2960, A0=>PRI_IN_3(13), A1=>nx2793); ix3005 : xor2 port map ( Y=>nx3004, A0=>PRI_IN_0(14), A1=>nx2819); ix2818 : xnor2 port map ( Y=>nx2817, A0=>nx2085, A1=>nx2819); ix3029 : xor2 port map ( Y=>nx3028, A0=>PRI_IN_3(14), A1=>nx2819); ix2840 : xor2 port map ( Y=>nx2839, A0=>PRI_IN_0(15), A1=>reg_6_q_c_15); ix2848 : xor2 port map ( Y=>nx2847, A0=>reg_1_q_c_15, A1=>nx2841); ix2862 : xor2 port map ( Y=>nx2861, A0=>PRI_IN_3(15), A1=>reg_6_q_c_15); end CIRCUIT_arch ;