-- -- Definition of CIRCUIT -- -- 12/14/05 22:06:43 -- -- LeonardoSpectrum Level 3, 2004a.63 -- library IEEE; use IEEE.STD_LOGIC_1164.all; entity CIRCUIT is port ( PRI_IN_0 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_1 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_2 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_3 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_4 : IN std_logic_vector (15 DOWNTO 0) ; PRI_OUT_0 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_1 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_2 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_3 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_4 : OUT std_logic_vector (15 DOWNTO 0) ; C_MUX2_1_SEL : IN std_logic ; C_MUX2_2_SEL : IN std_logic ; C_MUX2_3_SEL : IN std_logic ; C_MUX2_4_SEL : IN std_logic ; C_MUX2_5_SEL : IN std_logic ; CLK : IN std_logic) ; end CIRCUIT ; architecture CIRCUIT_arch of CIRCUIT is signal PRI_OUT_0_15_EXMPLR, PRI_OUT_0_10_EXMPLR, PRI_OUT_0_8_EXMPLR, PRI_OUT_0_6_EXMPLR, PRI_OUT_0_4_EXMPLR, PRI_OUT_0_2_EXMPLR, PRI_OUT_0_0_EXMPLR, PRI_OUT_4_15_EXMPLR, PRI_OUT_4_14_EXMPLR, PRI_OUT_4_13_EXMPLR, PRI_OUT_4_12_EXMPLR, PRI_OUT_4_11_EXMPLR, PRI_OUT_4_10_EXMPLR, PRI_OUT_4_9_EXMPLR, PRI_OUT_4_8_EXMPLR, PRI_OUT_4_7_EXMPLR, PRI_OUT_4_6_EXMPLR, PRI_OUT_4_5_EXMPLR, PRI_OUT_4_4_EXMPLR, PRI_OUT_4_3_EXMPLR, PRI_OUT_4_2_EXMPLR, PRI_OUT_4_1_EXMPLR, PRI_OUT_4_0_EXMPLR, nx2, nx10, nx18, nx20, nx38, nx40, nx56, nx58, nx60, nx78, nx80, nx96, nx98, nx100, nx118, nx120, nx136, nx138, nx140, nx158, nx160, nx176, nx178, nx180, nx198, nx200, nx216, nx218, nx220, nx238, nx240, nx256, nx258, nx260, nx278, nx280, nx296, nx300, nx318, nx326, nx328, nx344, nx346, nx348, nx366, nx368, nx384, nx386, nx388, nx406, nx408, nx424, nx426, nx428, nx446, nx448, nx464, nx466, nx468, nx486, nx488, nx504, nx506, nx508, nx526, nx528, nx544, nx546, nx548, nx566, nx568, nx584, nx586, nx588, nx606, nx608, reg_6_q_c_0, reg_9_q_c_0, reg_10_q_c_0, nx626, nx640, nx654, reg_3_q_c_0, nx676, nx686, nx694, nx706, reg_1_q_c_0, nx720, nx732, nx736, nx742, nx750, reg_6_q_c_1, reg_9_q_c_1, reg_10_q_c_1, nx766, nx768, nx776, nx778, nx786, nx788, reg_3_q_c_1, nx800, nx802, nx812, nx814, nx816, reg_1_q_c_1, nx830, nx844, nx846, reg_6_q_c_2, reg_2_q_c_2, nx898, nx908, nx918, reg_3_q_c_2, reg_5_q_c_2, nx946, nx948, nx950, nx962, nx964, reg_1_q_c_2, nx984, nx988, nx998, nx1002, nx1004, reg_6_q_c_3, reg_9_q_c_3, nx1036, reg_2_q_c_3, nx1044, reg_10_q_c_3, nx1052, nx1054, nx1056, nx1064, nx1066, nx1074, nx1076, reg_3_q_c_3, nx1090, reg_5_q_c_3, nx1106, nx1108, nx1118, nx1120, nx1122, reg_1_q_c_3, nx1146, nx1160, nx1162, reg_6_q_c_4, nx1214, nx1224, nx1234, reg_3_q_c_4, nx1262, nx1264, nx1266, nx1278, nx1280, reg_1_q_c_4, nx1304, nx1314, nx1318, nx1320, reg_6_q_c_5, nx1344, reg_9_q_c_5, nx1352, reg_2_q_c_5, nx1360, reg_10_q_c_5, nx1368, nx1370, nx1372, nx1380, nx1382, nx1390, nx1392, reg_3_q_c_5, nx1406, reg_5_q_c_5, nx1422, nx1424, nx1434, nx1436, nx1438, reg_1_q_c_5, nx1462, nx1476, nx1478, reg_6_q_c_6, reg_2_q_c_6, nx1530, nx1540, nx1550, reg_3_q_c_6, reg_5_q_c_6, nx1578, nx1580, nx1582, nx1594, nx1596, reg_1_q_c_6, nx1620, nx1630, nx1634, nx1636, reg_6_q_c_7, nx1660, reg_9_q_c_7, nx1668, reg_2_q_c_7, nx1676, reg_10_q_c_7, nx1684, nx1686, nx1688, nx1696, nx1698, nx1706, nx1708, reg_3_q_c_7, nx1722, reg_5_q_c_7, nx1738, nx1740, nx1750, nx1752, nx1754, reg_1_q_c_7, nx1778, nx1792, nx1794, reg_6_q_c_8, reg_2_q_c_8, nx1846, nx1856, nx1866, reg_3_q_c_8, reg_5_q_c_8, nx1894, nx1896, nx1898, nx1910, nx1912, reg_1_q_c_8, nx1936, nx1946, nx1950, nx1952, reg_6_q_c_9, nx1976, reg_9_q_c_9, nx1984, reg_2_q_c_9, nx1992, reg_10_q_c_9, nx2000, nx2002, nx2004, nx2012, nx2014, nx2022, nx2024, reg_3_q_c_9, nx2038, reg_5_q_c_9, nx2054, nx2056, nx2066, nx2068, nx2070, reg_1_q_c_9, nx2094, nx2108, nx2110, reg_6_q_c_10, reg_2_q_c_10, nx2162, nx2172, nx2182, reg_3_q_c_10, reg_5_q_c_10, nx2210, nx2212, nx2214, nx2226, nx2228, reg_1_q_c_10, nx2248, nx2252, nx2262, nx2266, nx2268, reg_6_q_c_11, nx2292, reg_9_q_c_11, nx2300, reg_2_q_c_11, nx2308, reg_10_q_c_11, nx2316, nx2318, nx2320, nx2328, nx2330, nx2338, nx2340, reg_3_q_c_11, nx2354, reg_5_q_c_11, nx2370, nx2372, nx2382, nx2384, nx2386, reg_1_q_c_11, nx2410, nx2426, reg_6_q_c_12, reg_2_q_c_12, nx2478, nx2488, nx2498, reg_3_q_c_12, reg_5_q_c_12, nx2526, nx2528, nx2530, nx2542, nx2544, reg_1_q_c_12, nx2568, nx2578, nx2582, nx2584, reg_6_q_c_13, reg_9_q_c_13, nx2616, reg_2_q_c_13, nx2624, reg_10_q_c_13, nx2632, nx2634, nx2636, nx2644, nx2646, nx2654, nx2656, reg_3_q_c_13, nx2670, reg_5_q_c_13, nx2686, nx2688, nx2698, nx2700, nx2702, reg_1_q_c_13, nx2726, nx2742, reg_6_q_c_14, reg_2_q_c_14, nx2794, nx2804, nx2814, reg_3_q_c_14, reg_5_q_c_14, nx2842, nx2844, nx2846, nx2858, nx2860, reg_1_q_c_14, nx2884, nx2894, nx2898, nx2900, reg_6_q_c_15, reg_9_q_c_15, nx2932, reg_2_q_c_15, nx2940, reg_10_q_c_15, nx2948, nx2952, nx2962, nx2972, reg_3_q_c_15, nx2986, reg_5_q_c_15, nx3002, nx3004, nx3018, reg_1_q_c_15, nx3052, nx3072, reg_4_q_c_0, nx3080, nx3094, reg_4_q_c_1, nx3096, nx3098, nx3112, reg_4_q_c_2, nx3122, nx3124, nx3138, reg_4_q_c_3, nx3146, nx3148, nx3150, nx3164, reg_4_q_c_4, nx3174, nx3176, nx3190, reg_4_q_c_5, nx3198, nx3200, nx3202, nx3216, reg_4_q_c_6, nx3226, nx3228, nx3242, reg_4_q_c_7, nx3250, nx3252, nx3254, nx3268, reg_4_q_c_8, nx3278, nx3280, nx3294, reg_4_q_c_9, nx3302, nx3304, nx3306, nx3320, reg_4_q_c_10, nx3330, nx3332, nx3346, reg_4_q_c_11, nx3354, nx3356, nx3358, nx3372, reg_4_q_c_12, nx3382, nx3384, nx3398, reg_4_q_c_13, nx3406, nx3408, nx3410, nx3424, reg_4_q_c_14, nx3434, nx3436, nx3450, reg_4_q_c_15, nx3458, nx3462, nx1401, nx1415, nx1417, nx1431, nx1433, nx1447, nx1449, nx1465, nx1467, nx1482, nx1484, nx1497, nx1499, nx1515, nx1517, nx1527, nx1541, nx1549, nx1551, nx1559, nx1569, nx1571, nx1577, nx1579, nx1585, nx1587, nx1605, nx1613, nx1619, nx1623, nx1627, nx1631, nx1637, nx1640, nx1642, nx1643, nx1645, nx1665, nx1673, nx1675, nx1683, nx1691, nx1693, nx1699, nx1702, nx1705, nx1713, nx1719, nx1725, nx1729, nx1735, nx1739, nx1744, nx1747, nx1749, nx1751, nx1771, nx1779, nx1781, nx1787, nx1795, nx1797, nx1801, nx1805, nx1809, nx1819, nx1827, nx1833, nx1837, nx1843, nx1847, nx1851, nx1855, nx1857, nx1858, nx1859, nx1874, nx1883, nx1885, nx1893, nx1901, nx1903, nx1909, nx1913, nx1916, nx1923, nx1931, nx1937, nx1940, nx1945, nx1949, nx1955, nx1958, nx1961, nx1962, nx1963, nx1983, nx1991, nx1993, nx2001, nx2008, nx2010, nx2016, nx2019, nx2023, nx2030, nx2037, nx2043, nx2047, nx2053, nx2057, nx2061, nx2065, nx2067, nx2069, nx2071, nx2089, nx2097, nx2099, nx2105, nx2113, nx2115, nx2120, nx2125, nx2129, nx2139, nx2147, nx2153, nx2157, nx2163, nx2166, nx2171, nx2175, nx2177, nx2178, nx2179, nx2197, nx2203, nx2205, nx2213, nx2219, nx2221, nx2227, nx2231, nx2234, nx2243, nx2251, nx2256, nx2259, nx2265, nx2269, nx2273, nx2277, nx2279, nx2280, nx2281, nx2301, nx2303, nx2311, nx2313, nx2321, nx2326, nx2329, nx2333, nx2336, nx2345, nx2347, nx2365, nx2367, nx2381, nx2383, nx2395, nx2397, nx2413, nx2415, nx2430, nx2432, nx2445, nx2447, nx2463, nx2465, nx2487, nx2505, nx2515, nx2529, nx2531, nx2539, nx2549, nx2565, nx2601, nx2611, nx2623, nx2639, nx2673, nx2675, nx2685, nx2708, nx2746, nx2748, nx2757, nx2769, nx2785, nx2809, nx2820, nx2822, nx2833, nx2845, nx2857, nx2904, nx2915, nx2978, nx2989, nx3013, nx3038, nx3041, nx3043, nx3045, nx3061, nx3063, nx3069, nx3071, nx3073, nx3075, nx3077, nx3079, nx3081, nx3083, nx3085, nx3087, nx3089, nx3091, nx3093, nx3095, nx3097, nx3099, nx3101, nx1534, reg_2_q_c_0, nx1544, reg_5_q_c_0, nx1565, reg_2_q_c_1, nx1593, reg_5_q_c_1, nx1599, nx1565_XX0_XREP3, reg_2_q_c_4, nx1753, reg_5_q_c_4, nx3263, nx3264, nx3265, nx3266, nx3267, nx3269, nx3270, nx3271, nx3272, nx3273, nx3274, nx3275, nx3276, nx3277, nx3279, nx3281, nx3282, nx3283, nx3284, nx3285, nx3286, nx3287, nx3288, nx3289, nx2880, nx3290, nx3059, nx3291, nx3292, nx2951, nx2957, nx3057, nx2564, nx2873, nx2881, nx3055, nx3293, nx3295, nx3296, nx3297, nx3298, nx3299, nx3300, nx3301, nx3303, nx3305, nx3307, nx3308, nx3309, nx3310, nx3311, nx3312, nx3313, nx3314, nx3315, nx3316, nx3317, nx2803, nx3318, nx3053, nx3319, nx3321, nx2727, nx2732, nx3322, nx2653, nx2660, nx3049, nx3323, nx3324, nx3325, nx3326, nx3327, nx3328, PRI_OUT_0_13_EXMPLR, nx3329, nx3331, nx3333, nx3334, nx3335, nx3336, nx3337, nx3338, nx3339, nx3340, nx3341, nx3342, nx3343, nx3344, nx3345, nx3347, nx3348, PRI_OUT_0_14_EXMPLR, nx3349, nx3350, nx3351, nx3352, nx3353, nx3058, nx2968, nx2608, nx3355, nx2740, nx3357, nx3359, nx2893, PRI_OUT_0_12_EXMPLR, nx3360, nx2424, nx3361, PRI_OUT_0_11_EXMPLR, nx3362, nx3363, nx3364, nx3365, nx3366, nx3367, nx3368, nx3369, nx3042, nx3370, nx3371, nx3373, nx3374, nx3375, nx3376, nx3377, nx3378, nx3379, nx3380, nx3381, nx3383, nx3385, nx3386, nx3387, nx3388, nx3389, nx3390, nx3391, nx3392, nx3393, nx3394, nx3395, nx3396, nx3397, nx3399, nx3400, nx3401, nx3402, nx3403, nx3404, nx3405, NOT_nx1932, nx3407, nx3409, nx3411, nx3412, nx3413, nx3414, nx3415, nx3416, nx3417, nx3418, nx1616, nx3419, nx3420, nx3421, nx2694, nx1300, nx3422, nx3051, nx3423, nx2581, nx2588, nx3047, nx3425, nx3426, nx3427, nx3428, nx3429, nx1028, nx2599, nx3430, nx3431, nx3432, nx3433, nx3435, nx3437, nx3438, nx3439, nx3440, nx3441, nx3442, nx3443, nx3444, nx3445, nx3446, nx3447, nx3448, nx3449, nx3451, nx3452, nx3622: std_logic ; begin PRI_OUT_0(15) <= PRI_OUT_0_15_EXMPLR ; PRI_OUT_0(14) <= PRI_OUT_0_14_EXMPLR ; PRI_OUT_0(13) <= PRI_OUT_0_13_EXMPLR ; PRI_OUT_0(12) <= PRI_OUT_0_12_EXMPLR ; PRI_OUT_0(11) <= PRI_OUT_0_11_EXMPLR ; PRI_OUT_0(10) <= PRI_OUT_0_10_EXMPLR ; PRI_OUT_0(8) <= PRI_OUT_0_8_EXMPLR ; PRI_OUT_0(6) <= PRI_OUT_0_6_EXMPLR ; PRI_OUT_0(4) <= PRI_OUT_0_4_EXMPLR ; PRI_OUT_0(2) <= PRI_OUT_0_2_EXMPLR ; PRI_OUT_0(0) <= PRI_OUT_0_0_EXMPLR ; PRI_OUT_4(15) <= PRI_OUT_4_15_EXMPLR ; PRI_OUT_4(14) <= PRI_OUT_4_14_EXMPLR ; PRI_OUT_4(13) <= PRI_OUT_4_13_EXMPLR ; PRI_OUT_4(12) <= PRI_OUT_4_12_EXMPLR ; PRI_OUT_4(11) <= PRI_OUT_4_11_EXMPLR ; PRI_OUT_4(10) <= PRI_OUT_4_10_EXMPLR ; PRI_OUT_4(9) <= PRI_OUT_4_9_EXMPLR ; PRI_OUT_4(8) <= PRI_OUT_4_8_EXMPLR ; PRI_OUT_4(7) <= PRI_OUT_4_7_EXMPLR ; PRI_OUT_4(6) <= PRI_OUT_4_6_EXMPLR ; PRI_OUT_4(5) <= PRI_OUT_4_5_EXMPLR ; PRI_OUT_4(4) <= PRI_OUT_4_4_EXMPLR ; PRI_OUT_4(3) <= PRI_OUT_4_3_EXMPLR ; PRI_OUT_4(2) <= PRI_OUT_4_2_EXMPLR ; PRI_OUT_4(1) <= PRI_OUT_4_1_EXMPLR ; PRI_OUT_4(0) <= PRI_OUT_4_0_EXMPLR ; REG_8_reg_q_0 : dff port map ( Q=>PRI_OUT_4_0_EXMPLR, QB=>OPEN, D=>nx10, CLK=>CLK); ix11 : oai21 port map ( Y=>nx10, A0=>nx1401, A1=>PRI_IN_4(0), B0=>nx2); ix1402 : inv02 port map ( Y=>nx1401, A=>PRI_IN_1(0)); ix3 : nand02 port map ( Y=>nx2, A0=>PRI_IN_4(0), A1=>nx1401); REG_8_reg_q_1 : dff port map ( Q=>PRI_OUT_4_1_EXMPLR, QB=>OPEN, D=>nx20, CLK=>CLK); ix21 : xor2 port map ( Y=>nx20, A0=>nx2, A1=>nx18); ix19 : xnor2 port map ( Y=>nx18, A0=>PRI_IN_1(1), A1=>PRI_IN_4(1)); REG_8_reg_q_2 : dff port map ( Q=>PRI_OUT_4_2_EXMPLR, QB=>OPEN, D=>nx40, CLK=>CLK); ix41 : xnor2 port map ( Y=>nx40, A0=>nx1415, A1=>nx38); ix1416 : aoi22 port map ( Y=>nx1415, A0=>nx1417, A1=>PRI_IN_1(1), B0=>nx2, B1=>nx18); ix1418 : inv02 port map ( Y=>nx1417, A=>PRI_IN_4(1)); ix39 : xnor2 port map ( Y=>nx38, A0=>PRI_IN_1(2), A1=>PRI_IN_4(2)); REG_8_reg_q_3 : dff port map ( Q=>PRI_OUT_4_3_EXMPLR, QB=>OPEN, D=>nx60, CLK=>CLK); ix61 : xor2 port map ( Y=>nx60, A0=>nx56, A1=>nx58); ix57 : mux21 port map ( Y=>nx56, A0=>PRI_IN_4(2), A1=>nx1415, S0=>nx38); ix59 : xnor2 port map ( Y=>nx58, A0=>PRI_IN_1(3), A1=>PRI_IN_4(3)); REG_8_reg_q_4 : dff port map ( Q=>PRI_OUT_4_4_EXMPLR, QB=>OPEN, D=>nx80, CLK=>CLK); ix81 : xnor2 port map ( Y=>nx80, A0=>nx1431, A1=>nx78); ix1432 : aoi22 port map ( Y=>nx1431, A0=>nx1433, A1=>PRI_IN_1(3), B0=> nx56, B1=>nx58); ix1434 : inv02 port map ( Y=>nx1433, A=>PRI_IN_4(3)); ix79 : xnor2 port map ( Y=>nx78, A0=>PRI_IN_1(4), A1=>PRI_IN_4(4)); REG_8_reg_q_5 : dff port map ( Q=>PRI_OUT_4_5_EXMPLR, QB=>OPEN, D=>nx100, CLK=>CLK); ix101 : xor2 port map ( Y=>nx100, A0=>nx96, A1=>nx98); ix97 : mux21 port map ( Y=>nx96, A0=>PRI_IN_4(4), A1=>nx1431, S0=>nx78); ix99 : xnor2 port map ( Y=>nx98, A0=>PRI_IN_1(5), A1=>PRI_IN_4(5)); REG_8_reg_q_6 : dff port map ( Q=>PRI_OUT_4_6_EXMPLR, QB=>OPEN, D=>nx120, CLK=>CLK); ix121 : xnor2 port map ( Y=>nx120, A0=>nx1447, A1=>nx118); ix1448 : aoi22 port map ( Y=>nx1447, A0=>nx1449, A1=>PRI_IN_1(5), B0=> nx96, B1=>nx98); ix1450 : inv02 port map ( Y=>nx1449, A=>PRI_IN_4(5)); ix119 : xnor2 port map ( Y=>nx118, A0=>PRI_IN_1(6), A1=>PRI_IN_4(6)); REG_8_reg_q_7 : dff port map ( Q=>PRI_OUT_4_7_EXMPLR, QB=>OPEN, D=>nx140, CLK=>CLK); ix141 : xor2 port map ( Y=>nx140, A0=>nx136, A1=>nx138); ix137 : mux21 port map ( Y=>nx136, A0=>PRI_IN_4(6), A1=>nx1447, S0=>nx118 ); ix139 : xnor2 port map ( Y=>nx138, A0=>PRI_IN_1(7), A1=>PRI_IN_4(7)); REG_8_reg_q_8 : dff port map ( Q=>PRI_OUT_4_8_EXMPLR, QB=>OPEN, D=>nx160, CLK=>CLK); ix161 : xnor2 port map ( Y=>nx160, A0=>nx1465, A1=>nx158); ix1466 : aoi22 port map ( Y=>nx1465, A0=>nx1467, A1=>PRI_IN_1(7), B0=> nx136, B1=>nx138); ix1468 : inv02 port map ( Y=>nx1467, A=>PRI_IN_4(7)); ix159 : xnor2 port map ( Y=>nx158, A0=>PRI_IN_1(8), A1=>PRI_IN_4(8)); REG_8_reg_q_9 : dff port map ( Q=>PRI_OUT_4_9_EXMPLR, QB=>OPEN, D=>nx180, CLK=>CLK); ix181 : xor2 port map ( Y=>nx180, A0=>nx176, A1=>nx178); ix177 : mux21 port map ( Y=>nx176, A0=>PRI_IN_4(8), A1=>nx1465, S0=>nx158 ); ix179 : xnor2 port map ( Y=>nx178, A0=>PRI_IN_1(9), A1=>PRI_IN_4(9)); REG_8_reg_q_10 : dff port map ( Q=>PRI_OUT_4_10_EXMPLR, QB=>OPEN, D=> nx200, CLK=>CLK); ix201 : xnor2 port map ( Y=>nx200, A0=>nx1482, A1=>nx198); ix1483 : aoi22 port map ( Y=>nx1482, A0=>nx1484, A1=>PRI_IN_1(9), B0=> nx176, B1=>nx178); ix1485 : inv02 port map ( Y=>nx1484, A=>PRI_IN_4(9)); ix199 : xnor2 port map ( Y=>nx198, A0=>PRI_IN_1(10), A1=>PRI_IN_4(10)); REG_8_reg_q_11 : dff port map ( Q=>PRI_OUT_4_11_EXMPLR, QB=>OPEN, D=> nx220, CLK=>CLK); ix221 : xor2 port map ( Y=>nx220, A0=>nx216, A1=>nx218); ix217 : mux21 port map ( Y=>nx216, A0=>PRI_IN_4(10), A1=>nx1482, S0=> nx198); ix219 : xnor2 port map ( Y=>nx218, A0=>PRI_IN_1(11), A1=>PRI_IN_4(11)); REG_8_reg_q_12 : dff port map ( Q=>PRI_OUT_4_12_EXMPLR, QB=>OPEN, D=> nx240, CLK=>CLK); ix241 : xnor2 port map ( Y=>nx240, A0=>nx1497, A1=>nx238); ix1498 : aoi22 port map ( Y=>nx1497, A0=>nx1499, A1=>PRI_IN_1(11), B0=> nx216, B1=>nx218); ix1500 : inv02 port map ( Y=>nx1499, A=>PRI_IN_4(11)); ix239 : xnor2 port map ( Y=>nx238, A0=>PRI_IN_1(12), A1=>PRI_IN_4(12)); REG_8_reg_q_13 : dff port map ( Q=>PRI_OUT_4_13_EXMPLR, QB=>OPEN, D=> nx260, CLK=>CLK); ix261 : xor2 port map ( Y=>nx260, A0=>nx256, A1=>nx258); ix257 : mux21 port map ( Y=>nx256, A0=>PRI_IN_4(12), A1=>nx1497, S0=> nx238); ix259 : xnor2 port map ( Y=>nx258, A0=>PRI_IN_1(13), A1=>PRI_IN_4(13)); REG_8_reg_q_14 : dff port map ( Q=>PRI_OUT_4_14_EXMPLR, QB=>OPEN, D=> nx280, CLK=>CLK); ix281 : xnor2 port map ( Y=>nx280, A0=>nx1515, A1=>nx278); ix1516 : aoi22 port map ( Y=>nx1515, A0=>nx1517, A1=>PRI_IN_1(13), B0=> nx256, B1=>nx258); ix1518 : inv02 port map ( Y=>nx1517, A=>PRI_IN_4(13)); ix279 : xnor2 port map ( Y=>nx278, A0=>PRI_IN_1(14), A1=>PRI_IN_4(14)); REG_8_reg_q_15 : dff port map ( Q=>PRI_OUT_4_15_EXMPLR, QB=>OPEN, D=> nx300, CLK=>CLK); ix301 : xnor2 port map ( Y=>nx300, A0=>nx296, A1=>nx1527); ix297 : mux21 port map ( Y=>nx296, A0=>PRI_IN_4(14), A1=>nx1515, S0=> nx278); ix1528 : xor2 port map ( Y=>nx1527, A0=>PRI_IN_1(15), A1=>PRI_IN_4(15)); ix3091 : ao21 port map ( Y=>PRI_OUT_3(0), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_0, B0=>nx3072); REG_4_reg_q_0 : dff port map ( Q=>reg_4_q_c_0, QB=>OPEN, D=>nx3080, CLK=> CLK); ix3081 : xnor2 port map ( Y=>nx3080, A0=>PRI_OUT_4_0_EXMPLR, A1=>nx3263); ix641 : xor2 port map ( Y=>nx640, A0=>PRI_IN_1(0), A1=>reg_10_q_c_0); REG_10_reg_q_0 : dff port map ( Q=>reg_10_q_c_0, QB=>OPEN, D=>nx626, CLK =>CLK); REG_9_reg_q_0 : dff port map ( Q=>reg_9_q_c_0, QB=>nx1541, D=>nx654, CLK =>CLK); ix677 : ao21 port map ( Y=>nx676, A0=>PRI_IN_2(0), A1=>nx1549, B0=>nx1551 ); ix1550 : inv02 port map ( Y=>nx1549, A=>PRI_IN_3(0)); ix1552 : nor02 port map ( Y=>nx1551, A0=>nx1549, A1=>PRI_IN_2(0)); ix3073 : nor02 port map ( Y=>nx3072, A0=>C_MUX2_4_SEL, A1=>nx1544); ix3109 : ao21 port map ( Y=>PRI_OUT_3(1), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_1, B0=>nx3094); REG_4_reg_q_1 : dff port map ( Q=>reg_4_q_c_1, QB=>OPEN, D=>nx3098, CLK=> CLK); ix3099 : xnor2 port map ( Y=>nx3098, A0=>nx1559, A1=>nx3096); ix1560 : nand02 port map ( Y=>nx1559, A0=>PRI_OUT_4_0_EXMPLR, A1=>nx686); ix3097 : xnor2 port map ( Y=>nx3096, A0=>PRI_OUT_4_1_EXMPLR, A1=>nx1565); ix779 : xor2 port map ( Y=>nx778, A0=>nx1569, A1=>nx1571); ix1570 : nand02 port map ( Y=>nx1569, A0=>PRI_IN_1(0), A1=>reg_10_q_c_0); ix1572 : xnor2 port map ( Y=>nx1571, A0=>PRI_IN_1(1), A1=>reg_10_q_c_1); REG_10_reg_q_1 : dff port map ( Q=>reg_10_q_c_1, QB=>OPEN, D=>nx768, CLK =>CLK); ix769 : xor2 port map ( Y=>nx768, A0=>nx1577, A1=>nx1579); ix1578 : nand02 port map ( Y=>nx1577, A0=>PRI_IN_1(0), A1=>reg_9_q_c_0); ix1580 : xnor2 port map ( Y=>nx1579, A0=>PRI_IN_1(1), A1=>reg_9_q_c_1); REG_9_reg_q_1 : dff port map ( Q=>reg_9_q_c_1, QB=>OPEN, D=>nx788, CLK=> CLK); ix789 : xor2 port map ( Y=>nx788, A0=>nx1585, A1=>nx1587); ix1586 : nand02 port map ( Y=>nx1585, A0=>PRI_IN_3(0), A1=>reg_2_q_c_0); ix803 : xnor2 port map ( Y=>nx802, A0=>nx1551, A1=>nx800); ix801 : xnor2 port map ( Y=>nx800, A0=>PRI_IN_2(1), A1=>PRI_IN_3(1)); ix3095 : nor02 port map ( Y=>nx3094, A0=>C_MUX2_4_SEL, A1=>nx1593); ix3135 : ao21 port map ( Y=>PRI_OUT_3(2), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_2, B0=>nx3112); REG_4_reg_q_2 : dff port map ( Q=>reg_4_q_c_2, QB=>OPEN, D=>nx3124, CLK=> CLK); ix3125 : xnor2 port map ( Y=>nx3124, A0=>nx1605, A1=>nx3122); ix1606 : aoi32 port map ( Y=>nx1605, A0=>PRI_OUT_4_0_EXMPLR, A1=>nx686, A2=>nx3096, B0=>nx812, B1=>PRI_OUT_4_1_EXMPLR); ix3123 : xnor2 port map ( Y=>nx3122, A0=>PRI_OUT_4_2_EXMPLR, A1=>nx3047); ix1614 : mux21 port map ( Y=>nx1613, A0=>reg_2_q_c_2, A1=>nx3430, S0=> C_MUX2_1_SEL); REG_2_reg_q_2 : dff port map ( Q=>reg_2_q_c_2, QB=>nx1645, D=>nx908, CLK =>CLK); ix909 : xor2 port map ( Y=>nx908, A0=>nx1619, A1=>nx1623); ix1620 : aoi32 port map ( Y=>nx1619, A0=>PRI_IN_1(0), A1=>reg_10_q_c_0, A2=>nx776, B0=>reg_10_q_c_1, B1=>PRI_IN_1(1)); REG_10_reg_q_2 : dff port map ( Q=>OPEN, QB=>nx1643, D=>nx898, CLK=>CLK); ix899 : xor2 port map ( Y=>nx898, A0=>nx1627, A1=>nx1631); ix1628 : aoi32 port map ( Y=>nx1627, A0=>PRI_IN_1(0), A1=>reg_9_q_c_0, A2 =>nx766, B0=>reg_9_q_c_1, B1=>PRI_IN_1(1)); REG_9_reg_q_2 : dff port map ( Q=>OPEN, QB=>nx1642, D=>nx918, CLK=>CLK); ix919 : xor2 port map ( Y=>nx918, A0=>nx1637, A1=>nx1640); ix1638 : aoi32 port map ( Y=>nx1637, A0=>PRI_IN_3(0), A1=>reg_2_q_c_0, A2 =>nx786, B0=>reg_2_q_c_1, B1=>PRI_IN_3(1)); REG_5_reg_q_2 : dff port map ( Q=>reg_5_q_c_2, QB=>OPEN, D=>nx950, CLK=> CLK); ix951 : xor2 port map ( Y=>nx950, A0=>nx946, A1=>nx948); ix947 : mux21 port map ( Y=>nx946, A0=>PRI_IN_3(1), A1=>nx1551, S0=>nx800 ); ix949 : xnor2 port map ( Y=>nx948, A0=>PRI_IN_2(2), A1=>PRI_IN_3(2)); ix3113 : nor02 port map ( Y=>nx3112, A0=>C_MUX2_4_SEL, A1=>nx1645); ix3161 : ao21 port map ( Y=>PRI_OUT_3(3), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_3, B0=>nx3138); REG_4_reg_q_3 : dff port map ( Q=>reg_4_q_c_3, QB=>OPEN, D=>nx3150, CLK=> CLK); ix3151 : xor2 port map ( Y=>nx3150, A0=>nx3146, A1=>nx3148); ix3147 : mux21 port map ( Y=>nx3146, A0=>nx3047, A1=>nx1605, S0=>nx3122); ix3149 : xnor2 port map ( Y=>nx3148, A0=>PRI_OUT_4_3_EXMPLR, A1=>nx3432); ix1666 : mux21 port map ( Y=>nx1665, A0=>reg_2_q_c_3, A1=>reg_5_q_c_3, S0 =>C_MUX2_1_SEL); REG_2_reg_q_3 : dff port map ( Q=>reg_2_q_c_3, QB=>nx1699, D=>nx1066, CLK =>CLK); ix1067 : xnor2 port map ( Y=>nx1066, A0=>nx1044, A1=>nx1675); ix1045 : oai22 port map ( Y=>nx1044, A0=>nx1619, A1=>nx1623, B0=>nx1643, B1=>nx1673); ix1674 : inv02 port map ( Y=>nx1673, A=>PRI_IN_1(2)); ix1676 : xnor2 port map ( Y=>nx1675, A0=>PRI_IN_1(3), A1=>reg_10_q_c_3); REG_10_reg_q_3 : dff port map ( Q=>reg_10_q_c_3, QB=>OPEN, D=>nx1056, CLK =>CLK); ix1057 : xnor2 port map ( Y=>nx1056, A0=>nx1052, A1=>nx1683); ix1053 : oai22 port map ( Y=>nx1052, A0=>nx1627, A1=>nx1631, B0=>nx1642, B1=>nx1673); ix1684 : xnor2 port map ( Y=>nx1683, A0=>PRI_IN_1(3), A1=>reg_9_q_c_3); REG_9_reg_q_3 : dff port map ( Q=>reg_9_q_c_3, QB=>OPEN, D=>nx1076, CLK=> CLK); ix1077 : xnor2 port map ( Y=>nx1076, A0=>nx1036, A1=>nx1693); ix1037 : oai22 port map ( Y=>nx1036, A0=>nx1637, A1=>nx1640, B0=>nx1645, B1=>nx1691); ix1692 : inv02 port map ( Y=>nx1691, A=>PRI_IN_3(2)); REG_5_reg_q_3 : dff port map ( Q=>reg_5_q_c_3, QB=>nx1705, D=>nx1108, CLK =>CLK); ix1109 : xnor2 port map ( Y=>nx1108, A0=>nx1702, A1=>nx1106); ix1703 : aoi22 port map ( Y=>nx1702, A0=>nx1691, A1=>PRI_IN_2(2), B0=> nx946, B1=>nx948); ix1107 : xnor2 port map ( Y=>nx1106, A0=>PRI_IN_2(3), A1=>PRI_IN_3(3)); ix3139 : nor02 port map ( Y=>nx3138, A0=>C_MUX2_4_SEL, A1=>nx1699); ix3187 : ao21 port map ( Y=>PRI_OUT_3(4), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_4, B0=>nx3164); REG_4_reg_q_4 : dff port map ( Q=>reg_4_q_c_4, QB=>OPEN, D=>nx3176, CLK=> CLK); ix3177 : xnor2 port map ( Y=>nx3176, A0=>nx1713, A1=>nx3174); ix1714 : aoi22 port map ( Y=>nx1713, A0=>nx1118, A1=>PRI_OUT_4_3_EXMPLR, B0=>nx3146, B1=>nx3148); ix3175 : xnor2 port map ( Y=>nx3174, A0=>PRI_OUT_4_4_EXMPLR, A1=>nx3264); ix1720 : mux21 port map ( Y=>nx1719, A0=>reg_2_q_c_4, A1=>reg_5_q_c_4, S0 =>C_MUX2_1_SEL); ix1225 : xor2 port map ( Y=>nx1224, A0=>nx1725, A1=>nx1729); ix1726 : aoi22 port map ( Y=>nx1725, A0=>reg_10_q_c_3, A1=>PRI_IN_1(3), B0=>nx1044, B1=>nx1064); REG_10_reg_q_4 : dff port map ( Q=>OPEN, QB=>nx1751, D=>nx1214, CLK=>CLK ); ix1215 : xor2 port map ( Y=>nx1214, A0=>nx1735, A1=>nx1739); ix1736 : aoi22 port map ( Y=>nx1735, A0=>reg_9_q_c_3, A1=>PRI_IN_1(3), B0 =>nx1052, B1=>nx1054); REG_9_reg_q_4 : dff port map ( Q=>OPEN, QB=>nx1749, D=>nx1234, CLK=>CLK); ix1235 : xor2 port map ( Y=>nx1234, A0=>nx1744, A1=>nx1747); ix1745 : aoi22 port map ( Y=>nx1744, A0=>reg_2_q_c_3, A1=>PRI_IN_3(3), B0 =>nx1036, B1=>nx1074); ix1267 : xor2 port map ( Y=>nx1266, A0=>nx1262, A1=>nx1264); ix1263 : mux21 port map ( Y=>nx1262, A0=>PRI_IN_3(3), A1=>nx1702, S0=> nx1106); ix1265 : xnor2 port map ( Y=>nx1264, A0=>PRI_IN_2(4), A1=>PRI_IN_3(4)); ix3165 : nor02 port map ( Y=>nx3164, A0=>C_MUX2_4_SEL, A1=>nx1753); ix3213 : ao21 port map ( Y=>PRI_OUT_3(5), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_5, B0=>nx3190); REG_4_reg_q_5 : dff port map ( Q=>reg_4_q_c_5, QB=>OPEN, D=>nx3202, CLK=> CLK); ix3203 : xor2 port map ( Y=>nx3202, A0=>nx3198, A1=>nx3200); ix3199 : mux21 port map ( Y=>nx3198, A0=>nx3264, A1=>nx1713, S0=>nx3174); ix3201 : xnor2 port map ( Y=>nx3200, A0=>PRI_OUT_4_5_EXMPLR, A1=>nx3435); ix1772 : mux21 port map ( Y=>nx1771, A0=>reg_2_q_c_5, A1=>reg_5_q_c_5, S0 =>C_MUX2_1_SEL); REG_2_reg_q_5 : dff port map ( Q=>reg_2_q_c_5, QB=>nx1801, D=>nx1382, CLK =>CLK); ix1383 : xnor2 port map ( Y=>nx1382, A0=>nx1360, A1=>nx1781); ix1361 : oai22 port map ( Y=>nx1360, A0=>nx1725, A1=>nx1729, B0=>nx1751, B1=>nx1779); ix1780 : inv02 port map ( Y=>nx1779, A=>PRI_IN_1(4)); ix1782 : xnor2 port map ( Y=>nx1781, A0=>PRI_IN_1(5), A1=>reg_10_q_c_5); REG_10_reg_q_5 : dff port map ( Q=>reg_10_q_c_5, QB=>OPEN, D=>nx1372, CLK =>CLK); ix1373 : xnor2 port map ( Y=>nx1372, A0=>nx1368, A1=>nx1787); ix1369 : oai22 port map ( Y=>nx1368, A0=>nx1735, A1=>nx1739, B0=>nx1749, B1=>nx1779); ix1788 : xnor2 port map ( Y=>nx1787, A0=>PRI_IN_1(5), A1=>reg_9_q_c_5); REG_9_reg_q_5 : dff port map ( Q=>reg_9_q_c_5, QB=>OPEN, D=>nx1392, CLK=> CLK); ix1393 : xnor2 port map ( Y=>nx1392, A0=>nx1352, A1=>nx1797); ix1353 : oai22 port map ( Y=>nx1352, A0=>nx1744, A1=>nx1747, B0=>nx1753, B1=>nx1795); ix1796 : inv02 port map ( Y=>nx1795, A=>PRI_IN_3(4)); REG_5_reg_q_5 : dff port map ( Q=>reg_5_q_c_5, QB=>nx1809, D=>nx1424, CLK =>CLK); ix1425 : xnor2 port map ( Y=>nx1424, A0=>nx1805, A1=>nx1422); ix1806 : aoi22 port map ( Y=>nx1805, A0=>nx1795, A1=>PRI_IN_2(4), B0=> nx1262, B1=>nx1264); ix1423 : xnor2 port map ( Y=>nx1422, A0=>PRI_IN_2(5), A1=>PRI_IN_3(5)); ix3191 : nor02 port map ( Y=>nx3190, A0=>C_MUX2_4_SEL, A1=>nx1801); ix3239 : ao21 port map ( Y=>PRI_OUT_3(6), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_6, B0=>nx3216); REG_4_reg_q_6 : dff port map ( Q=>reg_4_q_c_6, QB=>OPEN, D=>nx3228, CLK=> CLK); ix3229 : xnor2 port map ( Y=>nx3228, A0=>nx1819, A1=>nx3226); ix1820 : aoi22 port map ( Y=>nx1819, A0=>nx1434, A1=>PRI_OUT_4_5_EXMPLR, B0=>nx3198, B1=>nx3200); ix3227 : xnor2 port map ( Y=>nx3226, A0=>PRI_OUT_4_6_EXMPLR, A1=>nx3051); ix1828 : mux21 port map ( Y=>nx1827, A0=>nx3438, A1=>nx3440, S0=> C_MUX2_1_SEL); REG_2_reg_q_6 : dff port map ( Q=>reg_2_q_c_6, QB=>nx1859, D=>nx1540, CLK =>CLK); ix1541 : xor2 port map ( Y=>nx1540, A0=>nx1833, A1=>nx1837); ix1834 : aoi22 port map ( Y=>nx1833, A0=>reg_10_q_c_5, A1=>PRI_IN_1(5), B0=>nx1360, B1=>nx1380); REG_10_reg_q_6 : dff port map ( Q=>OPEN, QB=>nx1858, D=>nx1530, CLK=>CLK ); ix1531 : xor2 port map ( Y=>nx1530, A0=>nx1843, A1=>nx1847); ix1844 : aoi22 port map ( Y=>nx1843, A0=>reg_9_q_c_5, A1=>PRI_IN_1(5), B0 =>nx1368, B1=>nx1370); REG_9_reg_q_6 : dff port map ( Q=>OPEN, QB=>nx1857, D=>nx1550, CLK=>CLK); ix1551 : xor2 port map ( Y=>nx1550, A0=>nx1851, A1=>nx1855); ix1852 : aoi22 port map ( Y=>nx1851, A0=>reg_2_q_c_5, A1=>PRI_IN_3(5), B0 =>nx1352, B1=>nx1390); REG_5_reg_q_6 : dff port map ( Q=>reg_5_q_c_6, QB=>OPEN, D=>nx1582, CLK=> CLK); ix1583 : xor2 port map ( Y=>nx1582, A0=>nx1578, A1=>nx1580); ix1579 : mux21 port map ( Y=>nx1578, A0=>PRI_IN_3(5), A1=>nx1805, S0=> nx1422); ix1581 : xnor2 port map ( Y=>nx1580, A0=>PRI_IN_2(6), A1=>PRI_IN_3(6)); ix3217 : nor02 port map ( Y=>nx3216, A0=>C_MUX2_4_SEL, A1=>nx1859); ix3265 : ao21 port map ( Y=>PRI_OUT_3(7), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_7, B0=>nx3242); REG_4_reg_q_7 : dff port map ( Q=>reg_4_q_c_7, QB=>OPEN, D=>nx3254, CLK=> CLK); ix3255 : xor2 port map ( Y=>nx3254, A0=>nx3250, A1=>nx3252); ix3251 : mux21 port map ( Y=>nx3250, A0=>nx3051, A1=>nx1819, S0=>nx3226); ix3253 : xnor2 port map ( Y=>nx3252, A0=>PRI_OUT_4_7_EXMPLR, A1=>nx3442); ix1876 : mux21 port map ( Y=>nx1874, A0=>reg_2_q_c_7, A1=>reg_5_q_c_7, S0 =>C_MUX2_1_SEL); REG_2_reg_q_7 : dff port map ( Q=>reg_2_q_c_7, QB=>nx1909, D=>nx1698, CLK =>CLK); ix1699 : xnor2 port map ( Y=>nx1698, A0=>nx1676, A1=>nx1885); ix1677 : oai22 port map ( Y=>nx1676, A0=>nx1833, A1=>nx1837, B0=>nx1858, B1=>nx1883); ix1884 : inv02 port map ( Y=>nx1883, A=>PRI_IN_1(6)); ix1886 : xnor2 port map ( Y=>nx1885, A0=>PRI_IN_1(7), A1=>reg_10_q_c_7); REG_10_reg_q_7 : dff port map ( Q=>reg_10_q_c_7, QB=>OPEN, D=>nx1688, CLK =>CLK); ix1689 : xnor2 port map ( Y=>nx1688, A0=>nx1684, A1=>nx1893); ix1685 : oai22 port map ( Y=>nx1684, A0=>nx1843, A1=>nx1847, B0=>nx1857, B1=>nx1883); ix1894 : xnor2 port map ( Y=>nx1893, A0=>PRI_IN_1(7), A1=>reg_9_q_c_7); REG_9_reg_q_7 : dff port map ( Q=>reg_9_q_c_7, QB=>OPEN, D=>nx1708, CLK=> CLK); ix1709 : xnor2 port map ( Y=>nx1708, A0=>nx1668, A1=>nx1903); ix1669 : oai22 port map ( Y=>nx1668, A0=>nx1851, A1=>nx1855, B0=>nx1859, B1=>nx1901); ix1902 : inv02 port map ( Y=>nx1901, A=>PRI_IN_3(6)); REG_5_reg_q_7 : dff port map ( Q=>reg_5_q_c_7, QB=>nx1916, D=>nx1740, CLK =>CLK); ix1741 : xnor2 port map ( Y=>nx1740, A0=>nx1913, A1=>nx1738); ix1914 : aoi22 port map ( Y=>nx1913, A0=>nx1901, A1=>PRI_IN_2(6), B0=> nx1578, B1=>nx1580); ix1739 : xnor2 port map ( Y=>nx1738, A0=>PRI_IN_2(7), A1=>PRI_IN_3(7)); ix3243 : nor02 port map ( Y=>nx3242, A0=>C_MUX2_4_SEL, A1=>nx1909); ix3291 : ao21 port map ( Y=>PRI_OUT_3(8), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_8, B0=>nx3268); REG_4_reg_q_8 : dff port map ( Q=>reg_4_q_c_8, QB=>OPEN, D=>nx3280, CLK=> CLK); ix3281 : xnor2 port map ( Y=>nx3280, A0=>nx1923, A1=>nx3278); ix1924 : aoi22 port map ( Y=>nx1923, A0=>nx1750, A1=>PRI_OUT_4_7_EXMPLR, B0=>nx3250, B1=>nx3252); ix3279 : xnor2 port map ( Y=>nx3278, A0=>PRI_OUT_4_8_EXMPLR, A1=>nx3053); ix1932 : mux21 port map ( Y=>nx1931, A0=>reg_2_q_c_8, A1=>reg_5_q_c_8, S0 =>C_MUX2_1_SEL); REG_2_reg_q_8 : dff port map ( Q=>reg_2_q_c_8, QB=>nx1963, D=>nx1856, CLK =>CLK); ix1857 : xor2 port map ( Y=>nx1856, A0=>nx1937, A1=>nx1940); ix1938 : aoi22 port map ( Y=>nx1937, A0=>reg_10_q_c_7, A1=>PRI_IN_1(7), B0=>nx1676, B1=>nx1696); REG_10_reg_q_8 : dff port map ( Q=>OPEN, QB=>nx1962, D=>nx1846, CLK=>CLK ); ix1847 : xor2 port map ( Y=>nx1846, A0=>nx1945, A1=>nx1949); ix1946 : aoi22 port map ( Y=>nx1945, A0=>reg_9_q_c_7, A1=>PRI_IN_1(7), B0 =>nx1684, B1=>nx1686); REG_9_reg_q_8 : dff port map ( Q=>OPEN, QB=>nx1961, D=>nx1866, CLK=>CLK); ix1867 : xor2 port map ( Y=>nx1866, A0=>nx1955, A1=>nx1958); ix1956 : aoi22 port map ( Y=>nx1955, A0=>reg_2_q_c_7, A1=>PRI_IN_3(7), B0 =>nx1668, B1=>nx1706); REG_5_reg_q_8 : dff port map ( Q=>reg_5_q_c_8, QB=>OPEN, D=>nx1898, CLK=> CLK); ix1899 : xor2 port map ( Y=>nx1898, A0=>nx1894, A1=>nx1896); ix1895 : mux21 port map ( Y=>nx1894, A0=>PRI_IN_3(7), A1=>nx1913, S0=> nx1738); ix1897 : xnor2 port map ( Y=>nx1896, A0=>PRI_IN_2(8), A1=>PRI_IN_3(8)); ix3269 : nor02 port map ( Y=>nx3268, A0=>C_MUX2_4_SEL, A1=>nx1963); ix3317 : ao21 port map ( Y=>PRI_OUT_3(9), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_9, B0=>nx3294); REG_4_reg_q_9 : dff port map ( Q=>reg_4_q_c_9, QB=>OPEN, D=>nx3306, CLK=> CLK); ix3307 : xor2 port map ( Y=>nx3306, A0=>nx3302, A1=>nx3304); ix3303 : mux21 port map ( Y=>nx3302, A0=>nx3053, A1=>nx1923, S0=>nx3278); ix3305 : xnor2 port map ( Y=>nx3304, A0=>PRI_OUT_4_9_EXMPLR, A1=>nx1983); ix1984 : mux21 port map ( Y=>nx1983, A0=>reg_2_q_c_9, A1=>reg_5_q_c_9, S0 =>C_MUX2_1_SEL); REG_2_reg_q_9 : dff port map ( Q=>reg_2_q_c_9, QB=>nx2016, D=>nx2014, CLK =>CLK); ix2015 : xnor2 port map ( Y=>nx2014, A0=>nx1992, A1=>nx1993); ix1993 : oai22 port map ( Y=>nx1992, A0=>nx1937, A1=>nx1940, B0=>nx1962, B1=>nx1991); ix1992 : inv02 port map ( Y=>nx1991, A=>PRI_IN_1(8)); ix1994 : xnor2 port map ( Y=>nx1993, A0=>PRI_IN_1(9), A1=>reg_10_q_c_9); REG_10_reg_q_9 : dff port map ( Q=>reg_10_q_c_9, QB=>OPEN, D=>nx2004, CLK =>CLK); ix2005 : xnor2 port map ( Y=>nx2004, A0=>nx2000, A1=>nx2001); ix2001 : oai22 port map ( Y=>nx2000, A0=>nx1945, A1=>nx1949, B0=>nx1961, B1=>nx1991); ix2002 : xnor2 port map ( Y=>nx2001, A0=>PRI_IN_1(9), A1=>reg_9_q_c_9); REG_9_reg_q_9 : dff port map ( Q=>reg_9_q_c_9, QB=>OPEN, D=>nx2024, CLK=> CLK); ix2025 : xnor2 port map ( Y=>nx2024, A0=>nx1984, A1=>nx2010); ix1985 : oai22 port map ( Y=>nx1984, A0=>nx1955, A1=>nx1958, B0=>nx1963, B1=>nx2008); ix2009 : inv02 port map ( Y=>nx2008, A=>PRI_IN_3(8)); REG_5_reg_q_9 : dff port map ( Q=>reg_5_q_c_9, QB=>nx2023, D=>nx2056, CLK =>CLK); ix2057 : xnor2 port map ( Y=>nx2056, A0=>nx2019, A1=>nx2054); ix2020 : aoi22 port map ( Y=>nx2019, A0=>nx2008, A1=>PRI_IN_2(8), B0=> nx1894, B1=>nx1896); ix2055 : xnor2 port map ( Y=>nx2054, A0=>PRI_IN_2(9), A1=>PRI_IN_3(9)); ix3295 : nor02 port map ( Y=>nx3294, A0=>C_MUX2_4_SEL, A1=>nx2016); ix3343 : ao21 port map ( Y=>PRI_OUT_3(10), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_10, B0=>nx3320); REG_4_reg_q_10 : dff port map ( Q=>reg_4_q_c_10, QB=>OPEN, D=>nx3332, CLK =>CLK); ix3333 : xnor2 port map ( Y=>nx3332, A0=>nx2030, A1=>nx3330); ix2031 : aoi22 port map ( Y=>nx2030, A0=>nx2066, A1=>PRI_OUT_4_9_EXMPLR, B0=>nx3302, B1=>nx3304); ix3331 : xnor2 port map ( Y=>nx3330, A0=>PRI_OUT_4_10_EXMPLR, A1=>nx3055 ); ix2038 : mux21 port map ( Y=>nx2037, A0=>reg_2_q_c_10, A1=>reg_5_q_c_10, S0=>C_MUX2_1_SEL); REG_2_reg_q_10 : dff port map ( Q=>reg_2_q_c_10, QB=>nx2071, D=>nx2172, CLK=>CLK); ix2173 : xor2 port map ( Y=>nx2172, A0=>nx2043, A1=>nx2047); ix2044 : aoi22 port map ( Y=>nx2043, A0=>reg_10_q_c_9, A1=>PRI_IN_1(9), B0=>nx1992, B1=>nx2012); REG_10_reg_q_10 : dff port map ( Q=>OPEN, QB=>nx2069, D=>nx2162, CLK=>CLK ); ix2163 : xor2 port map ( Y=>nx2162, A0=>nx2053, A1=>nx2057); ix2054 : aoi22 port map ( Y=>nx2053, A0=>reg_9_q_c_9, A1=>PRI_IN_1(9), B0 =>nx2000, B1=>nx2002); REG_9_reg_q_10 : dff port map ( Q=>OPEN, QB=>nx2067, D=>nx2182, CLK=>CLK ); ix2183 : xor2 port map ( Y=>nx2182, A0=>nx2061, A1=>nx2065); ix2062 : aoi22 port map ( Y=>nx2061, A0=>reg_2_q_c_9, A1=>PRI_IN_3(9), B0 =>nx1984, B1=>nx2022); REG_5_reg_q_10 : dff port map ( Q=>reg_5_q_c_10, QB=>OPEN, D=>nx2214, CLK =>CLK); ix2215 : xor2 port map ( Y=>nx2214, A0=>nx2210, A1=>nx2212); ix2211 : mux21 port map ( Y=>nx2210, A0=>PRI_IN_3(9), A1=>nx2019, S0=> nx2054); ix2213 : xnor2 port map ( Y=>nx2212, A0=>PRI_IN_2(10), A1=>PRI_IN_3(10)); ix3321 : nor02 port map ( Y=>nx3320, A0=>C_MUX2_4_SEL, A1=>nx2071); ix3369 : ao21 port map ( Y=>PRI_OUT_3(11), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_11, B0=>nx3346); REG_4_reg_q_11 : dff port map ( Q=>reg_4_q_c_11, QB=>OPEN, D=>nx3358, CLK =>CLK); ix3359 : xor2 port map ( Y=>nx3358, A0=>nx3354, A1=>nx3356); ix3355 : mux21 port map ( Y=>nx3354, A0=>nx3055, A1=>nx2030, S0=>nx3330); ix3357 : xnor2 port map ( Y=>nx3356, A0=>PRI_OUT_4_11_EXMPLR, A1=>nx3444 ); ix2090 : mux21 port map ( Y=>nx2089, A0=>reg_2_q_c_11, A1=>reg_5_q_c_11, S0=>C_MUX2_1_SEL); REG_2_reg_q_11 : dff port map ( Q=>reg_2_q_c_11, QB=>nx2120, D=>nx2330, CLK=>CLK); ix2331 : xnor2 port map ( Y=>nx2330, A0=>nx2308, A1=>nx2099); ix2309 : oai22 port map ( Y=>nx2308, A0=>nx2043, A1=>nx2047, B0=>nx2069, B1=>nx2097); ix2098 : inv02 port map ( Y=>nx2097, A=>PRI_IN_1(10)); ix2100 : xnor2 port map ( Y=>nx2099, A0=>PRI_IN_1(11), A1=>reg_10_q_c_11 ); REG_10_reg_q_11 : dff port map ( Q=>reg_10_q_c_11, QB=>OPEN, D=>nx2320, CLK=>CLK); ix2321 : xnor2 port map ( Y=>nx2320, A0=>nx2316, A1=>nx2105); ix2317 : oai22 port map ( Y=>nx2316, A0=>nx2053, A1=>nx2057, B0=>nx2067, B1=>nx2097); ix2106 : xnor2 port map ( Y=>nx2105, A0=>PRI_IN_1(11), A1=>reg_9_q_c_11); REG_9_reg_q_11 : dff port map ( Q=>reg_9_q_c_11, QB=>OPEN, D=>nx2340, CLK =>CLK); ix2341 : xnor2 port map ( Y=>nx2340, A0=>nx2300, A1=>nx2115); ix2301 : oai22 port map ( Y=>nx2300, A0=>nx2061, A1=>nx2065, B0=>nx2071, B1=>nx2113); ix2114 : inv02 port map ( Y=>nx2113, A=>PRI_IN_3(10)); REG_5_reg_q_11 : dff port map ( Q=>reg_5_q_c_11, QB=>nx2129, D=>nx2372, CLK=>CLK); ix2373 : xnor2 port map ( Y=>nx2372, A0=>nx2125, A1=>nx2370); ix2126 : aoi22 port map ( Y=>nx2125, A0=>nx2113, A1=>PRI_IN_2(10), B0=> nx2210, B1=>nx2212); ix2371 : xnor2 port map ( Y=>nx2370, A0=>PRI_IN_2(11), A1=>PRI_IN_3(11)); ix3347 : nor02 port map ( Y=>nx3346, A0=>C_MUX2_4_SEL, A1=>nx2120); ix3395 : ao21 port map ( Y=>PRI_OUT_3(12), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_12, B0=>nx3372); REG_4_reg_q_12 : dff port map ( Q=>reg_4_q_c_12, QB=>OPEN, D=>nx3384, CLK =>CLK); ix3385 : xnor2 port map ( Y=>nx3384, A0=>nx2139, A1=>nx3382); ix2140 : aoi22 port map ( Y=>nx2139, A0=>nx2382, A1=>PRI_OUT_4_11_EXMPLR, B0=>nx3354, B1=>nx3356); ix3383 : xnor2 port map ( Y=>nx3382, A0=>PRI_OUT_4_12_EXMPLR, A1=>nx3057 ); ix2148 : mux21 port map ( Y=>nx2147, A0=>reg_2_q_c_12, A1=>nx3446, S0=> C_MUX2_1_SEL); REG_2_reg_q_12 : dff port map ( Q=>reg_2_q_c_12, QB=>nx2179, D=>nx2488, CLK=>CLK); ix2489 : xor2 port map ( Y=>nx2488, A0=>nx2153, A1=>nx2157); ix2154 : aoi22 port map ( Y=>nx2153, A0=>reg_10_q_c_11, A1=>PRI_IN_1(11), B0=>nx2308, B1=>nx2328); REG_10_reg_q_12 : dff port map ( Q=>OPEN, QB=>nx2178, D=>nx2478, CLK=>CLK ); ix2479 : xor2 port map ( Y=>nx2478, A0=>nx2163, A1=>nx2166); ix2164 : aoi22 port map ( Y=>nx2163, A0=>reg_9_q_c_11, A1=>PRI_IN_1(11), B0=>nx2316, B1=>nx2318); REG_9_reg_q_12 : dff port map ( Q=>OPEN, QB=>nx2177, D=>nx2498, CLK=>CLK ); ix2499 : xor2 port map ( Y=>nx2498, A0=>nx2171, A1=>nx2175); ix2172 : aoi22 port map ( Y=>nx2171, A0=>reg_2_q_c_11, A1=>PRI_IN_3(11), B0=>nx2300, B1=>nx2338); REG_5_reg_q_12 : dff port map ( Q=>reg_5_q_c_12, QB=>OPEN, D=>nx2530, CLK =>CLK); ix2531 : xor2 port map ( Y=>nx2530, A0=>nx2526, A1=>nx2528); ix2527 : mux21 port map ( Y=>nx2526, A0=>PRI_IN_3(11), A1=>nx2125, S0=> nx2370); ix2529 : xnor2 port map ( Y=>nx2528, A0=>PRI_IN_2(12), A1=>PRI_IN_3(12)); ix3373 : nor02 port map ( Y=>nx3372, A0=>C_MUX2_4_SEL, A1=>nx2179); ix3421 : ao21 port map ( Y=>PRI_OUT_3(13), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_13, B0=>nx3398); REG_4_reg_q_13 : dff port map ( Q=>reg_4_q_c_13, QB=>OPEN, D=>nx3410, CLK =>CLK); ix3411 : xor2 port map ( Y=>nx3410, A0=>nx3406, A1=>nx3408); ix3407 : mux21 port map ( Y=>nx3406, A0=>nx3057, A1=>nx2139, S0=>nx3382); ix3409 : xnor2 port map ( Y=>nx3408, A0=>PRI_OUT_4_13_EXMPLR, A1=>nx3448 ); ix2198 : mux21 port map ( Y=>nx2197, A0=>reg_2_q_c_13, A1=>reg_5_q_c_13, S0=>C_MUX2_1_SEL); REG_2_reg_q_13 : dff port map ( Q=>reg_2_q_c_13, QB=>nx2227, D=>nx2646, CLK=>CLK); ix2647 : xnor2 port map ( Y=>nx2646, A0=>nx2624, A1=>nx2205); ix2625 : oai22 port map ( Y=>nx2624, A0=>nx2153, A1=>nx2157, B0=>nx2178, B1=>nx2203); ix2204 : inv02 port map ( Y=>nx2203, A=>PRI_IN_1(12)); ix2206 : xnor2 port map ( Y=>nx2205, A0=>PRI_IN_1(13), A1=>reg_10_q_c_13 ); REG_10_reg_q_13 : dff port map ( Q=>reg_10_q_c_13, QB=>OPEN, D=>nx2636, CLK=>CLK); ix2637 : xnor2 port map ( Y=>nx2636, A0=>nx2632, A1=>nx2213); ix2633 : oai22 port map ( Y=>nx2632, A0=>nx2163, A1=>nx2166, B0=>nx2177, B1=>nx2203); ix2214 : xnor2 port map ( Y=>nx2213, A0=>PRI_IN_1(13), A1=>reg_9_q_c_13); REG_9_reg_q_13 : dff port map ( Q=>reg_9_q_c_13, QB=>OPEN, D=>nx2656, CLK =>CLK); ix2657 : xnor2 port map ( Y=>nx2656, A0=>nx2616, A1=>nx2221); ix2617 : oai22 port map ( Y=>nx2616, A0=>nx2171, A1=>nx2175, B0=>nx2179, B1=>nx2219); ix2220 : inv02 port map ( Y=>nx2219, A=>PRI_IN_3(12)); REG_5_reg_q_13 : dff port map ( Q=>reg_5_q_c_13, QB=>nx2234, D=>nx2688, CLK=>CLK); ix2689 : xnor2 port map ( Y=>nx2688, A0=>nx2231, A1=>nx2686); ix2232 : aoi22 port map ( Y=>nx2231, A0=>nx2219, A1=>PRI_IN_2(12), B0=> nx2526, B1=>nx2528); ix2687 : xnor2 port map ( Y=>nx2686, A0=>PRI_IN_2(13), A1=>PRI_IN_3(13)); ix3399 : nor02 port map ( Y=>nx3398, A0=>C_MUX2_4_SEL, A1=>nx2227); ix3447 : ao21 port map ( Y=>PRI_OUT_3(14), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_14, B0=>nx3424); REG_4_reg_q_14 : dff port map ( Q=>reg_4_q_c_14, QB=>OPEN, D=>nx3436, CLK =>CLK); ix3437 : xnor2 port map ( Y=>nx3436, A0=>nx2243, A1=>nx3434); ix2244 : aoi22 port map ( Y=>nx2243, A0=>nx2698, A1=>PRI_OUT_4_13_EXMPLR, B0=>nx3406, B1=>nx3408); ix3435 : xnor2 port map ( Y=>nx3434, A0=>PRI_OUT_4_14_EXMPLR, A1=>nx3059 ); ix2252 : mux21 port map ( Y=>nx2251, A0=>reg_2_q_c_14, A1=>reg_5_q_c_14, S0=>C_MUX2_1_SEL); REG_2_reg_q_14 : dff port map ( Q=>reg_2_q_c_14, QB=>nx2281, D=>nx2804, CLK=>CLK); ix2805 : xor2 port map ( Y=>nx2804, A0=>nx2256, A1=>nx2259); ix2257 : aoi22 port map ( Y=>nx2256, A0=>reg_10_q_c_13, A1=>PRI_IN_1(13), B0=>nx2624, B1=>nx2644); REG_10_reg_q_14 : dff port map ( Q=>OPEN, QB=>nx2280, D=>nx2794, CLK=>CLK ); ix2795 : xor2 port map ( Y=>nx2794, A0=>nx2265, A1=>nx2269); ix2266 : aoi22 port map ( Y=>nx2265, A0=>reg_9_q_c_13, A1=>PRI_IN_1(13), B0=>nx2632, B1=>nx2634); REG_9_reg_q_14 : dff port map ( Q=>OPEN, QB=>nx2279, D=>nx2814, CLK=>CLK ); ix2815 : xor2 port map ( Y=>nx2814, A0=>nx2273, A1=>nx2277); ix2274 : aoi22 port map ( Y=>nx2273, A0=>reg_2_q_c_13, A1=>PRI_IN_3(13), B0=>nx2616, B1=>nx2654); REG_5_reg_q_14 : dff port map ( Q=>reg_5_q_c_14, QB=>OPEN, D=>nx2846, CLK =>CLK); ix2847 : xor2 port map ( Y=>nx2846, A0=>nx2842, A1=>nx2844); ix2843 : mux21 port map ( Y=>nx2842, A0=>PRI_IN_3(13), A1=>nx2231, S0=> nx2686); ix2845 : xnor2 port map ( Y=>nx2844, A0=>PRI_IN_2(14), A1=>PRI_IN_3(14)); ix3425 : nor02 port map ( Y=>nx3424, A0=>C_MUX2_4_SEL, A1=>nx2281); ix3473 : ao21 port map ( Y=>PRI_OUT_3(15), A0=>C_MUX2_4_SEL, A1=> reg_4_q_c_15, B0=>nx3450); REG_4_reg_q_15 : dff port map ( Q=>reg_4_q_c_15, QB=>OPEN, D=>nx3462, CLK =>CLK); ix3463 : xnor2 port map ( Y=>nx3462, A0=>nx3458, A1=>nx2301); ix3459 : mux21 port map ( Y=>nx3458, A0=>nx3059, A1=>nx2243, S0=>nx3434); ix2302 : xor2 port map ( Y=>nx2301, A0=>PRI_OUT_4_15_EXMPLR, A1=>nx2303); ix2304 : mux21 port map ( Y=>nx2303, A0=>reg_2_q_c_15, A1=>reg_5_q_c_15, S0=>C_MUX2_1_SEL); REG_2_reg_q_15 : dff port map ( Q=>reg_2_q_c_15, QB=>nx2333, D=>nx2962, CLK=>CLK); ix2963 : xnor2 port map ( Y=>nx2962, A0=>nx2940, A1=>nx2313); ix2941 : oai22 port map ( Y=>nx2940, A0=>nx2256, A1=>nx2259, B0=>nx2280, B1=>nx2311); ix2312 : inv02 port map ( Y=>nx2311, A=>PRI_IN_1(14)); ix2314 : xnor2 port map ( Y=>nx2313, A0=>PRI_IN_1(15), A1=>reg_10_q_c_15 ); REG_10_reg_q_15 : dff port map ( Q=>reg_10_q_c_15, QB=>OPEN, D=>nx2952, CLK=>CLK); ix2953 : xnor2 port map ( Y=>nx2952, A0=>nx2948, A1=>nx2321); ix2949 : oai22 port map ( Y=>nx2948, A0=>nx2265, A1=>nx2269, B0=>nx2279, B1=>nx2311); ix2322 : xnor2 port map ( Y=>nx2321, A0=>PRI_IN_1(15), A1=>reg_9_q_c_15); REG_9_reg_q_15 : dff port map ( Q=>reg_9_q_c_15, QB=>OPEN, D=>nx2972, CLK =>CLK); ix2973 : xnor2 port map ( Y=>nx2972, A0=>nx2932, A1=>nx2329); ix2933 : oai22 port map ( Y=>nx2932, A0=>nx2273, A1=>nx2277, B0=>nx2281, B1=>nx2326); ix2327 : inv02 port map ( Y=>nx2326, A=>PRI_IN_3(14)); REG_5_reg_q_15 : dff port map ( Q=>reg_5_q_c_15, QB=>OPEN, D=>nx3004, CLK =>CLK); ix3005 : xnor2 port map ( Y=>nx3004, A0=>nx2336, A1=>nx3002); ix2337 : aoi22 port map ( Y=>nx2336, A0=>nx2326, A1=>PRI_IN_2(14), B0=> nx2842, B1=>nx2844); ix3003 : xnor2 port map ( Y=>nx3002, A0=>PRI_IN_2(15), A1=>PRI_IN_3(15)); ix3451 : nor02 port map ( Y=>nx3450, A0=>C_MUX2_4_SEL, A1=>nx2333); REG_7_reg_q_0 : dff port map ( Q=>PRI_OUT_2(0), QB=>OPEN, D=>nx318, CLK=> CLK); ix319 : ao21 port map ( Y=>nx318, A0=>nx2345, A1=>PRI_OUT_4_0_EXMPLR, B0 =>nx2347); ix2346 : inv02 port map ( Y=>nx2345, A=>PRI_IN_0(0)); ix2348 : nor02 port map ( Y=>nx2347, A0=>PRI_OUT_4_0_EXMPLR, A1=>nx2345); REG_7_reg_q_1 : dff port map ( Q=>PRI_OUT_2(1), QB=>OPEN, D=>nx328, CLK=> CLK); ix329 : xnor2 port map ( Y=>nx328, A0=>nx2347, A1=>nx326); ix327 : xnor2 port map ( Y=>nx326, A0=>PRI_IN_0(1), A1=> PRI_OUT_4_1_EXMPLR); REG_7_reg_q_2 : dff port map ( Q=>PRI_OUT_2(2), QB=>OPEN, D=>nx348, CLK=> CLK); ix349 : xor2 port map ( Y=>nx348, A0=>nx344, A1=>nx346); ix345 : mux21 port map ( Y=>nx344, A0=>PRI_IN_0(1), A1=>nx2347, S0=>nx326 ); ix347 : xnor2 port map ( Y=>nx346, A0=>PRI_IN_0(2), A1=> PRI_OUT_4_2_EXMPLR); REG_7_reg_q_3 : dff port map ( Q=>PRI_OUT_2(3), QB=>OPEN, D=>nx368, CLK=> CLK); ix369 : xnor2 port map ( Y=>nx368, A0=>nx2365, A1=>nx366); ix2366 : aoi22 port map ( Y=>nx2365, A0=>nx2367, A1=>PRI_OUT_4_2_EXMPLR, B0=>nx344, B1=>nx346); ix2368 : inv02 port map ( Y=>nx2367, A=>PRI_IN_0(2)); ix367 : xnor2 port map ( Y=>nx366, A0=>PRI_IN_0(3), A1=> PRI_OUT_4_3_EXMPLR); REG_7_reg_q_4 : dff port map ( Q=>PRI_OUT_2(4), QB=>OPEN, D=>nx388, CLK=> CLK); ix389 : xor2 port map ( Y=>nx388, A0=>nx384, A1=>nx386); ix385 : mux21 port map ( Y=>nx384, A0=>PRI_IN_0(3), A1=>nx2365, S0=>nx366 ); ix387 : xnor2 port map ( Y=>nx386, A0=>PRI_IN_0(4), A1=> PRI_OUT_4_4_EXMPLR); REG_7_reg_q_5 : dff port map ( Q=>PRI_OUT_2(5), QB=>OPEN, D=>nx408, CLK=> CLK); ix409 : xnor2 port map ( Y=>nx408, A0=>nx2381, A1=>nx406); ix2382 : aoi22 port map ( Y=>nx2381, A0=>nx2383, A1=>PRI_OUT_4_4_EXMPLR, B0=>nx384, B1=>nx386); ix2384 : inv02 port map ( Y=>nx2383, A=>PRI_IN_0(4)); ix407 : xnor2 port map ( Y=>nx406, A0=>PRI_IN_0(5), A1=> PRI_OUT_4_5_EXMPLR); REG_7_reg_q_6 : dff port map ( Q=>PRI_OUT_2(6), QB=>OPEN, D=>nx428, CLK=> CLK); ix429 : xor2 port map ( Y=>nx428, A0=>nx424, A1=>nx426); ix425 : mux21 port map ( Y=>nx424, A0=>PRI_IN_0(5), A1=>nx2381, S0=>nx406 ); ix427 : xnor2 port map ( Y=>nx426, A0=>PRI_IN_0(6), A1=> PRI_OUT_4_6_EXMPLR); REG_7_reg_q_7 : dff port map ( Q=>PRI_OUT_2(7), QB=>OPEN, D=>nx448, CLK=> CLK); ix449 : xnor2 port map ( Y=>nx448, A0=>nx2395, A1=>nx446); ix2396 : aoi22 port map ( Y=>nx2395, A0=>nx2397, A1=>PRI_OUT_4_6_EXMPLR, B0=>nx424, B1=>nx426); ix2398 : inv02 port map ( Y=>nx2397, A=>PRI_IN_0(6)); ix447 : xnor2 port map ( Y=>nx446, A0=>PRI_IN_0(7), A1=> PRI_OUT_4_7_EXMPLR); REG_7_reg_q_8 : dff port map ( Q=>PRI_OUT_2(8), QB=>OPEN, D=>nx468, CLK=> CLK); ix469 : xor2 port map ( Y=>nx468, A0=>nx464, A1=>nx466); ix465 : mux21 port map ( Y=>nx464, A0=>PRI_IN_0(7), A1=>nx2395, S0=>nx446 ); ix467 : xnor2 port map ( Y=>nx466, A0=>PRI_IN_0(8), A1=> PRI_OUT_4_8_EXMPLR); REG_7_reg_q_9 : dff port map ( Q=>PRI_OUT_2(9), QB=>OPEN, D=>nx488, CLK=> CLK); ix489 : xnor2 port map ( Y=>nx488, A0=>nx2413, A1=>nx486); ix2414 : aoi22 port map ( Y=>nx2413, A0=>nx2415, A1=>PRI_OUT_4_8_EXMPLR, B0=>nx464, B1=>nx466); ix2416 : inv02 port map ( Y=>nx2415, A=>PRI_IN_0(8)); ix487 : xnor2 port map ( Y=>nx486, A0=>PRI_IN_0(9), A1=> PRI_OUT_4_9_EXMPLR); REG_7_reg_q_10 : dff port map ( Q=>PRI_OUT_2(10), QB=>OPEN, D=>nx508, CLK =>CLK); ix509 : xor2 port map ( Y=>nx508, A0=>nx504, A1=>nx506); ix505 : mux21 port map ( Y=>nx504, A0=>PRI_IN_0(9), A1=>nx2413, S0=>nx486 ); ix507 : xnor2 port map ( Y=>nx506, A0=>PRI_IN_0(10), A1=> PRI_OUT_4_10_EXMPLR); REG_7_reg_q_11 : dff port map ( Q=>PRI_OUT_2(11), QB=>OPEN, D=>nx528, CLK =>CLK); ix529 : xnor2 port map ( Y=>nx528, A0=>nx2430, A1=>nx526); ix2431 : aoi22 port map ( Y=>nx2430, A0=>nx2432, A1=>PRI_OUT_4_10_EXMPLR, B0=>nx504, B1=>nx506); ix2433 : inv02 port map ( Y=>nx2432, A=>PRI_IN_0(10)); ix527 : xnor2 port map ( Y=>nx526, A0=>PRI_IN_0(11), A1=> PRI_OUT_4_11_EXMPLR); REG_7_reg_q_12 : dff port map ( Q=>PRI_OUT_2(12), QB=>OPEN, D=>nx548, CLK =>CLK); ix549 : xor2 port map ( Y=>nx548, A0=>nx544, A1=>nx546); ix545 : mux21 port map ( Y=>nx544, A0=>PRI_IN_0(11), A1=>nx2430, S0=> nx526); ix547 : xnor2 port map ( Y=>nx546, A0=>PRI_IN_0(12), A1=> PRI_OUT_4_12_EXMPLR); REG_7_reg_q_13 : dff port map ( Q=>PRI_OUT_2(13), QB=>OPEN, D=>nx568, CLK =>CLK); ix569 : xnor2 port map ( Y=>nx568, A0=>nx2445, A1=>nx566); ix2446 : aoi22 port map ( Y=>nx2445, A0=>nx2447, A1=>PRI_OUT_4_12_EXMPLR, B0=>nx544, B1=>nx546); ix2448 : inv02 port map ( Y=>nx2447, A=>PRI_IN_0(12)); ix567 : xnor2 port map ( Y=>nx566, A0=>PRI_IN_0(13), A1=> PRI_OUT_4_13_EXMPLR); REG_7_reg_q_14 : dff port map ( Q=>PRI_OUT_2(14), QB=>OPEN, D=>nx588, CLK =>CLK); ix589 : xor2 port map ( Y=>nx588, A0=>nx584, A1=>nx586); ix585 : mux21 port map ( Y=>nx584, A0=>PRI_IN_0(13), A1=>nx2445, S0=> nx566); ix587 : xnor2 port map ( Y=>nx586, A0=>PRI_IN_0(14), A1=> PRI_OUT_4_14_EXMPLR); REG_7_reg_q_15 : dff port map ( Q=>PRI_OUT_2(15), QB=>OPEN, D=>nx608, CLK =>CLK); ix609 : xnor2 port map ( Y=>nx608, A0=>nx2463, A1=>nx606); ix2464 : aoi22 port map ( Y=>nx2463, A0=>nx2465, A1=>PRI_OUT_4_14_EXMPLR, B0=>nx584, B1=>nx586); ix2466 : inv02 port map ( Y=>nx2465, A=>PRI_IN_0(14)); ix607 : xnor2 port map ( Y=>nx606, A0=>PRI_IN_0(15), A1=> PRI_OUT_4_15_EXMPLR); REG_6_reg_q_0 : dff port map ( Q=>reg_6_q_c_0, QB=>OPEN, D=>nx750, CLK=> CLK); ix751 : oai21 port map ( Y=>nx750, A0=>nx1541, A1=>PRI_OUT_0_0_EXMPLR, B0 =>nx742); ix739 : ao21 port map ( Y=>PRI_OUT_0_0_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_0, B0=>nx736); REG_3_reg_q_0 : dff port map ( Q=>reg_3_q_c_0, QB=>OPEN, D=>nx694, CLK=> CLK); ix695 : xnor2 port map ( Y=>nx694, A0=>reg_6_q_c_0, A1=>nx3263); ix737 : ao32 port map ( Y=>nx736, A0=>reg_5_q_c_0, A1=>nx3061, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_0, B1=>nx3041); REG_1_reg_q_0 : dff port map ( Q=>reg_1_q_c_0, QB=>OPEN, D=>nx720, CLK=> CLK); ix721 : ao21 port map ( Y=>nx720, A0=>reg_5_q_c_0, A1=>nx3263, B0=>nx2487 ); ix2488 : nor03 port map ( Y=>nx2487, A0=>C_MUX2_1_SEL, A1=>reg_5_q_c_0, A2=>nx1544); ix733 : nor02 port map ( Y=>nx732, A0=>C_MUX2_3_SEL, A1=>C_MUX2_2_SEL); ix743 : nand02 port map ( Y=>nx742, A0=>PRI_OUT_0_0_EXMPLR, A1=>nx1541); REG_6_reg_q_1 : dff port map ( Q=>reg_6_q_c_1, QB=>OPEN, D=>nx846, CLK=> CLK); ix847 : xor2 port map ( Y=>nx846, A0=>nx742, A1=>nx844); REG_3_reg_q_1 : dff port map ( Q=>reg_3_q_c_1, QB=>OPEN, D=>nx816, CLK=> CLK); ix817 : xnor2 port map ( Y=>nx816, A0=>nx2505, A1=>nx814); ix2506 : nand02 port map ( Y=>nx2505, A0=>reg_6_q_c_0, A1=>nx686); ix815 : xnor2 port map ( Y=>nx814, A0=>reg_6_q_c_1, A1=>nx1565); REG_1_reg_q_1 : dff port map ( Q=>reg_1_q_c_1, QB=>OPEN, D=>nx830, CLK=> CLK); ix831 : xor2 port map ( Y=>nx830, A0=>nx2487, A1=>nx2515); REG_6_reg_q_2 : dff port map ( Q=>reg_6_q_c_2, QB=>OPEN, D=>nx1004, CLK=> CLK); ix1005 : xnor2 port map ( Y=>nx1004, A0=>nx2529, A1=>nx1002); ix2530 : aoi22 port map ( Y=>nx2529, A0=>nx2531, A1=>reg_9_q_c_1, B0=> nx742, B1=>nx844); ix2532 : aoi222 port map ( Y=>nx2531, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_1, B0=>reg_1_q_c_1, B1=>nx3041, C0=>reg_5_q_c_1, C1=>nx3038); ix707 : and02 port map ( Y=>nx706, A0=>nx3061, A1=>C_MUX2_2_SEL); ix1001 : ao21 port map ( Y=>PRI_OUT_0_2_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_2, B0=>nx998); REG_3_reg_q_2 : dff port map ( Q=>reg_3_q_c_2, QB=>OPEN, D=>nx964, CLK=> CLK); ix965 : xnor2 port map ( Y=>nx964, A0=>nx2539, A1=>nx962); ix2540 : aoi32 port map ( Y=>nx2539, A0=>reg_6_q_c_0, A1=>nx686, A2=> nx814, B0=>nx812, B1=>reg_6_q_c_1); ix963 : xnor2 port map ( Y=>nx962, A0=>reg_6_q_c_2, A1=>nx3047); ix999 : ao32 port map ( Y=>nx998, A0=>nx3430, A1=>nx3061, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_2, B1=>nx3041); REG_1_reg_q_2 : dff port map ( Q=>reg_1_q_c_2, QB=>OPEN, D=>nx988, CLK=> CLK); ix989 : xnor2 port map ( Y=>nx988, A0=>nx984, A1=>nx2549); ix985 : oai32 port map ( Y=>nx984, A0=>C_MUX2_1_SEL, A1=>nx1599, A2=> reg_2_q_c_1, B0=>nx2487, B1=>nx2515); ix2550 : xnor2 port map ( Y=>nx2549, A0=>nx3430, A1=>nx3047); REG_6_reg_q_3 : dff port map ( Q=>reg_6_q_c_3, QB=>OPEN, D=>nx1162, CLK=> CLK); ix1163 : xor2 port map ( Y=>nx1162, A0=>nx1028, A1=>nx1160); REG_3_reg_q_3 : dff port map ( Q=>reg_3_q_c_3, QB=>OPEN, D=>nx1122, CLK=> CLK); ix1123 : xor2 port map ( Y=>nx1122, A0=>nx1090, A1=>nx1120); ix1091 : mux21 port map ( Y=>nx1090, A0=>nx1613, A1=>nx2539, S0=>nx962); ix1121 : xnor2 port map ( Y=>nx1120, A0=>reg_6_q_c_3, A1=>nx3432); REG_1_reg_q_3 : dff port map ( Q=>reg_1_q_c_3, QB=>OPEN, D=>nx1146, CLK=> CLK); ix1147 : xor2 port map ( Y=>nx1146, A0=>nx2581, A1=>nx2588); REG_6_reg_q_4 : dff port map ( Q=>reg_6_q_c_4, QB=>OPEN, D=>nx1320, CLK=> CLK); ix1321 : xnor2 port map ( Y=>nx1320, A0=>nx2599, A1=>nx1318); ix2602 : aoi222 port map ( Y=>nx2601, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_3, B0=>reg_1_q_c_3, B1=>nx3041, C0=>reg_5_q_c_3, C1=>nx3038); ix1317 : ao21 port map ( Y=>PRI_OUT_0_4_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_4, B0=>nx1314); REG_3_reg_q_4 : dff port map ( Q=>reg_3_q_c_4, QB=>OPEN, D=>nx1280, CLK=> CLK); ix1281 : xnor2 port map ( Y=>nx1280, A0=>nx2611, A1=>nx1278); ix2612 : aoi22 port map ( Y=>nx2611, A0=>nx1118, A1=>reg_6_q_c_3, B0=> nx1090, B1=>nx1120); ix1279 : xnor2 port map ( Y=>nx1278, A0=>reg_6_q_c_4, A1=>nx3264); ix1315 : ao32 port map ( Y=>nx1314, A0=>reg_5_q_c_4, A1=>nx3061, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_4, B1=>nx3041); REG_1_reg_q_4 : dff port map ( Q=>reg_1_q_c_4, QB=>OPEN, D=>nx1304, CLK=> CLK); ix1305 : xnor2 port map ( Y=>nx1304, A0=>nx1300, A1=>nx2623); ix2624 : xnor2 port map ( Y=>nx2623, A0=>reg_5_q_c_4, A1=>nx3049); REG_6_reg_q_5 : dff port map ( Q=>reg_6_q_c_5, QB=>OPEN, D=>nx1478, CLK=> CLK); ix1479 : xor2 port map ( Y=>nx1478, A0=>nx1344, A1=>nx1476); ix1345 : oai22 port map ( Y=>nx1344, A0=>nx2599, A1=>nx2639, B0=> PRI_OUT_0_4_EXMPLR, B1=>nx1749); REG_3_reg_q_5 : dff port map ( Q=>reg_3_q_c_5, QB=>OPEN, D=>nx1438, CLK=> CLK); ix1439 : xor2 port map ( Y=>nx1438, A0=>nx1406, A1=>nx1436); ix1407 : mux21 port map ( Y=>nx1406, A0=>nx1719, A1=>nx2611, S0=>nx1278); ix1437 : xnor2 port map ( Y=>nx1436, A0=>reg_6_q_c_5, A1=>nx3435); REG_1_reg_q_5 : dff port map ( Q=>reg_1_q_c_5, QB=>OPEN, D=>nx1462, CLK=> CLK); ix1463 : xor2 port map ( Y=>nx1462, A0=>nx2653, A1=>nx2660); REG_6_reg_q_6 : dff port map ( Q=>reg_6_q_c_6, QB=>OPEN, D=>nx1636, CLK=> CLK); ix1637 : xnor2 port map ( Y=>nx1636, A0=>nx2673, A1=>nx1634); ix2674 : aoi22 port map ( Y=>nx2673, A0=>nx2675, A1=>reg_9_q_c_5, B0=> nx1344, B1=>nx1476); ix2676 : aoi222 port map ( Y=>nx2675, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_5, B0=>reg_1_q_c_5, B1=>nx3043, C0=>reg_5_q_c_5, C1=>nx3038); ix1633 : ao21 port map ( Y=>PRI_OUT_0_6_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_6, B0=>nx1630); REG_3_reg_q_6 : dff port map ( Q=>reg_3_q_c_6, QB=>OPEN, D=>nx1596, CLK=> CLK); ix1597 : xnor2 port map ( Y=>nx1596, A0=>nx2685, A1=>nx1594); ix2686 : aoi22 port map ( Y=>nx2685, A0=>nx1434, A1=>reg_6_q_c_5, B0=> nx1406, B1=>nx1436); ix1595 : xnor2 port map ( Y=>nx1594, A0=>reg_6_q_c_6, A1=>nx3051); ix1631 : ao32 port map ( Y=>nx1630, A0=>nx3440, A1=>nx3061, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_6, B1=>nx3043); REG_1_reg_q_6 : dff port map ( Q=>reg_1_q_c_6, QB=>OPEN, D=>nx1620, CLK=> CLK); ix1621 : xnor2 port map ( Y=>nx1620, A0=>nx1616, A1=>nx2694); REG_6_reg_q_7 : dff port map ( Q=>reg_6_q_c_7, QB=>OPEN, D=>nx1794, CLK=> CLK); ix1795 : xor2 port map ( Y=>nx1794, A0=>nx1660, A1=>nx1792); ix1661 : oai22 port map ( Y=>nx1660, A0=>nx2673, A1=>nx2708, B0=> PRI_OUT_0_6_EXMPLR, B1=>nx1857); REG_3_reg_q_7 : dff port map ( Q=>reg_3_q_c_7, QB=>OPEN, D=>nx1754, CLK=> CLK); ix1755 : xor2 port map ( Y=>nx1754, A0=>nx1722, A1=>nx1752); ix1723 : mux21 port map ( Y=>nx1722, A0=>nx1827, A1=>nx2685, S0=>nx1594); ix1753 : xnor2 port map ( Y=>nx1752, A0=>reg_6_q_c_7, A1=>nx3442); REG_1_reg_q_7 : dff port map ( Q=>reg_1_q_c_7, QB=>OPEN, D=>nx1778, CLK=> CLK); ix1779 : xor2 port map ( Y=>nx1778, A0=>nx2727, A1=>nx2732); REG_6_reg_q_8 : dff port map ( Q=>reg_6_q_c_8, QB=>OPEN, D=>nx1952, CLK=> CLK); ix1953 : xnor2 port map ( Y=>nx1952, A0=>nx2746, A1=>nx1950); ix2747 : aoi22 port map ( Y=>nx2746, A0=>nx2748, A1=>reg_9_q_c_7, B0=> nx1660, B1=>nx1792); ix2749 : aoi222 port map ( Y=>nx2748, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_7, B0=>reg_1_q_c_7, B1=>nx3043, C0=>reg_5_q_c_7, C1=>nx3038); ix1949 : ao21 port map ( Y=>PRI_OUT_0_8_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_8, B0=>nx1946); REG_3_reg_q_8 : dff port map ( Q=>reg_3_q_c_8, QB=>OPEN, D=>nx1912, CLK=> CLK); ix1913 : xnor2 port map ( Y=>nx1912, A0=>nx2757, A1=>nx1910); ix2758 : aoi22 port map ( Y=>nx2757, A0=>nx1750, A1=>reg_6_q_c_7, B0=> nx1722, B1=>nx1752); ix1911 : xnor2 port map ( Y=>nx1910, A0=>reg_6_q_c_8, A1=>nx3053); ix1947 : ao32 port map ( Y=>nx1946, A0=>reg_5_q_c_8, A1=>nx3063, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_8, B1=>nx3043); REG_1_reg_q_8 : dff port map ( Q=>reg_1_q_c_8, QB=>OPEN, D=>nx1936, CLK=> CLK); ix1937 : xnor2 port map ( Y=>nx1936, A0=>nx3319, A1=>nx2769); ix2770 : xnor2 port map ( Y=>nx2769, A0=>reg_5_q_c_8, A1=>nx3053); REG_6_reg_q_9 : dff port map ( Q=>reg_6_q_c_9, QB=>OPEN, D=>nx2110, CLK=> CLK); ix2111 : xor2 port map ( Y=>nx2110, A0=>nx1976, A1=>nx2108); ix1977 : oai22 port map ( Y=>nx1976, A0=>nx2746, A1=>nx2785, B0=> PRI_OUT_0_8_EXMPLR, B1=>nx1961); REG_3_reg_q_9 : dff port map ( Q=>reg_3_q_c_9, QB=>OPEN, D=>nx2070, CLK=> CLK); ix2071 : xor2 port map ( Y=>nx2070, A0=>nx2038, A1=>nx2068); ix2039 : mux21 port map ( Y=>nx2038, A0=>nx1931, A1=>nx2757, S0=>nx1910); ix2069 : xnor2 port map ( Y=>nx2068, A0=>reg_6_q_c_9, A1=>nx1983); REG_1_reg_q_9 : dff port map ( Q=>reg_1_q_c_9, QB=>OPEN, D=>nx2094, CLK=> CLK); ix2095 : xor2 port map ( Y=>nx2094, A0=>nx2803, A1=>nx2809); REG_6_reg_q_10 : dff port map ( Q=>reg_6_q_c_10, QB=>OPEN, D=>nx2268, CLK =>CLK); ix2269 : xnor2 port map ( Y=>nx2268, A0=>nx2820, A1=>nx2266); ix2821 : aoi22 port map ( Y=>nx2820, A0=>nx2822, A1=>reg_9_q_c_9, B0=> nx1976, B1=>nx2108); ix2824 : aoi222 port map ( Y=>nx2822, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_9, B0=>reg_1_q_c_9, B1=>nx3043, C0=>reg_5_q_c_9, C1=>nx3038); ix2265 : ao21 port map ( Y=>PRI_OUT_0_10_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_10, B0=>nx2262); REG_3_reg_q_10 : dff port map ( Q=>reg_3_q_c_10, QB=>OPEN, D=>nx2228, CLK =>CLK); ix2229 : xnor2 port map ( Y=>nx2228, A0=>nx2833, A1=>nx2226); ix2834 : aoi22 port map ( Y=>nx2833, A0=>nx2066, A1=>reg_6_q_c_9, B0=> nx2038, B1=>nx2068); ix2227 : xnor2 port map ( Y=>nx2226, A0=>reg_6_q_c_10, A1=>nx3055); ix2263 : ao32 port map ( Y=>nx2262, A0=>reg_5_q_c_10, A1=>nx3063, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_10, B1=>nx3451); REG_1_reg_q_10 : dff port map ( Q=>reg_1_q_c_10, QB=>OPEN, D=>nx2252, CLK =>CLK); ix2253 : xnor2 port map ( Y=>nx2252, A0=>nx2248, A1=>nx2845); ix2249 : oai32 port map ( Y=>nx2248, A0=>C_MUX2_1_SEL, A1=>nx2023, A2=> reg_2_q_c_9, B0=>nx3318, B1=>nx2809); ix2846 : xnor2 port map ( Y=>nx2845, A0=>reg_5_q_c_10, A1=>nx3055); REG_6_reg_q_11 : dff port map ( Q=>reg_6_q_c_11, QB=>OPEN, D=>nx2426, CLK =>CLK); ix2427 : xor2 port map ( Y=>nx2426, A0=>nx2292, A1=>nx2424); ix2293 : oai22 port map ( Y=>nx2292, A0=>nx2820, A1=>nx2857, B0=> PRI_OUT_0_10_EXMPLR, B1=>nx2067); REG_3_reg_q_11 : dff port map ( Q=>reg_3_q_c_11, QB=>OPEN, D=>nx2386, CLK =>CLK); ix2387 : xor2 port map ( Y=>nx2386, A0=>nx2354, A1=>nx2384); ix2355 : mux21 port map ( Y=>nx2354, A0=>nx2037, A1=>nx2833, S0=>nx2226); ix2385 : xnor2 port map ( Y=>nx2384, A0=>reg_6_q_c_11, A1=>nx3444); REG_1_reg_q_11 : dff port map ( Q=>reg_1_q_c_11, QB=>OPEN, D=>nx2410, CLK =>CLK); ix2411 : xor2 port map ( Y=>nx2410, A0=>nx2873, A1=>nx2881); REG_6_reg_q_12 : dff port map ( Q=>reg_6_q_c_12, QB=>OPEN, D=>nx2584, CLK =>CLK); ix2585 : xnor2 port map ( Y=>nx2584, A0=>nx2893, A1=>nx2582); REG_3_reg_q_12 : dff port map ( Q=>reg_3_q_c_12, QB=>OPEN, D=>nx2544, CLK =>CLK); ix2545 : xnor2 port map ( Y=>nx2544, A0=>nx2904, A1=>nx2542); ix2905 : aoi22 port map ( Y=>nx2904, A0=>nx2382, A1=>reg_6_q_c_11, B0=> nx2354, B1=>nx2384); ix2543 : xnor2 port map ( Y=>nx2542, A0=>reg_6_q_c_12, A1=>nx3057); ix2579 : ao32 port map ( Y=>nx2578, A0=>nx3446, A1=>nx3063, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_12, B1=>nx3451); REG_1_reg_q_12 : dff port map ( Q=>reg_1_q_c_12, QB=>OPEN, D=>nx2568, CLK =>CLK); ix2569 : xnor2 port map ( Y=>nx2568, A0=>nx2564, A1=>nx2915); ix2916 : xnor2 port map ( Y=>nx2915, A0=>nx3446, A1=>nx3057); REG_6_reg_q_13 : dff port map ( Q=>reg_6_q_c_13, QB=>OPEN, D=>nx2742, CLK =>CLK); ix2743 : xor2 port map ( Y=>nx2742, A0=>nx2608, A1=>nx2740); REG_3_reg_q_13 : dff port map ( Q=>reg_3_q_c_13, QB=>OPEN, D=>nx2702, CLK =>CLK); ix2703 : xor2 port map ( Y=>nx2702, A0=>nx2670, A1=>nx2700); ix2671 : mux21 port map ( Y=>nx2670, A0=>nx2147, A1=>nx2904, S0=>nx2542); ix2701 : xnor2 port map ( Y=>nx2700, A0=>reg_6_q_c_13, A1=>nx3448); REG_1_reg_q_13 : dff port map ( Q=>reg_1_q_c_13, QB=>OPEN, D=>nx2726, CLK =>CLK); ix2727 : xor2 port map ( Y=>nx2726, A0=>nx2951, A1=>nx2957); REG_6_reg_q_14 : dff port map ( Q=>reg_6_q_c_14, QB=>OPEN, D=>nx2900, CLK =>CLK); ix2901 : xnor2 port map ( Y=>nx2900, A0=>nx2968, A1=>nx2898); REG_3_reg_q_14 : dff port map ( Q=>reg_3_q_c_14, QB=>OPEN, D=>nx2860, CLK =>CLK); ix2861 : xnor2 port map ( Y=>nx2860, A0=>nx2978, A1=>nx2858); ix2979 : aoi22 port map ( Y=>nx2978, A0=>nx2698, A1=>reg_6_q_c_13, B0=> nx2670, B1=>nx2700); ix2859 : xnor2 port map ( Y=>nx2858, A0=>reg_6_q_c_14, A1=>nx3059); ix2895 : ao32 port map ( Y=>nx2894, A0=>reg_5_q_c_14, A1=>nx3063, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_14, B1=>nx3451); REG_1_reg_q_14 : dff port map ( Q=>reg_1_q_c_14, QB=>OPEN, D=>nx2884, CLK =>CLK); ix2885 : xnor2 port map ( Y=>nx2884, A0=>nx3291, A1=>nx2989); ix2990 : xnor2 port map ( Y=>nx2989, A0=>reg_5_q_c_14, A1=>nx3059); REG_6_reg_q_15 : dff port map ( Q=>reg_6_q_c_15, QB=>OPEN, D=>nx3058, CLK =>CLK); ix3055 : ao21 port map ( Y=>PRI_OUT_0_15_EXMPLR, A0=>C_MUX2_3_SEL, A1=> reg_3_q_c_15, B0=>nx3052); REG_3_reg_q_15 : dff port map ( Q=>reg_3_q_c_15, QB=>OPEN, D=>nx3018, CLK =>CLK); ix3019 : xnor2 port map ( Y=>nx3018, A0=>nx2986, A1=>nx3013); ix2987 : mux21 port map ( Y=>nx2986, A0=>nx2251, A1=>nx2978, S0=>nx2858); ix3014 : xor2 port map ( Y=>nx3013, A0=>reg_6_q_c_15, A1=>nx2303); ix3053 : ao32 port map ( Y=>nx3052, A0=>reg_5_q_c_15, A1=>nx3063, A2=> C_MUX2_2_SEL, B0=>reg_1_q_c_15, B1=>nx732); REG_1_reg_q_15 : dff port map ( Q=>reg_1_q_c_15, QB=>OPEN, D=>nx3042, CLK =>CLK); ix2699 : inv02 port map ( Y=>nx2698, A=>nx3448); ix2655 : inv02 port map ( Y=>nx2654, A=>nx2221); ix2645 : inv02 port map ( Y=>nx2644, A=>nx2205); ix2635 : inv02 port map ( Y=>nx2634, A=>nx2213); ix2383 : inv02 port map ( Y=>nx2382, A=>nx3444); ix2339 : inv02 port map ( Y=>nx2338, A=>nx2115); ix2329 : inv02 port map ( Y=>nx2328, A=>nx2099); ix2319 : inv02 port map ( Y=>nx2318, A=>nx2105); ix2858 : inv02 port map ( Y=>nx2857, A=>nx2266); ix2067 : inv02 port map ( Y=>nx2066, A=>nx1983); ix2023 : inv02 port map ( Y=>nx2022, A=>nx2010); ix2013 : inv02 port map ( Y=>nx2012, A=>nx1993); ix2003 : inv02 port map ( Y=>nx2002, A=>nx2001); ix2786 : inv02 port map ( Y=>nx2785, A=>nx1950); ix1751 : inv02 port map ( Y=>nx1750, A=>nx3442); ix1707 : inv02 port map ( Y=>nx1706, A=>nx1903); ix1697 : inv02 port map ( Y=>nx1696, A=>nx1885); ix1687 : inv02 port map ( Y=>nx1686, A=>nx1893); ix2709 : inv02 port map ( Y=>nx2708, A=>nx1634); ix1435 : inv02 port map ( Y=>nx1434, A=>nx3435); ix1391 : inv02 port map ( Y=>nx1390, A=>nx1797); ix1381 : inv02 port map ( Y=>nx1380, A=>nx1781); ix1371 : inv02 port map ( Y=>nx1370, A=>nx1787); ix2640 : inv02 port map ( Y=>nx2639, A=>nx1318); ix1119 : inv02 port map ( Y=>nx1118, A=>nx3432); ix1075 : inv02 port map ( Y=>nx1074, A=>nx1693); ix1065 : inv02 port map ( Y=>nx1064, A=>nx1675); ix1055 : inv02 port map ( Y=>nx1054, A=>nx1683); ix2566 : inv02 port map ( Y=>nx2565, A=>nx1002); ix813 : inv02 port map ( Y=>nx812, A=>nx1565); ix787 : inv02 port map ( Y=>nx786, A=>nx1587); ix777 : inv02 port map ( Y=>nx776, A=>nx1571); ix767 : inv02 port map ( Y=>nx766, A=>nx1579); ix687 : inv02 port map ( Y=>nx686, A=>nx1534); ix843 : inv02 port map ( Y=>PRI_OUT_0(1), A=>nx2531); ix1159 : inv02 port map ( Y=>PRI_OUT_0(3), A=>nx2601); ix1475 : inv02 port map ( Y=>PRI_OUT_0(5), A=>nx2675); ix1791 : inv02 port map ( Y=>PRI_OUT_0(7), A=>nx2748); ix2107 : inv02 port map ( Y=>PRI_OUT_0(9), A=>nx2822); ix3039 : nor02 port map ( Y=>nx3041, A0=>C_MUX2_3_SEL, A1=>C_MUX2_2_SEL); ix3042 : nor02 port map ( Y=>nx3043, A0=>C_MUX2_3_SEL, A1=>C_MUX2_2_SEL); ix3044 : nor02 port map ( Y=>nx3045, A0=>C_MUX2_3_SEL, A1=>C_MUX2_2_SEL); ix3060 : inv02 port map ( Y=>nx3061, A=>C_MUX2_3_SEL); ix3062 : inv02 port map ( Y=>nx3063, A=>C_MUX2_3_SEL); ix627 : xor2 port map ( Y=>nx626, A0=>PRI_IN_1(0), A1=>reg_9_q_c_0); ix655 : xor2 port map ( Y=>nx654, A0=>PRI_IN_3(0), A1=>reg_2_q_c_0); ix1588 : xor2 port map ( Y=>nx1587, A0=>PRI_IN_3(1), A1=>nx1593); ix1624 : xor2 port map ( Y=>nx1623, A0=>PRI_IN_1(2), A1=>nx1643); ix1632 : xor2 port map ( Y=>nx1631, A0=>PRI_IN_1(2), A1=>nx1642); ix1641 : xor2 port map ( Y=>nx1640, A0=>PRI_IN_3(2), A1=>nx1645); ix1694 : xor2 port map ( Y=>nx1693, A0=>PRI_IN_3(3), A1=>nx1699); ix1730 : xor2 port map ( Y=>nx1729, A0=>PRI_IN_1(4), A1=>nx1751); ix1740 : xor2 port map ( Y=>nx1739, A0=>PRI_IN_1(4), A1=>nx1749); ix1748 : xor2 port map ( Y=>nx1747, A0=>PRI_IN_3(4), A1=>nx1753); ix1798 : xor2 port map ( Y=>nx1797, A0=>PRI_IN_3(5), A1=>nx1801); ix1838 : xor2 port map ( Y=>nx1837, A0=>PRI_IN_1(6), A1=>nx1858); ix1848 : xor2 port map ( Y=>nx1847, A0=>PRI_IN_1(6), A1=>nx1857); ix1856 : xor2 port map ( Y=>nx1855, A0=>PRI_IN_3(6), A1=>nx1859); ix1904 : xor2 port map ( Y=>nx1903, A0=>PRI_IN_3(7), A1=>nx1909); ix1941 : xor2 port map ( Y=>nx1940, A0=>PRI_IN_1(8), A1=>nx1962); ix1950 : xor2 port map ( Y=>nx1949, A0=>PRI_IN_1(8), A1=>nx1961); ix1959 : xor2 port map ( Y=>nx1958, A0=>PRI_IN_3(8), A1=>nx1963); ix2011 : xor2 port map ( Y=>nx2010, A0=>PRI_IN_3(9), A1=>nx2016); ix2048 : xor2 port map ( Y=>nx2047, A0=>PRI_IN_1(10), A1=>nx2069); ix2058 : xor2 port map ( Y=>nx2057, A0=>PRI_IN_1(10), A1=>nx2067); ix2066 : xor2 port map ( Y=>nx2065, A0=>PRI_IN_3(10), A1=>nx2071); ix2116 : xor2 port map ( Y=>nx2115, A0=>PRI_IN_3(11), A1=>nx2120); ix2158 : xor2 port map ( Y=>nx2157, A0=>PRI_IN_1(12), A1=>nx2178); ix2167 : xor2 port map ( Y=>nx2166, A0=>PRI_IN_1(12), A1=>nx2177); ix2176 : xor2 port map ( Y=>nx2175, A0=>PRI_IN_3(12), A1=>nx2179); ix2222 : xor2 port map ( Y=>nx2221, A0=>PRI_IN_3(13), A1=>nx2227); ix2260 : xor2 port map ( Y=>nx2259, A0=>PRI_IN_1(14), A1=>nx2280); ix2270 : xor2 port map ( Y=>nx2269, A0=>PRI_IN_1(14), A1=>nx2279); ix2278 : xor2 port map ( Y=>nx2277, A0=>PRI_IN_3(14), A1=>nx2281); ix2330 : xor2 port map ( Y=>nx2329, A0=>PRI_IN_3(15), A1=>nx2333); ix2495 : mux21 port map ( Y=>PRI_OUT_1(0), A0=>OPEN, A1=>nx3069, S0=> C_MUX2_5_SEL); ix3068 : inv02 port map ( Y=>nx3069, A=>reg_6_q_c_0); ix845 : xor2 port map ( Y=>nx844, A0=>reg_9_q_c_1, A1=>nx2531); ix2516 : xor2 port map ( Y=>nx2515, A0=>nx1599, A1=>nx1565_XX0_XREP3); ix2522 : mux21 port map ( Y=>PRI_OUT_1(1), A0=>OPEN, A1=>nx3071, S0=> C_MUX2_5_SEL); ix3070 : inv02 port map ( Y=>nx3071, A=>reg_6_q_c_1); ix1003 : xor2 port map ( Y=>nx1002, A0=>nx1642, A1=>PRI_OUT_0_2_EXMPLR); ix2556 : mux21 port map ( Y=>PRI_OUT_1(2), A0=>OPEN, A1=>nx3073, S0=> C_MUX2_5_SEL); ix3072 : inv02 port map ( Y=>nx3073, A=>reg_6_q_c_2); ix1161 : xor2 port map ( Y=>nx1160, A0=>reg_9_q_c_3, A1=>nx2601); ix2594 : mux21 port map ( Y=>PRI_OUT_1(3), A0=>OPEN, A1=>nx3075, S0=> C_MUX2_5_SEL); ix3074 : inv02 port map ( Y=>nx3075, A=>reg_6_q_c_3); ix1319 : xor2 port map ( Y=>nx1318, A0=>nx1749, A1=>PRI_OUT_0_4_EXMPLR); ix2630 : mux21 port map ( Y=>PRI_OUT_1(4), A0=>OPEN, A1=>nx3077, S0=> C_MUX2_5_SEL); ix3076 : inv02 port map ( Y=>nx3077, A=>reg_6_q_c_4); ix1477 : xor2 port map ( Y=>nx1476, A0=>reg_9_q_c_5, A1=>nx2675); ix2666 : mux21 port map ( Y=>PRI_OUT_1(5), A0=>OPEN, A1=>nx3079, S0=> C_MUX2_5_SEL); ix3078 : inv02 port map ( Y=>nx3079, A=>reg_6_q_c_5); ix1635 : xor2 port map ( Y=>nx1634, A0=>nx1857, A1=>PRI_OUT_0_6_EXMPLR); ix2702 : mux21 port map ( Y=>PRI_OUT_1(6), A0=>OPEN, A1=>nx3081, S0=> C_MUX2_5_SEL); ix3080 : inv02 port map ( Y=>nx3081, A=>reg_6_q_c_6); ix1793 : xor2 port map ( Y=>nx1792, A0=>reg_9_q_c_7, A1=>nx2748); ix2740 : mux21 port map ( Y=>PRI_OUT_1(7), A0=>OPEN, A1=>nx3083, S0=> C_MUX2_5_SEL); ix3082 : inv02 port map ( Y=>nx3083, A=>reg_6_q_c_7); ix1951 : xor2 port map ( Y=>nx1950, A0=>nx1961, A1=>PRI_OUT_0_8_EXMPLR); ix2776 : mux21 port map ( Y=>PRI_OUT_1(8), A0=>OPEN, A1=>nx3085, S0=> C_MUX2_5_SEL); ix3084 : inv02 port map ( Y=>nx3085, A=>reg_6_q_c_8); ix2109 : xor2 port map ( Y=>nx2108, A0=>reg_9_q_c_9, A1=>nx2822); ix2810 : xor2 port map ( Y=>nx2809, A0=>nx2023, A1=>nx1983); ix2816 : mux21 port map ( Y=>PRI_OUT_1(9), A0=>OPEN, A1=>nx3087, S0=> C_MUX2_5_SEL); ix3086 : inv02 port map ( Y=>nx3087, A=>reg_6_q_c_9); ix2267 : xor2 port map ( Y=>nx2266, A0=>nx2067, A1=>PRI_OUT_0_10_EXMPLR); ix2851 : mux21 port map ( Y=>PRI_OUT_1(10), A0=>OPEN, A1=>nx3089, S0=> C_MUX2_5_SEL); ix3088 : inv02 port map ( Y=>nx3089, A=>reg_6_q_c_10); ix2888 : mux21 port map ( Y=>PRI_OUT_1(11), A0=>OPEN, A1=>nx3091, S0=> C_MUX2_5_SEL); ix3090 : inv02 port map ( Y=>nx3091, A=>reg_6_q_c_11); ix2583 : xor2 port map ( Y=>nx2582, A0=>nx2177, A1=>PRI_OUT_0_12_EXMPLR); ix2922 : mux21 port map ( Y=>PRI_OUT_1(12), A0=>OPEN, A1=>nx3093, S0=> C_MUX2_5_SEL); ix3092 : inv02 port map ( Y=>nx3093, A=>reg_6_q_c_12); ix2964 : mux21 port map ( Y=>PRI_OUT_1(13), A0=>OPEN, A1=>nx3095, S0=> C_MUX2_5_SEL); ix3094 : inv02 port map ( Y=>nx3095, A=>reg_6_q_c_13); ix2899 : xor2 port map ( Y=>nx2898, A0=>nx2279, A1=>PRI_OUT_0_14_EXMPLR); ix2996 : mux21 port map ( Y=>PRI_OUT_1(14), A0=>OPEN, A1=>nx3097, S0=> C_MUX2_5_SEL); ix3096 : inv02 port map ( Y=>nx3097, A=>reg_6_q_c_14); ix3032 : mux21 port map ( Y=>PRI_OUT_1(15), A0=>OPEN, A1=>nx3099, S0=> C_MUX2_5_SEL); ix3098 : inv02 port map ( Y=>nx3099, A=>reg_6_q_c_15); ix3037 : nor02 port map ( Y=>nx3038, A0=>C_MUX2_3_SEL, A1=>nx3101); ix3100 : inv02 port map ( Y=>nx3101, A=>C_MUX2_2_SEL); ix1535 : mux21 port map ( Y=>nx1534, A0=>reg_2_q_c_0, A1=>reg_5_q_c_0, S0 =>C_MUX2_1_SEL); REG_2_reg_q_0 : dff port map ( Q=>reg_2_q_c_0, QB=>nx1544, D=>nx640, CLK =>CLK); REG_5_reg_q_0 : dff port map ( Q=>reg_5_q_c_0, QB=>OPEN, D=>nx676, CLK=> CLK); ix1566 : mux21 port map ( Y=>nx1565, A0=>reg_2_q_c_1, A1=>reg_5_q_c_1, S0 =>C_MUX2_1_SEL); REG_2_reg_q_1 : dff port map ( Q=>reg_2_q_c_1, QB=>nx1593, D=>nx778, CLK =>CLK); REG_5_reg_q_1 : dff port map ( Q=>reg_5_q_c_1, QB=>nx1599, D=>nx802, CLK =>CLK); ix1566_0_XREP3 : mux21 port map ( Y=>nx1565_XX0_XREP3, A0=>reg_2_q_c_1, A1=>reg_5_q_c_1, S0=>C_MUX2_1_SEL); REG_2_reg_q_4 : dff port map ( Q=>reg_2_q_c_4, QB=>nx1753, D=>nx1224, CLK =>CLK); REG_5_reg_q_4 : dff port map ( Q=>reg_5_q_c_4, QB=>OPEN, D=>nx1266, CLK=> CLK); ix3453 : buf04 port map ( Y=>nx3263, A=>nx1534); ix3454 : buf04 port map ( Y=>nx3264, A=>nx3049); ix3455 : inv02 port map ( Y=>nx3265, A=>reg_2_q_c_14); ix3456 : inv02 port map ( Y=>nx3266, A=>C_MUX2_1_SEL); ix3457 : nand03 port map ( Y=>nx3267, A0=>nx3265, A1=>reg_5_q_c_14, A2=> nx3293); ix3458 : inv02 port map ( Y=>nx3269, A=>nx3445); ix3460 : nand02 port map ( Y=>nx3270, A0=>reg_5_q_c_10, A1=>nx3269); ix3461 : oai21 port map ( Y=>nx3271, A0=>reg_2_q_c_10, A1=>nx3270, B0=> reg_2_q_c_11); ix3462 : inv02 port map ( Y=>nx3272, A=>nx2129); ix3464 : oai22 port map ( Y=>nx3273, A0=>nx3272, A1=>nx3269, B0=>nx2129, B1=>nx3445); ix3465 : inv02 port map ( Y=>nx3274, A=>nx2845); ix3466 : and02 port map ( Y=>nx3275, A0=>nx2129, A1=>nx3445); ix3467 : inv02 port map ( Y=>nx3276, A=>reg_5_q_c_10); ix3468 : nor03 port map ( Y=>nx3277, A0=>reg_2_q_c_10, A1=>nx3276, A2=> C_MUX2_1_SEL); ix3469 : aoi332 port map ( Y=>nx3279, A0=>nx3271, A1=>nx3293, A2=>nx3272, B0=>nx2248, B1=>nx3273, B2=>nx3274, C0=>nx3275, C1=>nx3277); ix3470 : inv02 port map ( Y=>nx3281, A=>nx2234); ix3471 : inv02 port map ( Y=>nx3282, A=>nx3449); ix3472 : aoi22 port map ( Y=>nx3283, A0=>nx2234, A1=>nx3449, B0=>nx3281, B1=>nx3282); ix3474 : inv02 port map ( Y=>nx3284, A=>reg_2_q_c_12); ix3475 : and02 port map ( Y=>nx3285, A0=>nx3447, A1=>nx3282); ix3476 : inv02 port map ( Y=>nx3286, A=>reg_2_q_c_13); ix3477 : aoi21 port map ( Y=>nx3287, A0=>nx3284, A1=>nx3285, B0=>nx3286); ix3478 : nand02 port map ( Y=>nx3288, A0=>nx2234, A1=>nx3447); ix3479 : nand03 port map ( Y=>nx3289, A0=>nx3284, A1=>nx3449, A2=>nx3293 ); nx2880_EXMPLR : oai332 port map ( Y=>nx2880, A0=>nx3279, A1=>nx3283, A2=> nx2915, B0=>nx3287, B1=>C_MUX2_1_SEL, B2=>nx2234, C0=>nx3288, C1=> nx3289); ix3480 : inv01 port map ( Y=>nx3290, A=>nx2880); nx3059_EXMPLR : oai22 port map ( Y=>nx3059, A0=>reg_2_q_c_14, A1=> C_MUX2_1_SEL, B0=>nx3295, B1=>reg_5_q_c_14); ix3481 : inv01 port map ( Y=>nx3291, A=>nx3290); ix3482 : nand03 port map ( Y=>nx3292, A0=>nx3284, A1=>nx3447, A2=>nx3295 ); nx2951_EXMPLR : ao22 port map ( Y=>nx2951, A0=>nx3292, A1=>nx3279, B0=> nx2915, B1=>nx3292); nx2957_EXMPLR : oai22 port map ( Y=>nx2957, A0=>nx3282, A1=>nx2234, B0=> nx3281, B1=>nx3449); nx3057_EXMPLR : oai22 port map ( Y=>nx3057, A0=>C_MUX2_1_SEL, A1=> reg_2_q_c_12, B0=>nx3295, B1=>nx3447); nx2564_EXMPLR : inv01 port map ( Y=>nx2564, A=>nx3279); nx2873_EXMPLR : oai22 port map ( Y=>nx2873, A0=>nx3277, A1=>nx2248, B0=> nx3274, B1=>nx3277); nx2881_EXMPLR : oai22 port map ( Y=>nx2881, A0=>nx3269, A1=>nx2129, B0=> nx3272, B1=>nx3445); nx3055_EXMPLR : oai22 port map ( Y=>nx3055, A0=>C_MUX2_1_SEL, A1=> reg_2_q_c_10, B0=>nx3295, B1=>reg_5_q_c_10); ix3483 : buf04 port map ( Y=>nx3293, A=>nx3266); ix3484 : buf04 port map ( Y=>nx3295, A=>nx3266); ix3485 : inv02 port map ( Y=>nx3296, A=>reg_2_q_c_8); ix3486 : inv01 port map ( Y=>nx3297, A=>C_MUX2_1_SEL); ix3487 : nand03 port map ( Y=>nx3298, A0=>nx3296, A1=>reg_5_q_c_8, A2=> nx3323); ix3488 : inv01 port map ( Y=>nx3299, A=>nx3437); ix3489 : nand02 port map ( Y=>nx3300, A0=>reg_5_q_c_4, A1=>nx3299); ix3490 : inv01 port map ( Y=>nx3301, A=>nx1809); ix3491 : aoi22 port map ( Y=>nx3303, A0=>nx1809, A1=>nx3437, B0=>nx3301, B1=>nx3299); ix3492 : and02 port map ( Y=>nx3305, A0=>nx1809, A1=>nx3437); ix3493 : inv01 port map ( Y=>nx3307, A=>reg_5_q_c_4); ix3494 : nor03 port map ( Y=>nx3308, A0=>reg_2_q_c_4, A1=>nx3307, A2=> C_MUX2_1_SEL); ix3495 : inv01 port map ( Y=>nx3309, A=>nx1916); ix3496 : inv01 port map ( Y=>nx3310, A=>nx3443); ix3497 : aoi22 port map ( Y=>nx3311, A0=>nx1916, A1=>nx3443, B0=>nx3309, B1=>nx3310); ix3498 : inv01 port map ( Y=>nx3312, A=>nx3438); ix3499 : and02 port map ( Y=>nx3313, A0=>nx3440, A1=>nx3310); ix3500 : inv01 port map ( Y=>nx3314, A=>reg_2_q_c_7); ix3501 : nand02 port map ( Y=>nx3315, A0=>nx1916, A1=>nx3440); ix3502 : nand03 port map ( Y=>nx3316, A0=>nx3312, A1=>nx3443, A2=>nx3323 ); ix3503 : aoi22 port map ( Y=>nx3317, A0=>nx3298, A1=>NOT_nx1932, B0=> nx2769, B1=>nx3298); nx2803_EXMPLR : inv01 port map ( Y=>nx2803, A=>nx3317); ix3504 : inv01 port map ( Y=>nx3318, A=>nx3317); nx3053_EXMPLR : oai22 port map ( Y=>nx3053, A0=>reg_2_q_c_8, A1=> C_MUX2_1_SEL, B0=>nx3324, B1=>reg_5_q_c_8); ix3505 : inv02 port map ( Y=>nx3319, A=>NOT_nx1932); ix3506 : nand03 port map ( Y=>nx3321, A0=>nx3312, A1=>nx3441, A2=>nx3324 ); nx2727_EXMPLR : ao22 port map ( Y=>nx2727, A0=>nx3321, A1=>nx3419, B0=> nx2694, B1=>nx3321); nx2732_EXMPLR : oai22 port map ( Y=>nx2732, A0=>nx3310, A1=>nx1916, B0=> nx3309, B1=>nx3443); ix3507 : inv02 port map ( Y=>nx3322, A=>nx2623); nx2653_EXMPLR : oai22 port map ( Y=>nx2653, A0=>nx3622, A1=>nx3422, B0=> nx3322, B1=>nx3622); nx2660_EXMPLR : oai22 port map ( Y=>nx2660, A0=>nx3299, A1=>nx1809, B0=> nx3301, B1=>nx3437); nx3049_EXMPLR : oai22 port map ( Y=>nx3049, A0=>C_MUX2_1_SEL, A1=> reg_2_q_c_4, B0=>nx3324, B1=>reg_5_q_c_4); ix3508 : buf04 port map ( Y=>nx3323, A=>nx3297); ix3509 : buf04 port map ( Y=>nx3324, A=>nx3297); ix3510 : inv02 port map ( Y=>nx3325, A=>reg_9_q_c_13); ix3511 : oai22 port map ( Y=>nx3326, A0=>nx706, A1=>nx3452, B0=> reg_5_q_c_13, B1=>nx3452); ix3512 : nand02 port map ( Y=>nx3327, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_13 ); ix3513 : aoi21 port map ( Y=>nx3328, A0=>reg_5_q_c_13, A1=>nx706, B0=> reg_1_q_c_13); nx2971 : aoi22 port map ( Y=>PRI_OUT_0_13_EXMPLR, A0=>nx3326, A1=>nx3327, B0=>nx3327, B1=>nx3328); ix3514 : or02 port map ( Y=>nx3329, A0=>nx3325, A1=>PRI_OUT_0_13_EXMPLR); ix3515 : inv02 port map ( Y=>nx3331, A=>nx2582); ix3516 : oai22 port map ( Y=>nx3333, A0=>nx3452, A1=>reg_5_q_c_11, B0=> nx706, B1=>nx3452); ix3517 : nand02 port map ( Y=>nx3334, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_11 ); ix3518 : aoi221 port map ( Y=>nx3335, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_11, B0=>nx706, B1=>reg_5_q_c_11, C0=>reg_1_q_c_11); ix3519 : aoi21 port map ( Y=>nx3336, A0=>nx3333, A1=>nx3334, B0=>nx3335); ix3520 : inv02 port map ( Y=>nx3337, A=>reg_9_q_c_11); ix3521 : oai22 port map ( Y=>nx3338, A0=>nx3331, A1=>nx3361, B0=>nx3337, B1=>nx3331); ix3522 : and02 port map ( Y=>nx3339, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_12); ix3523 : oai33 port map ( Y=>nx3340, A0=>nx3361, A1=>nx3337, A2=>nx3331, B0=>nx3339, B1=>nx2177, B2=>nx2578); ix3524 : aoi21 port map ( Y=>nx3341, A0=>nx2292, A1=>nx3338, B0=>nx3340); ix3525 : aoi22 port map ( Y=>nx3342, A0=>nx3329, A1=>nx3341, B0=>nx3325, B1=>PRI_OUT_0_13_EXMPLR); ix3526 : inv02 port map ( Y=>nx3343, A=>nx2898); ix3527 : inv02 port map ( Y=>nx3344, A=>reg_9_q_c_15); ix3528 : inv02 port map ( Y=>nx3345, A=>PRI_OUT_0_15_EXMPLR); ix3529 : aoi22 port map ( Y=>nx3347, A0=>PRI_OUT_0_15_EXMPLR, A1=>nx3344, B0=>reg_9_q_c_15, B1=>nx3345); ix3530 : nor02 port map ( Y=>nx3348, A0=>nx3343, A1=>nx3347); PRI_OUT_0_14_EXMPLR_EXMPLR : ao21 port map ( Y=>PRI_OUT_0_14_EXMPLR, A0=> C_MUX2_3_SEL, A1=>reg_3_q_c_14, B0=>nx2894); ix3531 : aoi22 port map ( Y=>nx3349, A0=>nx2279, A1=>nx3347, B0=> PRI_OUT_0_14_EXMPLR, B1=>nx3347); ix3532 : inv02 port map ( Y=>nx3350, A=>nx2279); ix3533 : aoi21 port map ( Y=>nx3351, A0=>C_MUX2_3_SEL, A1=>reg_3_q_c_14, B0=>nx2894); ix3534 : nand02 port map ( Y=>nx3352, A0=>nx3350, A1=>nx3351); ix3535 : oai222 port map ( Y=>nx3353, A0=>nx3349, A1=>nx2898, B0=>nx3347, B1=>nx3352, C0=>nx3342, C1=>nx3349); nx3058_EXMPLR : ao21 port map ( Y=>nx3058, A0=>nx3342, A1=>nx3348, B0=> nx3353); nx2968_EXMPLR : inv01 port map ( Y=>nx2968, A=>nx3342); nx2608_EXMPLR : inv01 port map ( Y=>nx2608, A=>nx3341); ix3536 : nand02 port map ( Y=>nx3355, A0=>reg_9_q_c_13, A1=> PRI_OUT_0_13_EXMPLR); nx2740_EXMPLR : oai21 port map ( Y=>nx2740, A0=>PRI_OUT_0_13_EXMPLR, A1=> reg_9_q_c_13, B0=>nx3355); ix3537 : nor02 port map ( Y=>nx3357, A0=>nx3337, A1=>nx3361); ix3538 : nand02 port map ( Y=>nx3359, A0=>PRI_OUT_0_11_EXMPLR, A1=>nx3337 ); nx2893_EXMPLR : oai21 port map ( Y=>nx2893, A0=>nx3357, A1=>nx2292, B0=> nx3359); PRI_OUT_0_12_EXMPLR_EXMPLR : ao21 port map ( Y=>PRI_OUT_0_12_EXMPLR, A0=> C_MUX2_3_SEL, A1=>reg_3_q_c_12, B0=>nx2578); ix3539 : nand02 port map ( Y=>nx3360, A0=>reg_9_q_c_11, A1=> PRI_OUT_0_11_EXMPLR); nx2424_EXMPLR : oai21 port map ( Y=>nx2424, A0=>PRI_OUT_0_11_EXMPLR, A1=> reg_9_q_c_11, B0=>nx3360); ix3540 : buf04 port map ( Y=>nx3361, A=>nx3336); nx2895 : buf04 port map ( Y=>PRI_OUT_0_11_EXMPLR, A=>nx3336); ix3541 : inv02 port map ( Y=>nx3362, A=>nx2989); ix3542 : inv02 port map ( Y=>nx3363, A=>reg_5_q_c_15); ix3543 : inv02 port map ( Y=>nx3364, A=>nx2303); ix3544 : aoi22 port map ( Y=>nx3365, A0=>nx2303, A1=>nx3363, B0=> reg_5_q_c_15, B1=>nx3364); ix3545 : nand02 port map ( Y=>nx3366, A0=>nx3362, A1=>nx3365); ix3546 : inv02 port map ( Y=>nx3367, A=>nx3267); ix3547 : nor02 port map ( Y=>nx3368, A0=>nx3367, A1=>nx3365); ix3548 : aoi222 port map ( Y=>nx3369, A0=>nx2989, A1=>nx3368, B0=>nx3365, B1=>nx3367, C0=>nx3290, C1=>nx3368); nx3042_EXMPLR : oai21 port map ( Y=>nx3042, A0=>nx3290, A1=>nx3366, B0=> nx3369); ix3549 : inv01 port map ( Y=>nx3370, A=>nx3433); ix3550 : nand02 port map ( Y=>nx3371, A0=>nx3431, A1=>nx3370); ix3551 : oai21 port map ( Y=>nx3373, A0=>reg_2_q_c_2, A1=>nx3371, B0=> reg_2_q_c_3); ix3552 : inv01 port map ( Y=>nx3374, A=>nx1705); ix3553 : inv01 port map ( Y=>nx3375, A=>C_MUX2_1_SEL); ix3554 : oai22 port map ( Y=>nx3376, A0=>nx3374, A1=>nx3370, B0=>nx1705, B1=>nx3433); ix3555 : inv01 port map ( Y=>nx3377, A=>nx2549); ix3556 : and02 port map ( Y=>nx3378, A0=>nx984, A1=>nx3377); ix3557 : and02 port map ( Y=>nx3379, A0=>nx1705, A1=>nx3433); ix3558 : inv01 port map ( Y=>nx3380, A=>nx3431); ix3559 : nor03 port map ( Y=>nx3381, A0=>reg_2_q_c_2, A1=>nx3380, A2=> C_MUX2_1_SEL); ix3560 : aoi322 port map ( Y=>nx3383, A0=>nx3373, A1=>nx3374, A2=>nx3375, B0=>nx3376, B1=>nx3378, C0=>nx3379, C1=>nx3381); ix3561 : nor02 port map ( Y=>nx3385, A0=>nx3303, A1=>nx2623); ix3562 : inv01 port map ( Y=>nx3386, A=>nx3311); ix3563 : or02 port map ( Y=>nx3387, A0=>C_MUX2_1_SEL, A1=>nx3438); ix3564 : inv01 port map ( Y=>nx3388, A=>nx3441); ix3565 : inv01 port map ( Y=>nx3389, A=>nx3439); ix3566 : aoi33 port map ( Y=>nx3390, A0=>nx3387, A1=>nx3324, A2=>nx3388, B0=>nx3389, B1=>nx3441, B2=>nx3375); ix3567 : nand03 port map ( Y=>nx3391, A0=>nx3427, A1=>nx3386, A2=>nx3390 ); ix3568 : or02 port map ( Y=>nx3392, A0=>nx3425, A1=>nx3391); ix3569 : ao21 port map ( Y=>nx3393, A0=>nx3312, A1=>nx3313, B0=>nx3314); ix3570 : inv01 port map ( Y=>nx3394, A=>nx1916); ix3571 : oai21 port map ( Y=>nx3395, A0=>reg_2_q_c_4, A1=>nx3300, B0=> reg_2_q_c_5); ix3572 : inv01 port map ( Y=>nx3396, A=>nx3395); ix3573 : inv02 port map ( Y=>nx3397, A=>nx3323); ix3574 : inv01 port map ( Y=>nx3399, A=>nx3301); ix3575 : inv01 port map ( Y=>nx3400, A=>nx3305); ix3576 : inv01 port map ( Y=>nx3401, A=>nx3308); ix3577 : oai32 port map ( Y=>nx3402, A0=>nx3396, A1=>nx3397, A2=>nx3399, B0=>nx3400, B1=>nx3401); ix3578 : and02 port map ( Y=>nx3403, A0=>nx3386, A1=>nx3390); ix3579 : nor02 port map ( Y=>nx3404, A0=>nx3315, A1=>nx3316); ix3580 : aoi321 port map ( Y=>nx3405, A0=>nx3393, A1=>nx3375, A2=>nx3394, B0=>nx3402, B1=>nx3403, C0=>nx3404); NOT_nx1932_EXMPLR : and02 port map ( Y=>NOT_nx1932, A0=>nx3392, A1=> nx3405); ix3581 : aoi33 port map ( Y=>nx3407, A0=>nx3425, A1=>nx3401, A2=>nx3399, B0=>nx3425, B1=>nx3400, B2=>nx3396); ix3582 : nor02 port map ( Y=>nx3409, A0=>nx3305, A1=>nx3301); ix3583 : aoi32 port map ( Y=>nx3411, A0=>nx3426, A1=>nx3401, A2=>nx3397, B0=>nx3425, B1=>nx3409); ix3584 : nand03 port map ( Y=>nx3412, A0=>nx3426, A1=>nx3401, A2=>nx3396 ); ix3585 : nor02 port map ( Y=>nx3413, A0=>nx3427, A1=>nx3622); ix3586 : nor03 port map ( Y=>nx3414, A0=>nx3395, A1=>nx3427, A2=>nx3305); ix3587 : oai33 port map ( Y=>nx3415, A0=>nx3428, A1=>nx3622, A2=>nx3323, B0=>nx3428, B1=>nx3622, B2=>nx3301); ix3588 : oai33 port map ( Y=>nx3416, A0=>nx3428, A1=>nx3305, A2=>nx3323, B0=>nx3428, B1=>nx3305, B2=>nx3301); ix3589 : or03 port map ( Y=>nx3417, A0=>nx3414, A1=>nx3415, A2=>nx3416); ix3590 : aoi321 port map ( Y=>nx3418, A0=>nx3426, A1=>nx3400, A2=>nx3397, B0=>nx3396, B1=>nx3413, C0=>nx3417); nx1616_EXMPLR : and04 port map ( Y=>nx1616, A0=>nx3407, A1=>nx3411, A2=> nx3412, A3=>nx3418); ix3591 : inv02 port map ( Y=>nx3419, A=>nx1616); ix3592 : nor02 port map ( Y=>nx3420, A0=>C_MUX2_1_SEL, A1=>nx3439); ix3593 : inv02 port map ( Y=>nx3421, A=>nx3324); nx2694_EXMPLR : oai33 port map ( Y=>nx2694, A0=>nx3420, A1=>nx3421, A2=> nx3441, B0=>nx3439, B1=>nx3388, B2=>C_MUX2_1_SEL); nx1300_EXMPLR : inv02 port map ( Y=>nx1300, A=>nx3426); ix3594 : inv02 port map ( Y=>nx3422, A=>nx3426); nx3051_EXMPLR : oai22 port map ( Y=>nx3051, A0=>C_MUX2_1_SEL, A1=>nx3439, B0=>nx3441, B1=>nx3324); ix3595 : inv02 port map ( Y=>nx3423, A=>reg_2_q_c_2); nx2581_EXMPLR : aoi32 port map ( Y=>nx2581, A0=>nx3423, A1=>nx3431, A2=> nx3375, B0=>nx984, B1=>nx3377); nx2588_EXMPLR : oai22 port map ( Y=>nx2588, A0=>nx3370, A1=>nx1705, B0=> nx3374, B1=>nx3433); nx3047_EXMPLR : oai22 port map ( Y=>nx3047, A0=>reg_2_q_c_2, A1=> C_MUX2_1_SEL, B0=>nx3375, B1=>nx3431); ix3596 : buf04 port map ( Y=>nx3425, A=>nx3383); ix3597 : buf04 port map ( Y=>nx3426, A=>nx3383); ix3598 : buf04 port map ( Y=>nx3427, A=>nx3385); ix3599 : buf04 port map ( Y=>nx3428, A=>nx3385); ix3600 : and02 port map ( Y=>nx3429, A0=>nx2601, A1=>reg_9_q_c_3); nx1028_EXMPLR : oai22 port map ( Y=>nx1028, A0=>nx2529, A1=>nx2565, B0=> PRI_OUT_0_2_EXMPLR, B1=>nx1642); nx2599_EXMPLR : oai22 port map ( Y=>nx2599, A0=>nx3429, A1=>nx1028, B0=> nx3429, B1=>nx1160); ix3601 : buf16 port map ( Y=>nx3430, A=>reg_5_q_c_2); ix3602 : buf16 port map ( Y=>nx3431, A=>reg_5_q_c_2); ix3603 : buf16 port map ( Y=>nx3432, A=>nx1665); ix3604 : buf16 port map ( Y=>nx3433, A=>nx1665); ix3605 : buf16 port map ( Y=>nx3435, A=>nx1771); ix3606 : buf16 port map ( Y=>nx3437, A=>nx1771); ix3607 : buf16 port map ( Y=>nx3438, A=>reg_2_q_c_6); ix3608 : buf16 port map ( Y=>nx3439, A=>reg_2_q_c_6); ix3609 : buf16 port map ( Y=>nx3440, A=>reg_5_q_c_6); ix3610 : buf16 port map ( Y=>nx3441, A=>reg_5_q_c_6); ix3611 : buf16 port map ( Y=>nx3442, A=>nx1874); ix3612 : buf16 port map ( Y=>nx3443, A=>nx1874); ix3613 : buf16 port map ( Y=>nx3444, A=>nx2089); ix3614 : buf16 port map ( Y=>nx3445, A=>nx2089); ix3615 : buf16 port map ( Y=>nx3446, A=>reg_5_q_c_12); ix3616 : buf16 port map ( Y=>nx3447, A=>reg_5_q_c_12); ix3617 : buf16 port map ( Y=>nx3448, A=>nx2197); ix3618 : buf16 port map ( Y=>nx3449, A=>nx2197); ix3619 : buf16 port map ( Y=>nx3451, A=>nx3045); ix3620 : buf16 port map ( Y=>nx3452, A=>nx3045); ix3621 : inv02 port map ( Y=>nx3622, A=>nx3401); end CIRCUIT_arch ;