-- -- Definition of CIRCUIT -- -- 12/14/05 22:09:39 -- -- LeonardoSpectrum Level 3, 2004a.63 -- library IEEE; use IEEE.STD_LOGIC_1164.all; entity CIRCUIT is port ( PRI_IN_0 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_1 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_2 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_3 : IN std_logic_vector (15 DOWNTO 0) ; PRI_IN_4 : IN std_logic_vector (15 DOWNTO 0) ; PRI_OUT_0 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_1 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_2 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_3 : OUT std_logic_vector (15 DOWNTO 0) ; PRI_OUT_4 : OUT std_logic_vector (15 DOWNTO 0) ; C_MUX2_1_SEL : IN std_logic ; C_MUX2_2_SEL : IN std_logic ; C_MUX2_3_SEL : IN std_logic ; C_MUX2_4_SEL : IN std_logic ; C_MUX2_5_SEL : IN std_logic ; CLK : IN std_logic) ; end CIRCUIT ; architecture CIRCUIT_arch of CIRCUIT is signal PRI_OUT_0_15_EXMPLR, PRI_OUT_0_dup0_14, PRI_OUT_0_dup0_13, PRI_OUT_0_12_EXMPLR, PRI_OUT_0_11_EXMPLR, PRI_OUT_0_dup0_10, PRI_OUT_0_dup0_9, PRI_OUT_0_dup0_8, PRI_OUT_0_dup0_7, PRI_OUT_0_dup0_6, PRI_OUT_0_5_EXMPLR, PRI_OUT_0_dup0_4, PRI_OUT_0_3_EXMPLR, PRI_OUT_0_dup0_2, PRI_OUT_0_dup0_1, PRI_OUT_0_dup0_0, PRI_OUT_1_15_EXMPLR, PRI_OUT_1_14_EXMPLR, PRI_OUT_1_13_EXMPLR, PRI_OUT_1_12_EXMPLR, PRI_OUT_1_11_EXMPLR, PRI_OUT_1_10_EXMPLR, PRI_OUT_1_9_EXMPLR, PRI_OUT_1_8_EXMPLR, PRI_OUT_1_7_EXMPLR, PRI_OUT_1_6_EXMPLR, PRI_OUT_1_5_EXMPLR, PRI_OUT_1_4_EXMPLR, PRI_OUT_1_3_EXMPLR, PRI_OUT_1_2_EXMPLR, PRI_OUT_1_1_EXMPLR, PRI_OUT_1_0_EXMPLR, PRI_OUT_2_15_EXMPLR, PRI_OUT_2_14_EXMPLR, PRI_OUT_2_13_EXMPLR, PRI_OUT_2_12_EXMPLR, PRI_OUT_2_11_EXMPLR, PRI_OUT_2_10_EXMPLR, PRI_OUT_2_9_EXMPLR, PRI_OUT_2_8_EXMPLR, PRI_OUT_2_7_EXMPLR, PRI_OUT_2_6_EXMPLR, PRI_OUT_2_5_EXMPLR, PRI_OUT_2_4_EXMPLR, PRI_OUT_2_3_EXMPLR, PRI_OUT_2_2_EXMPLR, PRI_OUT_2_1_EXMPLR, PRI_OUT_2_0_EXMPLR, PRI_OUT_3_15_EXMPLR, PRI_OUT_3_14_EXMPLR, PRI_OUT_3_13_EXMPLR, PRI_OUT_3_12_EXMPLR, PRI_OUT_3_11_EXMPLR, PRI_OUT_3_10_EXMPLR, PRI_OUT_3_9_EXMPLR, PRI_OUT_3_8_EXMPLR, PRI_OUT_3_dup0_7, PRI_OUT_3_6_EXMPLR, PRI_OUT_3_5_EXMPLR, PRI_OUT_3_4_EXMPLR, PRI_OUT_3_2_EXMPLR, PRI_OUT_3_1_EXMPLR, PRI_OUT_4_15_EXMPLR, PRI_OUT_4_14_EXMPLR, PRI_OUT_4_13_EXMPLR, PRI_OUT_4_12_EXMPLR, PRI_OUT_4_11_EXMPLR, PRI_OUT_4_10_EXMPLR, PRI_OUT_4_9_EXMPLR, PRI_OUT_4_8_EXMPLR, PRI_OUT_4_7_EXMPLR, PRI_OUT_4_6_EXMPLR, PRI_OUT_4_5_EXMPLR, PRI_OUT_4_4_EXMPLR, PRI_OUT_4_3_EXMPLR, PRI_OUT_4_2_EXMPLR, PRI_OUT_4_1_EXMPLR, PRI_OUT_4_0_EXMPLR, reg_5_q_c_0, reg_2_q_c_0, reg_10_q_c_0, nx26, nx44, nx80, nx94, nx108, nx130, reg_9_q_c_0, reg_1_q_c_0, nx152, nx174, nx184, nx192, reg_5_q_c_1, reg_2_q_c_1, reg_10_q_c_1, nx214, nx222, nx234, nx236, nx248, nx250, nx258, nx260, nx268, nx270, nx278, nx280, nx294, reg_9_q_c_1, nx304, reg_1_q_c_1, nx306, nx308, nx318, nx320, nx322, nx330, nx332, reg_5_q_c_2, reg_2_q_c_2, nx396, nx408, nx412, nx422, nx424, nx442, nx444, nx446, nx458, nx460, nx470, nx480, nx490, nx504, reg_9_q_c_2, nx520, nx524, reg_1_q_c_2, nx534, nx536, nx538, nx548, nx550, nx552, nx560, nx562, nx578, reg_5_q_c_3, nx588, reg_2_q_c_3, nx600, reg_10_q_c_3, nx616, nx626, nx638, nx652, nx654, nx674, nx676, nx698, nx700, nx710, nx718, nx720, nx734, reg_9_q_c_3, nx754, reg_1_q_c_3, nx766, nx768, nx778, nx780, nx782, nx790, nx792, reg_5_q_c_4, reg_2_q_c_4, nx868, nx872, nx880, nx882, nx884, nx902, nx904, nx906, nx920, nx930, nx940, nx950, nx964, reg_9_q_c_4, nx980, nx984, reg_1_q_c_4, nx994, nx996, nx998, nx1008, nx1010, nx1012, nx1020, nx1022, nx1038, reg_5_q_c_5, nx1048, reg_2_q_c_5, nx1060, reg_10_q_c_5, nx1068, nx1076, nx1098, nx1112, nx1114, nx1134, nx1136, nx1150, nx1158, nx1160, nx1168, nx1170, nx1178, nx1180, nx1194, reg_9_q_c_5, nx1214, reg_1_q_c_5, nx1226, nx1228, nx1238, nx1240, nx1242, nx1250, nx1252, reg_5_q_c_6, reg_2_q_c_6, nx1328, nx1332, nx1340, nx1342, nx1344, nx1362, nx1364, nx1366, nx1380, nx1390, nx1400, nx1410, nx1424, reg_9_q_c_6, nx1440, nx1444, reg_1_q_c_6, nx1454, nx1456, nx1458, nx1468, nx1470, nx1472, nx1480, nx1482, nx1498, reg_5_q_c_7, nx1508, reg_2_q_c_7, nx1520, reg_10_q_c_7, nx1536, nx1558, nx1572, nx1574, nx1596, nx1610, nx1618, nx1620, nx1630, nx1638, nx1640, nx1654, reg_9_q_c_7, nx1674, reg_1_q_c_7, nx1686, nx1688, nx1698, nx1700, nx1702, nx1710, nx1712, reg_5_q_c_8, reg_2_q_c_8, nx1788, nx1800, nx1802, nx1804, nx1826, nx1840, nx1850, nx1860, nx1870, nx1884, reg_9_q_c_8, nx1900, nx1904, reg_1_q_c_8, nx1914, nx1916, nx1918, nx1928, nx1930, nx1932, nx1940, nx1942, nx1958, reg_5_q_c_9, nx1968, reg_2_q_c_9, nx1980, reg_10_q_c_9, nx1996, nx2018, nx2032, nx2034, nx2056, nx2070, nx2078, nx2080, nx2090, nx2098, nx2100, nx2114, reg_9_q_c_9, nx2134, reg_1_q_c_9, nx2146, nx2148, nx2158, nx2160, nx2162, nx2170, nx2172, reg_5_q_c_10, reg_2_q_c_10, nx2248, nx2260, nx2262, nx2264, nx2286, nx2300, nx2310, nx2320, nx2330, nx2344, reg_9_q_c_10, nx2360, nx2364, reg_1_q_c_10, nx2374, nx2376, nx2378, nx2388, nx2390, nx2392, nx2400, nx2402, nx2418, reg_5_q_c_11, nx2428, reg_2_q_c_11, nx2440, reg_10_q_c_11, nx2456, nx2478, nx2492, nx2494, nx2516, nx2530, nx2538, nx2540, nx2548, nx2550, nx2558, nx2560, nx2574, reg_9_q_c_11, nx2594, reg_1_q_c_11, nx2606, nx2608, nx2618, nx2620, nx2622, nx2630, nx2632, reg_5_q_c_12, reg_2_q_c_12, nx2708, nx2720, nx2722, nx2724, nx2746, nx2760, nx2770, nx2780, nx2790, nx2804, reg_9_q_c_12, nx2820, nx2824, reg_1_q_c_12, nx2834, nx2836, nx2838, nx2848, nx2850, nx2852, nx2860, nx2862, nx2878, reg_5_q_c_13, nx2888, reg_2_q_c_13, nx2900, reg_10_q_c_13, nx2906, nx2916, nx2938, nx2952, nx2954, nx2976, nx2990, nx2998, nx3000, nx3010, nx3018, nx3020, nx3034, reg_9_q_c_13, nx3054, reg_1_q_c_13, nx3066, nx3068, nx3078, nx3080, nx3082, nx3090, nx3092, reg_5_q_c_14, reg_2_q_c_14, nx3168, nx3180, nx3182, nx3184, nx3206, nx3218, nx3220, nx3230, nx3240, nx3250, nx3264, reg_9_q_c_14, nx3284, reg_1_q_c_14, nx3294, nx3296, nx3298, nx3308, nx3310, nx3320, nx3322, nx3338, reg_5_q_c_15, nx3348, reg_2_q_c_15, nx3360, reg_10_q_c_15, nx3376, nx3398, nx3400, nx3402, nx3412, nx3414, nx3434, nx3436, nx3450, nx3460, nx3480, nx3494, reg_9_q_c_15, reg_1_q_c_15, nx3526, nx3528, nx3542, nx3552, nx1453, nx1505, nx1507, nx1513, nx1533, nx1535, nx1541, nx1543, nx1549, nx1551, nx1559, nx1565, nx1573, nx1587, nx1598, nx1621, nx1631, nx1633, nx1637, nx1641, nx1655, nx1658, nx1662, nx1675, nx1683, nx1692, nx1705, nx1739, nx1741, nx1749, nx1759, nx1767, nx1773, nx1781, nx1793, nx1797, nx1803, nx1813, nx1817, nx1819, nx1829, nx1831, nx1843, nx1849, nx1851, nx1853, nx1855, nx1859, nx1863, nx1875, nx1879, nx1891, nx1907, nx1921, nx1949, nx1951, nx1959, nx1969, nx1975, nx1991, nx2005, nx2009, nx2015, nx2029, nx2033, nx2035, nx2041, nx2043, nx2055, nx2061, nx2063, nx2065, nx2067, nx2073, nx2076, nx2081, nx2089, nx2093, nx2105, nx2119, nx2133, nx2167, nx2169, nx2176, nx2183, nx2191, nx2219, nx2223, nx2229, nx2242, nx2245, nx2247, nx2257, nx2259, nx2269, nx2275, nx2277, nx2279, nx2281, nx2287, nx2290, nx2304, nx2307, nx2319, nx2334, nx2347, nx2381, nx2383, nx2389, nx2397, nx2403, nx2429, nx2433, nx2453, nx2457, nx2459, nx2469, nx2471, nx2483, nx2491, nx2493, nx2495, nx2497, nx2501, nx2505, nx2520, nx2523, nx2536, nx2549, nx2561, nx2589, nx2591, nx2597, nx2607, nx2613, nx2637, nx2640, nx2661, nx2665, nx2667, nx2677, nx2679, nx2691, nx2699, nx2701, nx2703, nx2705, nx2711, nx2715, nx2721, nx2725, nx2729, nx2732, nx2747, nx2763, nx2774, nx2799, nx2801, nx2808, nx2815, nx2823, nx2851, nx2855, nx2871, nx2875, nx2877, nx2887, nx2889, nx2901, nx2909, nx2911, nx2913, nx2915, nx2921, nx2925, nx2941, nx2945, nx2959, nx2965, nx2975, nx2987, nx3009, nx3015, nx3017, nx3024, nx3038, nx3047, nx3053, nx3055, nx3061, nx3131, nx3133, nx3143, nx3145, PRI_OUT_3_dup0_3, nx690, PRI_OUT_3_dup0_0, nx66, PRI_OUT_3_3_EXMPLR, PRI_OUT_3_0_EXMPLR, nx3335, nx3336, nx3337, nx3339, nx3340, nx3341, nx3342, nx2737, nx3343, nx3344, nx3345, nx3346, nx3347, nx3349, nx3350, nx3351, nx3352, nx2988, nx2829, nx3353, nx3354, nx3355, nx2758, nx3356, nx3357, nx3358, nx2528, nx3359, nx3361, nx3362, nx3363, nx3364, nx58, nx3365, nx3366, nx3367, nx3368, nx1555, nx1479, nx18, nx1473, nx3369, nx3370, nx3371, nx2931, nx3372, nx3373, nx3374, nx3375, nx3377, nx3378, nx3379, nx3380, nx3381, nx3382, nx3031, nx3383, nx3384, nx3470, nx2935, nx2908, nx3385, nx3387, nx3388, nx3389, nx3390, nx3391, nx3392, nx2407, nx3393, nx3394, nx3395, nx3396, nx3397, nx3399, nx2466, nx2617, nx3401, nx3403, nx3404, nx2298, nx2529, nx3405, nx3406, nx3407, nx2068, nx3408, nx3409, nx3410, nx1838, nx3411, nx3413, nx1645, nx3415, nx3416, nx3417, nx3418, nx3419, nx3420, nx3421, nx3422, nx3423, nx3424, nx608, nx3425, nx1867, nx1871, nx1649, nx3426, nx3427, nx3428, nx3429, nx3430, nx3431, nx3432, nx1885, nx3433, nx3435, nx3437, nx3438, nx3439, nx3440, nx2097, nx3441, nx3442, nx3443, nx1148, nx1981, nx3444, nx3445, nx3446, nx918, nx3447, nx3448, nx3449, nx688, nx3451, nx3452, nx3453, nx3454, nx3455, nx3456, nx3457, nx1601, nx3458, nx3459, nx162, nx3461, nx3462, nx3463, nx3464, nx3465, nx3466, nx3467, nx3468, nx3469, nx3471, nx3472, nx2313, nx1608, nx2197, nx3473, nx3474, nx3475, nx1378, nx3476, nx3477, nx3478, nx3479, nx3481, nx2448, nx3482, nx2511, nx3483, nx3484, nx2515, nx2299, nx3485, nx3486, nx3487, nx3488, nx1066, nx3489, nx3490, nx3491, nx3492, nx3493, nx3495, nx3496, nx3497, nx3498, nx3499, nx3500, nx3501, nx3502, nx3503, nx3504, nx3505, nx3506, nx3507, nx3508, nx3509, nx3511, nx3512, nx3513, nx3514, nx3204, nx2839, nx3515, nx3516, nx2861, nx2974, nx3517, nx2744, nx2626, nx3518, nx3519, nx2647, nx2514, nx2284, nx3520, nx3521, nx3522, nx3523, nx3524, nx3525, nx3527, nx3529, nx1822, nx3530, nx3531, nx3532, nx3533, nx3534, nx3535, nx3536, nx3537, nx3538, nx3539, nx3540, nx3541, nx2282, nx3543, nx3544, nx3545, nx3546, nx3547, nx3202, nx2742, nx3548, nx3549, nx3550, nx2415, nx3551, nx3553, nx3554, nx2439, nx2054, nx3555, nx1824, nx2205, nx3556, nx3557, nx3558, nx3559, nx1594, nx3560, nx3561, nx3562, nx3563, nx3564, nx3565, nx3566, nx3510, nx3567, nx3568, nx3569, nx3570, nx1528, nx3571, nx3572, nx3573, nx3574, nx3575, nx3576, nx3577, nx3312, nx3578, nx3579, nx3386, nx3580, nx3581, nx3582, nx3583, nx14, nx3584, nx3585, nx3586, nx420, nx3587, nx1581, nx1578, nx3588, nx3589, nx3590, nx3591, nx3592, nx220, nx1485, nx3593, nx3594, nx3595, nx3596, nx3597, nx3069, nx2951, nx3598, nx3599, nx3600, nx3601, nx3602, nx3603, nx3604, nx3605, nx1735, nx3606, nx3607, nx3608, nx3609, nx358, nx3610, nx3611, nx1525, nx3612, nx3613, nx122, nx1457, nx3614, nx3615, nx3616, nx3617, nx3618, nx1776, nx1316, nx3619, nx3620, nx3621, nx3622, nx3623, nx3624, nx3625, nx3626, nx3627, nx3628, nx3629, nx3630, nx3631, nx3632, nx3633, nx3634, nx3635, nx3636, nx3637, nx3638, nx3639, nx3640, nx3641, nx3642, nx3643, nx3644, nx3645, nx1988, nx3646, nx3647, nx3648, nx3649, nx2295, nx1526, nx2084, nx3650, nx3651, nx3652, nx3653, nx3654, nx3655, nx3656, nx3657, nx3658, nx3659, nx3660, PRI_OUT_0_0_EXMPLR, nx3661, nx3662, nx3663, PRI_OUT_0_1_EXMPLR, nx3664, PRI_OUT_0_2_EXMPLR, nx3665, PRI_OUT_0_4_EXMPLR, nx3666, PRI_OUT_0_6_EXMPLR, nx3667, PRI_OUT_0_7_EXMPLR, nx3668, PRI_OUT_3_7_EXMPLR, nx3669, PRI_OUT_0_8_EXMPLR, nx3670, nx3671, nx3672, PRI_OUT_0_9_EXMPLR, nx3673, PRI_OUT_0_10_EXMPLR, nx3674, nx3675, nx3676, nx3677, nx3678, PRI_OUT_0_13_EXMPLR, nx3679, PRI_OUT_0_14_EXMPLR, nx3680: std_logic ; begin PRI_OUT_0(15) <= PRI_OUT_0_15_EXMPLR ; PRI_OUT_0(14) <= PRI_OUT_0_14_EXMPLR ; PRI_OUT_0(13) <= PRI_OUT_0_13_EXMPLR ; PRI_OUT_0(12) <= PRI_OUT_0_12_EXMPLR ; PRI_OUT_0(11) <= PRI_OUT_0_11_EXMPLR ; PRI_OUT_0(10) <= PRI_OUT_0_10_EXMPLR ; PRI_OUT_0(9) <= PRI_OUT_0_9_EXMPLR ; PRI_OUT_0(8) <= PRI_OUT_0_8_EXMPLR ; PRI_OUT_0(7) <= PRI_OUT_0_7_EXMPLR ; PRI_OUT_0(6) <= PRI_OUT_0_6_EXMPLR ; PRI_OUT_0(5) <= PRI_OUT_0_5_EXMPLR ; PRI_OUT_0(4) <= PRI_OUT_0_4_EXMPLR ; PRI_OUT_0(3) <= PRI_OUT_0_3_EXMPLR ; PRI_OUT_0(2) <= PRI_OUT_0_2_EXMPLR ; PRI_OUT_0(1) <= PRI_OUT_0_1_EXMPLR ; PRI_OUT_0(0) <= PRI_OUT_0_0_EXMPLR ; PRI_OUT_1(15) <= PRI_OUT_1_15_EXMPLR ; PRI_OUT_1(14) <= PRI_OUT_1_14_EXMPLR ; PRI_OUT_1(13) <= PRI_OUT_1_13_EXMPLR ; PRI_OUT_1(12) <= PRI_OUT_1_12_EXMPLR ; PRI_OUT_1(11) <= PRI_OUT_1_11_EXMPLR ; PRI_OUT_1(10) <= PRI_OUT_1_10_EXMPLR ; PRI_OUT_1(9) <= PRI_OUT_1_9_EXMPLR ; PRI_OUT_1(8) <= PRI_OUT_1_8_EXMPLR ; PRI_OUT_1(7) <= PRI_OUT_1_7_EXMPLR ; PRI_OUT_1(6) <= PRI_OUT_1_6_EXMPLR ; PRI_OUT_1(5) <= PRI_OUT_1_5_EXMPLR ; PRI_OUT_1(4) <= PRI_OUT_1_4_EXMPLR ; PRI_OUT_1(3) <= PRI_OUT_1_3_EXMPLR ; PRI_OUT_1(2) <= PRI_OUT_1_2_EXMPLR ; PRI_OUT_1(1) <= PRI_OUT_1_1_EXMPLR ; PRI_OUT_1(0) <= PRI_OUT_1_0_EXMPLR ; PRI_OUT_2(15) <= PRI_OUT_2_15_EXMPLR ; PRI_OUT_2(14) <= PRI_OUT_2_14_EXMPLR ; PRI_OUT_2(13) <= PRI_OUT_2_13_EXMPLR ; PRI_OUT_2(12) <= PRI_OUT_2_12_EXMPLR ; PRI_OUT_2(11) <= PRI_OUT_2_11_EXMPLR ; PRI_OUT_2(10) <= PRI_OUT_2_10_EXMPLR ; PRI_OUT_2(9) <= PRI_OUT_2_9_EXMPLR ; PRI_OUT_2(8) <= PRI_OUT_2_8_EXMPLR ; PRI_OUT_2(7) <= PRI_OUT_2_7_EXMPLR ; PRI_OUT_2(6) <= PRI_OUT_2_6_EXMPLR ; PRI_OUT_2(5) <= PRI_OUT_2_5_EXMPLR ; PRI_OUT_2(4) <= PRI_OUT_2_4_EXMPLR ; PRI_OUT_2(3) <= PRI_OUT_2_3_EXMPLR ; PRI_OUT_2(2) <= PRI_OUT_2_2_EXMPLR ; PRI_OUT_2(1) <= PRI_OUT_2_1_EXMPLR ; PRI_OUT_2(0) <= PRI_OUT_2_0_EXMPLR ; PRI_OUT_3(15) <= PRI_OUT_3_15_EXMPLR ; PRI_OUT_3(14) <= PRI_OUT_3_14_EXMPLR ; PRI_OUT_3(13) <= PRI_OUT_3_13_EXMPLR ; PRI_OUT_3(12) <= PRI_OUT_3_12_EXMPLR ; PRI_OUT_3(11) <= PRI_OUT_3_11_EXMPLR ; PRI_OUT_3(10) <= PRI_OUT_3_10_EXMPLR ; PRI_OUT_3(9) <= PRI_OUT_3_9_EXMPLR ; PRI_OUT_3(8) <= PRI_OUT_3_8_EXMPLR ; PRI_OUT_3(7) <= PRI_OUT_3_7_EXMPLR ; PRI_OUT_3(6) <= PRI_OUT_3_6_EXMPLR ; PRI_OUT_3(5) <= PRI_OUT_3_5_EXMPLR ; PRI_OUT_3(4) <= PRI_OUT_3_4_EXMPLR ; PRI_OUT_3(3) <= PRI_OUT_3_3_EXMPLR ; PRI_OUT_3(2) <= PRI_OUT_3_2_EXMPLR ; PRI_OUT_3(1) <= PRI_OUT_3_1_EXMPLR ; PRI_OUT_3(0) <= PRI_OUT_3_0_EXMPLR ; PRI_OUT_4(15) <= PRI_OUT_4_15_EXMPLR ; PRI_OUT_4(14) <= PRI_OUT_4_14_EXMPLR ; PRI_OUT_4(13) <= PRI_OUT_4_13_EXMPLR ; PRI_OUT_4(12) <= PRI_OUT_4_12_EXMPLR ; PRI_OUT_4(11) <= PRI_OUT_4_11_EXMPLR ; PRI_OUT_4(10) <= PRI_OUT_4_10_EXMPLR ; PRI_OUT_4(9) <= PRI_OUT_4_9_EXMPLR ; PRI_OUT_4(8) <= PRI_OUT_4_8_EXMPLR ; PRI_OUT_4(7) <= PRI_OUT_4_7_EXMPLR ; PRI_OUT_4(6) <= PRI_OUT_4_6_EXMPLR ; PRI_OUT_4(5) <= PRI_OUT_4_5_EXMPLR ; PRI_OUT_4(4) <= PRI_OUT_4_4_EXMPLR ; PRI_OUT_4(3) <= PRI_OUT_4_3_EXMPLR ; PRI_OUT_4(2) <= PRI_OUT_4_2_EXMPLR ; PRI_OUT_4(1) <= PRI_OUT_4_1_EXMPLR ; PRI_OUT_4(0) <= PRI_OUT_4_0_EXMPLR ; REG_8_reg_q_0 : dff port map ( Q=>PRI_OUT_4_0_EXMPLR, QB=>OPEN, D=>nx192, CLK=>CLK); ix193 : ao21 port map ( Y=>nx192, A0=>nx1453, A1=>reg_9_q_c_0, B0=>nx1513 ); ix131 : oai21 port map ( Y=>nx130, A0=>PRI_IN_4(0), A1=>nx1457, B0=>nx122 ); REG_5_reg_q_0 : dff port map ( Q=>reg_5_q_c_0, QB=>nx1453, D=>nx130, CLK =>CLK); REG_10_reg_q_0 : dff port map ( Q=>reg_10_q_c_0, QB=>OPEN, D=>nx94, CLK=> CLK); ix95 : xor2 port map ( Y=>nx94, A0=>PRI_IN_1(0), A1=>PRI_OUT_0_0_EXMPLR); REG_3_reg_q_0 : dff port map ( Q=>PRI_OUT_0_dup0_0, QB=>OPEN, D=>nx80, CLK=>CLK); REG_2_reg_q_0 : dff port map ( Q=>reg_2_q_c_0, QB=>OPEN, D=>nx108, CLK=> CLK); REG_6_reg_q_0 : dff port map ( Q=>PRI_OUT_2_0_EXMPLR, QB=>OPEN, D=>nx26, CLK=>CLK); ix27 : xnor2 port map ( Y=>nx26, A0=>PRI_OUT_4_0_EXMPLR, A1=>nx1485); REG_7_reg_q_0 : dff port map ( Q=>PRI_OUT_1_0_EXMPLR, QB=>OPEN, D=>nx44, CLK=>CLK); ix45 : xnor2 port map ( Y=>nx44, A0=>PRI_OUT_0_0_EXMPLR, A1=>nx1473); REG_9_reg_q_0 : dff port map ( Q=>reg_9_q_c_0, QB=>OPEN, D=>nx174, CLK=> CLK); ix175 : xor2 port map ( Y=>nx174, A0=>PRI_IN_3(0), A1=>nx162); REG_1_reg_q_0 : dff port map ( Q=>reg_1_q_c_0, QB=>OPEN, D=>nx152, CLK=> CLK); ix153 : ao21 port map ( Y=>nx152, A0=>nx1505, A1=>PRI_OUT_2_0_EXMPLR, B0 =>nx1507); ix1506 : inv02 port map ( Y=>nx1505, A=>PRI_IN_0(0)); ix1508 : nor02 port map ( Y=>nx1507, A0=>PRI_OUT_2_0_EXMPLR, A1=>nx1505); ix1514 : nor02 port map ( Y=>nx1513, A0=>reg_9_q_c_0, A1=>nx1453); REG_8_reg_q_1 : dff port map ( Q=>PRI_OUT_4_1_EXMPLR, QB=>OPEN, D=>nx332, CLK=>CLK); ix333 : xnor2 port map ( Y=>nx332, A0=>nx1513, A1=>nx330); REG_5_reg_q_1 : dff port map ( Q=>reg_5_q_c_1, QB=>nx1598, D=>nx294, CLK =>CLK); ix295 : xnor2 port map ( Y=>nx294, A0=>nx122, A1=>nx1525); ix281 : xor2 port map ( Y=>nx280, A0=>nx1533, A1=>nx1535); ix1534 : nand02 port map ( Y=>nx1533, A0=>PRI_IN_2(0), A1=>reg_10_q_c_0); ix1536 : xnor2 port map ( Y=>nx1535, A0=>PRI_IN_2(1), A1=>reg_10_q_c_1); REG_10_reg_q_1 : dff port map ( Q=>reg_10_q_c_1, QB=>OPEN, D=>nx270, CLK =>CLK); ix271 : xor2 port map ( Y=>nx270, A0=>nx1541, A1=>nx1543); ix1542 : nand02 port map ( Y=>nx1541, A0=>PRI_IN_1(0), A1=> PRI_OUT_0_0_EXMPLR); ix1544 : xnor2 port map ( Y=>nx1543, A0=>PRI_IN_1(1), A1=> PRI_OUT_0_1_EXMPLR); REG_3_reg_q_1 : dff port map ( Q=>PRI_OUT_0_dup0_1, QB=>OPEN, D=>nx260, CLK=>CLK); ix261 : xor2 port map ( Y=>nx260, A0=>nx1549, A1=>nx1551); ix1550 : nand02 port map ( Y=>nx1549, A0=>PRI_OUT_3_0_EXMPLR, A1=> reg_10_q_c_0); ix1552 : xnor2 port map ( Y=>nx1551, A0=>PRI_OUT_3_1_EXMPLR, A1=> reg_10_q_c_1); REG_4_reg_q_1 : dff port map ( Q=>PRI_OUT_3_1_EXMPLR, QB=>OPEN, D=>nx250, CLK=>CLK); ix251 : xnor2 port map ( Y=>nx250, A0=>nx1555, A1=>nx248); ix1560 : inv02 port map ( Y=>nx1559, A=>C_MUX2_5_SEL); ix249 : xnor2 port map ( Y=>nx248, A0=>nx1565, A1=>nx1573); ix1566 : mux21 port map ( Y=>nx1565, A0=>PRI_OUT_3_1_EXMPLR, A1=>nx214, S0=>C_MUX2_5_SEL); REG_2_reg_q_1 : dff port map ( Q=>reg_2_q_c_1, QB=>OPEN, D=>nx280, CLK=> CLK); ix1574 : mux21 port map ( Y=>nx1573, A0=>PRI_OUT_2_1_EXMPLR, A1=> PRI_OUT_1_1_EXMPLR, S0=>C_MUX2_4_SEL); REG_6_reg_q_1 : dff port map ( Q=>PRI_OUT_2_1_EXMPLR, QB=>OPEN, D=>nx222, CLK=>CLK); ix223 : xnor2 port map ( Y=>nx222, A0=>nx1578, A1=>nx220); REG_7_reg_q_1 : dff port map ( Q=>PRI_OUT_1_1_EXMPLR, QB=>OPEN, D=>nx236, CLK=>CLK); ix237 : xnor2 port map ( Y=>nx236, A0=>nx1587, A1=>nx234); ix1588 : nand02 port map ( Y=>nx1587, A0=>PRI_OUT_0_0_EXMPLR, A1=>nx18); ix235 : xnor2 port map ( Y=>nx234, A0=>PRI_OUT_0_1_EXMPLR, A1=>nx1565); REG_9_reg_q_1 : dff port map ( Q=>reg_9_q_c_1, QB=>OPEN, D=>nx322, CLK=> CLK); ix323 : xnor2 port map ( Y=>nx322, A0=>nx1601, A1=>nx320); ix321 : xnor2 port map ( Y=>nx320, A0=>PRI_IN_3(1), A1=>nx318); ix319 : ao21 port map ( Y=>nx318, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_1, B0=> nx304); REG_1_reg_q_1 : dff port map ( Q=>reg_1_q_c_1, QB=>OPEN, D=>nx308, CLK=> CLK); ix309 : xnor2 port map ( Y=>nx308, A0=>nx1507, A1=>nx306); ix307 : xnor2 port map ( Y=>nx306, A0=>PRI_IN_0(1), A1=> PRI_OUT_2_1_EXMPLR); ix305 : nor02 port map ( Y=>nx304, A0=>C_MUX2_3_SEL, A1=>nx1581); REG_8_reg_q_2 : dff port map ( Q=>PRI_OUT_4_2_EXMPLR, QB=>OPEN, D=>nx562, CLK=>CLK); ix563 : xnor2 port map ( Y=>nx562, A0=>nx1621, A1=>nx560); ix1622 : aoi22 port map ( Y=>nx1621, A0=>nx1598, A1=>reg_9_q_c_1, B0=> nx184, B1=>nx330); ix561 : xnor2 port map ( Y=>nx560, A0=>reg_5_q_c_2, A1=>reg_9_q_c_2); REG_5_reg_q_2 : dff port map ( Q=>reg_5_q_c_2, QB=>OPEN, D=>nx504, CLK=> CLK); ix505 : xnor2 port map ( Y=>nx504, A0=>nx358, A1=>nx1631); ix1632 : xnor2 port map ( Y=>nx1631, A0=>PRI_IN_4(2), A1=>nx1633); ix1634 : mux21 port map ( Y=>nx1633, A0=>reg_5_q_c_2, A1=>reg_2_q_c_2, S0 =>C_MUX2_2_SEL); ix491 : xor2 port map ( Y=>nx490, A0=>nx1637, A1=>nx1641); ix1638 : aoi32 port map ( Y=>nx1637, A0=>PRI_IN_2(0), A1=>reg_10_q_c_0, A2=>nx278, B0=>reg_10_q_c_1, B1=>PRI_IN_2(1)); REG_10_reg_q_2 : dff port map ( Q=>OPEN, QB=>nx1705, D=>nx480, CLK=>CLK); ix481 : xor2 port map ( Y=>nx480, A0=>nx1645, A1=>nx1649); REG_3_reg_q_2 : dff port map ( Q=>PRI_OUT_0_dup0_2, QB=>OPEN, D=>nx470, CLK=>CLK); ix471 : xor2 port map ( Y=>nx470, A0=>nx1655, A1=>nx1658); ix1656 : aoi32 port map ( Y=>nx1655, A0=>PRI_OUT_3_0_EXMPLR, A1=> reg_10_q_c_0, A2=>nx258, B0=>reg_10_q_c_1, B1=>PRI_OUT_3_1_EXMPLR); REG_4_reg_q_2 : dff port map ( Q=>PRI_OUT_3_2_EXMPLR, QB=>OPEN, D=>nx460, CLK=>CLK); ix461 : xnor2 port map ( Y=>nx460, A0=>nx1662, A1=>nx458); ix1664 : mux21 port map ( Y=>nx1662, A0=>nx1573, A1=>nx58, S0=>nx248); ix459 : xnor2 port map ( Y=>nx458, A0=>nx1675, A1=>nx1683); ix1676 : mux21 port map ( Y=>nx1675, A0=>PRI_OUT_3_2_EXMPLR, A1=>nx408, S0=>C_MUX2_5_SEL); REG_2_reg_q_2 : dff port map ( Q=>reg_2_q_c_2, QB=>OPEN, D=>nx490, CLK=> CLK); ix1684 : mux21 port map ( Y=>nx1683, A0=>PRI_OUT_2_2_EXMPLR, A1=> PRI_OUT_1_2_EXMPLR, S0=>C_MUX2_4_SEL); REG_6_reg_q_2 : dff port map ( Q=>PRI_OUT_2_2_EXMPLR, QB=>OPEN, D=>nx424, CLK=>CLK); ix425 : xor2 port map ( Y=>nx424, A0=>nx420, A1=>nx422); ix423 : xnor2 port map ( Y=>nx422, A0=>PRI_OUT_4_2_EXMPLR, A1=>nx1692); ix1693 : mux21 port map ( Y=>nx1692, A0=>reg_2_q_c_2, A1=> PRI_OUT_0_2_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_2 : dff port map ( Q=>PRI_OUT_1_2_EXMPLR, QB=>OPEN, D=>nx446, CLK=>CLK); ix447 : xor2 port map ( Y=>nx446, A0=>nx442, A1=>nx444); ix443 : mux21 port map ( Y=>nx442, A0=>nx1565, A1=>nx1587, S0=>nx234); ix445 : xnor2 port map ( Y=>nx444, A0=>PRI_OUT_0_2_EXMPLR, A1=>nx1675); REG_9_reg_q_2 : dff port map ( Q=>reg_9_q_c_2, QB=>OPEN, D=>nx552, CLK=> CLK); ix553 : xor2 port map ( Y=>nx552, A0=>nx520, A1=>nx550); ix521 : mux21 port map ( Y=>nx520, A0=>PRI_IN_3(1), A1=>nx1601, S0=>nx320 ); ix551 : xnor2 port map ( Y=>nx550, A0=>PRI_IN_3(2), A1=>nx548); ix549 : ao21 port map ( Y=>nx548, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_2, B0=> nx524); REG_1_reg_q_2 : dff port map ( Q=>reg_1_q_c_2, QB=>OPEN, D=>nx538, CLK=> CLK); ix539 : xor2 port map ( Y=>nx538, A0=>nx534, A1=>nx536); ix535 : mux21 port map ( Y=>nx534, A0=>PRI_IN_0(1), A1=>nx1507, S0=>nx306 ); ix537 : xnor2 port map ( Y=>nx536, A0=>PRI_IN_0(2), A1=> PRI_OUT_2_2_EXMPLR); ix525 : nor02 port map ( Y=>nx524, A0=>C_MUX2_3_SEL, A1=>nx1692); REG_8_reg_q_3 : dff port map ( Q=>PRI_OUT_4_3_EXMPLR, QB=>OPEN, D=>nx792, CLK=>CLK); ix793 : xor2 port map ( Y=>nx792, A0=>nx578, A1=>nx790); ix579 : mux21 port map ( Y=>nx578, A0=>reg_5_q_c_2, A1=>nx1621, S0=>nx560 ); REG_5_reg_q_3 : dff port map ( Q=>reg_5_q_c_3, QB=>nx1813, D=>nx734, CLK =>CLK); ix735 : xnor2 port map ( Y=>nx734, A0=>nx588, A1=>nx1739); ix589 : mux21 port map ( Y=>nx588, A0=>nx1735, A1=>PRI_IN_4(2), S0=> nx1631); ix1740 : xnor2 port map ( Y=>nx1739, A0=>PRI_IN_4(3), A1=>nx1741); ix1742 : mux21 port map ( Y=>nx1741, A0=>reg_5_q_c_3, A1=>reg_2_q_c_3, S0 =>C_MUX2_2_SEL); ix721 : xnor2 port map ( Y=>nx720, A0=>nx600, A1=>nx1749); ix601 : mux21 port map ( Y=>nx600, A0=>nx1637, A1=>nx1705, S0=>nx1641); ix1750 : xnor2 port map ( Y=>nx1749, A0=>PRI_IN_2(3), A1=>reg_10_q_c_3); REG_10_reg_q_3 : dff port map ( Q=>reg_10_q_c_3, QB=>OPEN, D=>nx710, CLK =>CLK); ix711 : xnor2 port map ( Y=>nx710, A0=>nx608, A1=>nx1759); ix1760 : xnor2 port map ( Y=>nx1759, A0=>PRI_IN_1(3), A1=> PRI_OUT_0_3_EXMPLR); REG_3_reg_q_3 : dff port map ( Q=>PRI_OUT_0_3_EXMPLR, QB=>OPEN, D=>nx700, CLK=>CLK); ix701 : xnor2 port map ( Y=>nx700, A0=>nx616, A1=>nx1767); ix617 : mux21 port map ( Y=>nx616, A0=>nx1655, A1=>nx1705, S0=>nx1658); ix1768 : xnor2 port map ( Y=>nx1767, A0=>PRI_OUT_3_3_EXMPLR, A1=> reg_10_q_c_3); ix1774 : mux21 port map ( Y=>nx1773, A0=>nx1683, A1=>nx396, S0=>nx458); ix1782 : mux21 port map ( Y=>nx1781, A0=>PRI_OUT_3_dup0_3, A1=>nx638, S0 =>C_MUX2_5_SEL); REG_2_reg_q_3 : dff port map ( Q=>reg_2_q_c_3, QB=>OPEN, D=>nx720, CLK=> CLK); REG_6_reg_q_3 : dff port map ( Q=>PRI_OUT_2_3_EXMPLR, QB=>OPEN, D=>nx654, CLK=>CLK); ix655 : xnor2 port map ( Y=>nx654, A0=>nx1793, A1=>nx652); ix1794 : aoi22 port map ( Y=>nx1793, A0=>nx408, A1=>PRI_OUT_4_2_EXMPLR, B0=>nx3587, B1=>nx422); ix653 : xnor2 port map ( Y=>nx652, A0=>PRI_OUT_4_3_EXMPLR, A1=>nx1797); ix1798 : mux21 port map ( Y=>nx1797, A0=>reg_2_q_c_3, A1=> PRI_OUT_0_3_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_3 : dff port map ( Q=>PRI_OUT_1_3_EXMPLR, QB=>OPEN, D=>nx676, CLK=>CLK); ix677 : xnor2 port map ( Y=>nx676, A0=>nx1803, A1=>nx674); ix1804 : aoi22 port map ( Y=>nx1803, A0=>nx412, A1=>PRI_OUT_0_2_EXMPLR, B0=>nx442, B1=>nx444); ix675 : xnor2 port map ( Y=>nx674, A0=>PRI_OUT_0_3_EXMPLR, A1=>nx1781); REG_9_reg_q_3 : dff port map ( Q=>reg_9_q_c_3, QB=>OPEN, D=>nx782, CLK=> CLK); ix783 : xnor2 port map ( Y=>nx782, A0=>nx1817, A1=>nx780); ix1818 : mux21 port map ( Y=>nx1817, A0=>nx1819, A1=>nx520, S0=>nx550); ix1820 : inv02 port map ( Y=>nx1819, A=>PRI_IN_3(2)); ix781 : xnor2 port map ( Y=>nx780, A0=>PRI_IN_3(3), A1=>nx778); ix779 : ao21 port map ( Y=>nx778, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_3, B0=> nx754); REG_1_reg_q_3 : dff port map ( Q=>reg_1_q_c_3, QB=>OPEN, D=>nx768, CLK=> CLK); ix769 : xnor2 port map ( Y=>nx768, A0=>nx1829, A1=>nx766); ix1830 : aoi22 port map ( Y=>nx1829, A0=>nx1831, A1=>PRI_OUT_2_2_EXMPLR, B0=>nx534, B1=>nx536); ix1832 : inv02 port map ( Y=>nx1831, A=>PRI_IN_0(2)); ix767 : xnor2 port map ( Y=>nx766, A0=>PRI_IN_0(3), A1=> PRI_OUT_2_3_EXMPLR); ix755 : nor02 port map ( Y=>nx754, A0=>C_MUX2_3_SEL, A1=>nx1797); REG_8_reg_q_4 : dff port map ( Q=>PRI_OUT_4_4_EXMPLR, QB=>OPEN, D=>nx1022, CLK=>CLK); ix1023 : xnor2 port map ( Y=>nx1022, A0=>nx1843, A1=>nx1020); ix1844 : aoi22 port map ( Y=>nx1843, A0=>nx1813, A1=>reg_9_q_c_3, B0=> nx578, B1=>nx790); ix1021 : xnor2 port map ( Y=>nx1020, A0=>reg_5_q_c_4, A1=>reg_9_q_c_4); REG_5_reg_q_4 : dff port map ( Q=>reg_5_q_c_4, QB=>OPEN, D=>nx964, CLK=> CLK); ix965 : xor2 port map ( Y=>nx964, A0=>nx1849, A1=>nx1853); ix1850 : mux21 port map ( Y=>nx1849, A0=>nx588, A1=>nx1851, S0=>nx1739); ix1852 : inv02 port map ( Y=>nx1851, A=>PRI_IN_4(3)); ix1854 : xnor2 port map ( Y=>nx1853, A0=>PRI_IN_4(4), A1=>nx1855); ix1856 : mux21 port map ( Y=>nx1855, A0=>reg_5_q_c_4, A1=>reg_2_q_c_4, S0 =>C_MUX2_2_SEL); ix951 : xor2 port map ( Y=>nx950, A0=>nx1859, A1=>nx1863); ix1860 : aoi22 port map ( Y=>nx1859, A0=>reg_10_q_c_3, A1=>PRI_IN_2(3), B0=>nx600, B1=>nx718); REG_10_reg_q_4 : dff port map ( Q=>OPEN, QB=>nx1921, D=>nx940, CLK=>CLK); ix941 : xor2 port map ( Y=>nx940, A0=>nx1867, A1=>nx1871); REG_3_reg_q_4 : dff port map ( Q=>PRI_OUT_0_dup0_4, QB=>OPEN, D=>nx930, CLK=>CLK); ix931 : xor2 port map ( Y=>nx930, A0=>nx1875, A1=>nx1879); ix1876 : aoi22 port map ( Y=>nx1875, A0=>reg_10_q_c_3, A1=> PRI_OUT_3_3_EXMPLR, B0=>nx616, B1=>nx698); REG_4_reg_q_4 : dff port map ( Q=>PRI_OUT_3_4_EXMPLR, QB=>OPEN, D=>nx920, CLK=>CLK); ix921 : xnor2 port map ( Y=>nx920, A0=>nx1885, A1=>nx918); ix1892 : mux21 port map ( Y=>nx1891, A0=>PRI_OUT_3_4_EXMPLR, A1=>nx868, S0=>C_MUX2_5_SEL); REG_2_reg_q_4 : dff port map ( Q=>reg_2_q_c_4, QB=>OPEN, D=>nx950, CLK=> CLK); REG_6_reg_q_4 : dff port map ( Q=>PRI_OUT_2_4_EXMPLR, QB=>OPEN, D=>nx884, CLK=>CLK); ix885 : xor2 port map ( Y=>nx884, A0=>nx880, A1=>nx882); ix881 : mux21 port map ( Y=>nx880, A0=>nx1797, A1=>nx1793, S0=>nx652); ix883 : xnor2 port map ( Y=>nx882, A0=>PRI_OUT_4_4_EXMPLR, A1=>nx1907); ix1908 : mux21 port map ( Y=>nx1907, A0=>reg_2_q_c_4, A1=> PRI_OUT_0_4_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_4 : dff port map ( Q=>PRI_OUT_1_4_EXMPLR, QB=>OPEN, D=>nx906, CLK=>CLK); ix907 : xor2 port map ( Y=>nx906, A0=>nx902, A1=>nx904); ix903 : mux21 port map ( Y=>nx902, A0=>nx1781, A1=>nx1803, S0=>nx674); ix905 : xnor2 port map ( Y=>nx904, A0=>PRI_OUT_0_4_EXMPLR, A1=>nx1891); REG_9_reg_q_4 : dff port map ( Q=>reg_9_q_c_4, QB=>OPEN, D=>nx1012, CLK=> CLK); ix1013 : xor2 port map ( Y=>nx1012, A0=>nx980, A1=>nx1010); ix981 : mux21 port map ( Y=>nx980, A0=>PRI_IN_3(3), A1=>nx1817, S0=>nx780 ); ix1011 : xnor2 port map ( Y=>nx1010, A0=>PRI_IN_3(4), A1=>nx1008); ix1009 : ao21 port map ( Y=>nx1008, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_4, B0 =>nx984); REG_1_reg_q_4 : dff port map ( Q=>reg_1_q_c_4, QB=>OPEN, D=>nx998, CLK=> CLK); ix999 : xor2 port map ( Y=>nx998, A0=>nx994, A1=>nx996); ix995 : mux21 port map ( Y=>nx994, A0=>PRI_IN_0(3), A1=>nx1829, S0=>nx766 ); ix997 : xnor2 port map ( Y=>nx996, A0=>PRI_IN_0(4), A1=> PRI_OUT_2_4_EXMPLR); ix985 : nor02 port map ( Y=>nx984, A0=>C_MUX2_3_SEL, A1=>nx1907); REG_8_reg_q_5 : dff port map ( Q=>PRI_OUT_4_5_EXMPLR, QB=>OPEN, D=>nx1252, CLK=>CLK); ix1253 : xor2 port map ( Y=>nx1252, A0=>nx1038, A1=>nx1250); ix1039 : mux21 port map ( Y=>nx1038, A0=>reg_5_q_c_4, A1=>nx1843, S0=> nx1020); REG_5_reg_q_5 : dff port map ( Q=>reg_5_q_c_5, QB=>nx2029, D=>nx1194, CLK =>CLK); ix1195 : xnor2 port map ( Y=>nx1194, A0=>nx1048, A1=>nx1949); ix1049 : mux21 port map ( Y=>nx1048, A0=>nx1849, A1=>PRI_IN_4(4), S0=> nx1853); ix1950 : xnor2 port map ( Y=>nx1949, A0=>PRI_IN_4(5), A1=>nx1951); ix1952 : mux21 port map ( Y=>nx1951, A0=>reg_5_q_c_5, A1=>reg_2_q_c_5, S0 =>C_MUX2_2_SEL); ix1181 : xnor2 port map ( Y=>nx1180, A0=>nx1060, A1=>nx1959); ix1061 : mux21 port map ( Y=>nx1060, A0=>nx1859, A1=>nx1921, S0=>nx1863); ix1960 : xnor2 port map ( Y=>nx1959, A0=>PRI_IN_2(5), A1=>reg_10_q_c_5); REG_10_reg_q_5 : dff port map ( Q=>reg_10_q_c_5, QB=>OPEN, D=>nx1170, CLK =>CLK); ix1171 : xnor2 port map ( Y=>nx1170, A0=>nx1068, A1=>nx1969); ix1069 : ao21 port map ( Y=>nx1068, A0=>PRI_OUT_0_4_EXMPLR, A1=> PRI_IN_1(4), B0=>nx1066); ix1970 : xnor2 port map ( Y=>nx1969, A0=>PRI_IN_1(5), A1=> PRI_OUT_0_5_EXMPLR); REG_3_reg_q_5 : dff port map ( Q=>PRI_OUT_0_5_EXMPLR, QB=>OPEN, D=>nx1160, CLK=>CLK); ix1161 : xnor2 port map ( Y=>nx1160, A0=>nx1076, A1=>nx1975); ix1077 : mux21 port map ( Y=>nx1076, A0=>nx1875, A1=>nx1921, S0=>nx1879); ix1976 : xnor2 port map ( Y=>nx1975, A0=>PRI_OUT_3_5_EXMPLR, A1=> reg_10_q_c_5); REG_4_reg_q_5 : dff port map ( Q=>PRI_OUT_3_5_EXMPLR, QB=>OPEN, D=>nx1150, CLK=>CLK); ix1151 : xnor2 port map ( Y=>nx1150, A0=>nx1981, A1=>nx1148); ix1992 : mux21 port map ( Y=>nx1991, A0=>PRI_OUT_3_5_EXMPLR, A1=>nx1098, S0=>C_MUX2_5_SEL); REG_2_reg_q_5 : dff port map ( Q=>reg_2_q_c_5, QB=>OPEN, D=>nx1180, CLK=> CLK); REG_6_reg_q_5 : dff port map ( Q=>PRI_OUT_2_5_EXMPLR, QB=>OPEN, D=>nx1114, CLK=>CLK); ix1115 : xnor2 port map ( Y=>nx1114, A0=>nx2005, A1=>nx1112); ix2006 : aoi22 port map ( Y=>nx2005, A0=>nx868, A1=>PRI_OUT_4_4_EXMPLR, B0=>nx880, B1=>nx882); ix1113 : xnor2 port map ( Y=>nx1112, A0=>PRI_OUT_4_5_EXMPLR, A1=>nx2009); ix2010 : mux21 port map ( Y=>nx2009, A0=>reg_2_q_c_5, A1=> PRI_OUT_0_5_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_5 : dff port map ( Q=>PRI_OUT_1_5_EXMPLR, QB=>OPEN, D=>nx1136, CLK=>CLK); ix1137 : xnor2 port map ( Y=>nx1136, A0=>nx2015, A1=>nx1134); ix2016 : aoi22 port map ( Y=>nx2015, A0=>nx872, A1=>nx3666, B0=>nx902, B1 =>nx904); ix1135 : xnor2 port map ( Y=>nx1134, A0=>PRI_OUT_0_5_EXMPLR, A1=>nx1991); REG_9_reg_q_5 : dff port map ( Q=>reg_9_q_c_5, QB=>OPEN, D=>nx1242, CLK=> CLK); ix1243 : xnor2 port map ( Y=>nx1242, A0=>nx2033, A1=>nx1240); ix2034 : mux21 port map ( Y=>nx2033, A0=>nx2035, A1=>nx980, S0=>nx1010); ix2036 : inv02 port map ( Y=>nx2035, A=>PRI_IN_3(4)); ix1241 : xnor2 port map ( Y=>nx1240, A0=>PRI_IN_3(5), A1=>nx1238); ix1239 : ao21 port map ( Y=>nx1238, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_5, B0 =>nx1214); REG_1_reg_q_5 : dff port map ( Q=>reg_1_q_c_5, QB=>OPEN, D=>nx1228, CLK=> CLK); ix1229 : xnor2 port map ( Y=>nx1228, A0=>nx2041, A1=>nx1226); ix2042 : aoi22 port map ( Y=>nx2041, A0=>nx2043, A1=>PRI_OUT_2_4_EXMPLR, B0=>nx994, B1=>nx996); ix2044 : inv02 port map ( Y=>nx2043, A=>PRI_IN_0(4)); ix1227 : xnor2 port map ( Y=>nx1226, A0=>PRI_IN_0(5), A1=> PRI_OUT_2_5_EXMPLR); ix1215 : nor02 port map ( Y=>nx1214, A0=>C_MUX2_3_SEL, A1=>nx2009); REG_8_reg_q_6 : dff port map ( Q=>PRI_OUT_4_6_EXMPLR, QB=>OPEN, D=>nx1482, CLK=>CLK); ix1483 : xnor2 port map ( Y=>nx1482, A0=>nx2055, A1=>nx1480); ix2056 : aoi22 port map ( Y=>nx2055, A0=>nx2029, A1=>reg_9_q_c_5, B0=> nx1038, B1=>nx1250); ix1481 : xnor2 port map ( Y=>nx1480, A0=>reg_5_q_c_6, A1=>reg_9_q_c_6); REG_5_reg_q_6 : dff port map ( Q=>reg_5_q_c_6, QB=>OPEN, D=>nx1424, CLK=> CLK); ix1425 : xor2 port map ( Y=>nx1424, A0=>nx2061, A1=>nx2065); ix2062 : mux21 port map ( Y=>nx2061, A0=>nx1048, A1=>nx2063, S0=>nx1949); ix2064 : inv02 port map ( Y=>nx2063, A=>PRI_IN_4(5)); ix2066 : xnor2 port map ( Y=>nx2065, A0=>PRI_IN_4(6), A1=>nx2067); ix2068 : mux21 port map ( Y=>nx2067, A0=>reg_5_q_c_6, A1=>reg_2_q_c_6, S0 =>C_MUX2_2_SEL); ix1411 : xor2 port map ( Y=>nx1410, A0=>nx2073, A1=>nx2076); ix2074 : aoi22 port map ( Y=>nx2073, A0=>reg_10_q_c_5, A1=>PRI_IN_2(5), B0=>nx1060, B1=>nx1178); REG_10_reg_q_6 : dff port map ( Q=>OPEN, QB=>nx2133, D=>nx1400, CLK=>CLK ); ix1401 : xor2 port map ( Y=>nx1400, A0=>nx2081, A1=>nx2084); ix2082 : aoi22 port map ( Y=>nx2081, A0=>PRI_OUT_0_5_EXMPLR, A1=> PRI_IN_1(5), B0=>nx1068, B1=>nx1168); REG_3_reg_q_6 : dff port map ( Q=>PRI_OUT_0_dup0_6, QB=>OPEN, D=>nx1390, CLK=>CLK); ix1391 : xor2 port map ( Y=>nx1390, A0=>nx2089, A1=>nx2093); ix2090 : aoi22 port map ( Y=>nx2089, A0=>reg_10_q_c_5, A1=> PRI_OUT_3_5_EXMPLR, B0=>nx1076, B1=>nx1158); REG_4_reg_q_6 : dff port map ( Q=>PRI_OUT_3_6_EXMPLR, QB=>OPEN, D=>nx1380, CLK=>CLK); ix1381 : xnor2 port map ( Y=>nx1380, A0=>nx2097, A1=>nx1378); ix2106 : mux21 port map ( Y=>nx2105, A0=>PRI_OUT_3_6_EXMPLR, A1=>nx1328, S0=>C_MUX2_5_SEL); REG_2_reg_q_6 : dff port map ( Q=>reg_2_q_c_6, QB=>OPEN, D=>nx1410, CLK=> CLK); REG_6_reg_q_6 : dff port map ( Q=>PRI_OUT_2_6_EXMPLR, QB=>OPEN, D=>nx1344, CLK=>CLK); ix1345 : xor2 port map ( Y=>nx1344, A0=>nx1340, A1=>nx1342); ix1341 : mux21 port map ( Y=>nx1340, A0=>nx2009, A1=>nx2005, S0=>nx1112); ix1343 : xnor2 port map ( Y=>nx1342, A0=>PRI_OUT_4_6_EXMPLR, A1=>nx2119); ix2120 : mux21 port map ( Y=>nx2119, A0=>reg_2_q_c_6, A1=> PRI_OUT_0_6_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_6 : dff port map ( Q=>PRI_OUT_1_6_EXMPLR, QB=>OPEN, D=>nx1366, CLK=>CLK); ix1367 : xor2 port map ( Y=>nx1366, A0=>nx1362, A1=>nx1364); ix1363 : mux21 port map ( Y=>nx1362, A0=>nx1991, A1=>nx2015, S0=>nx1134); ix1365 : xnor2 port map ( Y=>nx1364, A0=>PRI_OUT_0_6_EXMPLR, A1=>nx2105); REG_9_reg_q_6 : dff port map ( Q=>reg_9_q_c_6, QB=>OPEN, D=>nx1472, CLK=> CLK); ix1473 : xor2 port map ( Y=>nx1472, A0=>nx1440, A1=>nx1470); ix1441 : mux21 port map ( Y=>nx1440, A0=>PRI_IN_3(5), A1=>nx2033, S0=> nx1240); ix1471 : xnor2 port map ( Y=>nx1470, A0=>PRI_IN_3(6), A1=>nx1468); ix1469 : ao21 port map ( Y=>nx1468, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_6, B0 =>nx1444); REG_1_reg_q_6 : dff port map ( Q=>reg_1_q_c_6, QB=>OPEN, D=>nx1458, CLK=> CLK); ix1459 : xor2 port map ( Y=>nx1458, A0=>nx1454, A1=>nx1456); ix1455 : mux21 port map ( Y=>nx1454, A0=>PRI_IN_0(5), A1=>nx2041, S0=> nx1226); ix1457 : xnor2 port map ( Y=>nx1456, A0=>PRI_IN_0(6), A1=> PRI_OUT_2_6_EXMPLR); ix1445 : nor02 port map ( Y=>nx1444, A0=>C_MUX2_3_SEL, A1=>nx2119); REG_8_reg_q_7 : dff port map ( Q=>PRI_OUT_4_7_EXMPLR, QB=>OPEN, D=>nx1712, CLK=>CLK); ix1713 : xor2 port map ( Y=>nx1712, A0=>nx1498, A1=>nx1710); ix1499 : mux21 port map ( Y=>nx1498, A0=>reg_5_q_c_6, A1=>nx2055, S0=> nx1480); REG_5_reg_q_7 : dff port map ( Q=>reg_5_q_c_7, QB=>nx2242, D=>nx1654, CLK =>CLK); ix1655 : xnor2 port map ( Y=>nx1654, A0=>nx1508, A1=>nx2167); ix1509 : mux21 port map ( Y=>nx1508, A0=>nx2061, A1=>PRI_IN_4(6), S0=> nx2065); ix2168 : xnor2 port map ( Y=>nx2167, A0=>PRI_IN_4(7), A1=>nx2169); ix2170 : mux21 port map ( Y=>nx2169, A0=>reg_5_q_c_7, A1=>reg_2_q_c_7, S0 =>C_MUX2_2_SEL); ix1641 : xnor2 port map ( Y=>nx1640, A0=>nx1520, A1=>nx2176); ix1521 : mux21 port map ( Y=>nx1520, A0=>nx2073, A1=>nx2133, S0=>nx2076); ix2177 : xnor2 port map ( Y=>nx2176, A0=>PRI_IN_2(7), A1=>reg_10_q_c_7); REG_10_reg_q_7 : dff port map ( Q=>reg_10_q_c_7, QB=>OPEN, D=>nx1630, CLK =>CLK); ix1631 : xnor2 port map ( Y=>nx1630, A0=>nx1528, A1=>nx2183); ix2184 : xnor2 port map ( Y=>nx2183, A0=>PRI_IN_1(7), A1=> PRI_OUT_0_7_EXMPLR); REG_3_reg_q_7 : dff port map ( Q=>PRI_OUT_0_dup0_7, QB=>OPEN, D=>nx1620, CLK=>CLK); ix1621 : xnor2 port map ( Y=>nx1620, A0=>nx1536, A1=>nx2191); ix1537 : mux21 port map ( Y=>nx1536, A0=>nx2089, A1=>nx2133, S0=>nx2093); ix2192 : xnor2 port map ( Y=>nx2191, A0=>PRI_OUT_3_7_EXMPLR, A1=> reg_10_q_c_7); REG_4_reg_q_7 : dff port map ( Q=>PRI_OUT_3_dup0_7, QB=>OPEN, D=>nx1610, CLK=>CLK); ix1611 : xnor2 port map ( Y=>nx1610, A0=>nx2197, A1=>nx1608); REG_2_reg_q_7 : dff port map ( Q=>reg_2_q_c_7, QB=>OPEN, D=>nx1640, CLK=> CLK); REG_6_reg_q_7 : dff port map ( Q=>PRI_OUT_2_7_EXMPLR, QB=>OPEN, D=>nx1574, CLK=>CLK); ix1575 : xnor2 port map ( Y=>nx1574, A0=>nx2219, A1=>nx1572); ix2220 : aoi22 port map ( Y=>nx2219, A0=>nx1328, A1=>PRI_OUT_4_6_EXMPLR, B0=>nx1340, B1=>nx1342); ix1573 : xnor2 port map ( Y=>nx1572, A0=>PRI_OUT_4_7_EXMPLR, A1=>nx2223); ix2224 : mux21 port map ( Y=>nx2223, A0=>reg_2_q_c_7, A1=> PRI_OUT_0_7_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_7 : dff port map ( Q=>PRI_OUT_1_7_EXMPLR, QB=>OPEN, D=>nx1596, CLK=>CLK); ix1597 : xnor2 port map ( Y=>nx1596, A0=>nx2229, A1=>nx1594); ix2230 : aoi22 port map ( Y=>nx2229, A0=>nx1332, A1=>PRI_OUT_0_6_EXMPLR, B0=>nx1362, B1=>nx1364); REG_9_reg_q_7 : dff port map ( Q=>reg_9_q_c_7, QB=>OPEN, D=>nx1702, CLK=> CLK); ix1703 : xnor2 port map ( Y=>nx1702, A0=>nx2245, A1=>nx1700); ix2246 : mux21 port map ( Y=>nx2245, A0=>nx2247, A1=>nx1440, S0=>nx1470); ix2248 : inv02 port map ( Y=>nx2247, A=>PRI_IN_3(6)); ix1701 : xnor2 port map ( Y=>nx1700, A0=>PRI_IN_3(7), A1=>nx1698); ix1699 : ao21 port map ( Y=>nx1698, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_7, B0 =>nx1674); REG_1_reg_q_7 : dff port map ( Q=>reg_1_q_c_7, QB=>OPEN, D=>nx1688, CLK=> CLK); ix1689 : xnor2 port map ( Y=>nx1688, A0=>nx2257, A1=>nx1686); ix2258 : aoi22 port map ( Y=>nx2257, A0=>nx2259, A1=>PRI_OUT_2_6_EXMPLR, B0=>nx1454, B1=>nx1456); ix2260 : inv02 port map ( Y=>nx2259, A=>PRI_IN_0(6)); ix1687 : xnor2 port map ( Y=>nx1686, A0=>PRI_IN_0(7), A1=> PRI_OUT_2_7_EXMPLR); ix1675 : nor02 port map ( Y=>nx1674, A0=>C_MUX2_3_SEL, A1=>nx2223); REG_8_reg_q_8 : dff port map ( Q=>PRI_OUT_4_8_EXMPLR, QB=>OPEN, D=>nx1942, CLK=>CLK); ix1943 : xnor2 port map ( Y=>nx1942, A0=>nx2269, A1=>nx1940); ix2270 : aoi22 port map ( Y=>nx2269, A0=>nx2242, A1=>reg_9_q_c_7, B0=> nx1498, B1=>nx1710); ix1941 : xnor2 port map ( Y=>nx1940, A0=>reg_5_q_c_8, A1=>reg_9_q_c_8); REG_5_reg_q_8 : dff port map ( Q=>reg_5_q_c_8, QB=>OPEN, D=>nx1884, CLK=> CLK); ix1885 : xor2 port map ( Y=>nx1884, A0=>nx2275, A1=>nx2279); ix2276 : mux21 port map ( Y=>nx2275, A0=>nx1508, A1=>nx2277, S0=>nx2167); ix2278 : inv02 port map ( Y=>nx2277, A=>PRI_IN_4(7)); ix2280 : xnor2 port map ( Y=>nx2279, A0=>PRI_IN_4(8), A1=>nx2281); ix2282 : mux21 port map ( Y=>nx2281, A0=>reg_5_q_c_8, A1=>reg_2_q_c_8, S0 =>C_MUX2_2_SEL); ix1871 : xor2 port map ( Y=>nx1870, A0=>nx2287, A1=>nx2290); ix2288 : aoi22 port map ( Y=>nx2287, A0=>reg_10_q_c_7, A1=>PRI_IN_2(7), B0=>nx1520, B1=>nx1638); REG_10_reg_q_8 : dff port map ( Q=>OPEN, QB=>nx2347, D=>nx1860, CLK=>CLK ); ix1861 : xor2 port map ( Y=>nx1860, A0=>nx2295, A1=>nx2299); REG_3_reg_q_8 : dff port map ( Q=>PRI_OUT_0_dup0_8, QB=>OPEN, D=>nx1850, CLK=>CLK); ix1851 : xor2 port map ( Y=>nx1850, A0=>nx2304, A1=>nx2307); ix2305 : aoi22 port map ( Y=>nx2304, A0=>reg_10_q_c_7, A1=> PRI_OUT_3_7_EXMPLR, B0=>nx1536, B1=>nx1618); REG_4_reg_q_8 : dff port map ( Q=>PRI_OUT_3_8_EXMPLR, QB=>OPEN, D=>nx1840, CLK=>CLK); ix1841 : xnor2 port map ( Y=>nx1840, A0=>nx2313, A1=>nx1838); ix2320 : mux21 port map ( Y=>nx2319, A0=>PRI_OUT_3_8_EXMPLR, A1=>nx1788, S0=>C_MUX2_5_SEL); REG_2_reg_q_8 : dff port map ( Q=>reg_2_q_c_8, QB=>OPEN, D=>nx1870, CLK=> CLK); REG_6_reg_q_8 : dff port map ( Q=>PRI_OUT_2_8_EXMPLR, QB=>OPEN, D=>nx1804, CLK=>CLK); ix1805 : xor2 port map ( Y=>nx1804, A0=>nx1800, A1=>nx1802); ix1801 : mux21 port map ( Y=>nx1800, A0=>nx2223, A1=>nx2219, S0=>nx1572); ix1803 : xnor2 port map ( Y=>nx1802, A0=>PRI_OUT_4_8_EXMPLR, A1=>nx2334); ix2335 : mux21 port map ( Y=>nx2334, A0=>reg_2_q_c_8, A1=> PRI_OUT_0_8_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_8 : dff port map ( Q=>PRI_OUT_1_8_EXMPLR, QB=>OPEN, D=>nx1826, CLK=>CLK); ix1827 : xor2 port map ( Y=>nx1826, A0=>nx3555, A1=>nx1824); REG_9_reg_q_8 : dff port map ( Q=>reg_9_q_c_8, QB=>OPEN, D=>nx1932, CLK=> CLK); ix1933 : xor2 port map ( Y=>nx1932, A0=>nx1900, A1=>nx1930); ix1901 : mux21 port map ( Y=>nx1900, A0=>PRI_IN_3(7), A1=>nx2245, S0=> nx1700); ix1931 : xnor2 port map ( Y=>nx1930, A0=>PRI_IN_3(8), A1=>nx1928); ix1929 : ao21 port map ( Y=>nx1928, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_8, B0 =>nx1904); REG_1_reg_q_8 : dff port map ( Q=>reg_1_q_c_8, QB=>OPEN, D=>nx1918, CLK=> CLK); ix1919 : xor2 port map ( Y=>nx1918, A0=>nx1914, A1=>nx1916); ix1915 : mux21 port map ( Y=>nx1914, A0=>PRI_IN_0(7), A1=>nx2257, S0=> nx1686); ix1917 : xnor2 port map ( Y=>nx1916, A0=>PRI_IN_0(8), A1=> PRI_OUT_2_8_EXMPLR); ix1905 : nor02 port map ( Y=>nx1904, A0=>C_MUX2_3_SEL, A1=>nx2334); REG_8_reg_q_9 : dff port map ( Q=>PRI_OUT_4_9_EXMPLR, QB=>OPEN, D=>nx2172, CLK=>CLK); ix2173 : xor2 port map ( Y=>nx2172, A0=>nx1958, A1=>nx2170); ix1959 : mux21 port map ( Y=>nx1958, A0=>reg_5_q_c_8, A1=>nx2269, S0=> nx1940); REG_5_reg_q_9 : dff port map ( Q=>reg_5_q_c_9, QB=>nx2453, D=>nx2114, CLK =>CLK); ix2115 : xnor2 port map ( Y=>nx2114, A0=>nx1968, A1=>nx2381); ix1969 : mux21 port map ( Y=>nx1968, A0=>nx2275, A1=>PRI_IN_4(8), S0=> nx2279); ix2382 : xnor2 port map ( Y=>nx2381, A0=>PRI_IN_4(9), A1=>nx2383); ix2384 : mux21 port map ( Y=>nx2383, A0=>reg_5_q_c_9, A1=>reg_2_q_c_9, S0 =>C_MUX2_2_SEL); ix2101 : xnor2 port map ( Y=>nx2100, A0=>nx1980, A1=>nx2389); ix1981 : mux21 port map ( Y=>nx1980, A0=>nx2287, A1=>nx2347, S0=>nx2290); ix2390 : xnor2 port map ( Y=>nx2389, A0=>PRI_IN_2(9), A1=>reg_10_q_c_9); REG_10_reg_q_9 : dff port map ( Q=>reg_10_q_c_9, QB=>OPEN, D=>nx2090, CLK =>CLK); ix2091 : xnor2 port map ( Y=>nx2090, A0=>nx1988, A1=>nx2397); ix2398 : xnor2 port map ( Y=>nx2397, A0=>PRI_IN_1(9), A1=> PRI_OUT_0_9_EXMPLR); REG_3_reg_q_9 : dff port map ( Q=>PRI_OUT_0_dup0_9, QB=>OPEN, D=>nx2080, CLK=>CLK); ix2081 : xnor2 port map ( Y=>nx2080, A0=>nx1996, A1=>nx2403); ix1997 : mux21 port map ( Y=>nx1996, A0=>nx2304, A1=>nx2347, S0=>nx2307); ix2404 : xnor2 port map ( Y=>nx2403, A0=>PRI_OUT_3_9_EXMPLR, A1=> reg_10_q_c_9); REG_4_reg_q_9 : dff port map ( Q=>PRI_OUT_3_9_EXMPLR, QB=>OPEN, D=>nx2070, CLK=>CLK); ix2071 : xnor2 port map ( Y=>nx2070, A0=>nx2407, A1=>nx2068); REG_2_reg_q_9 : dff port map ( Q=>reg_2_q_c_9, QB=>OPEN, D=>nx2100, CLK=> CLK); REG_6_reg_q_9 : dff port map ( Q=>PRI_OUT_2_9_EXMPLR, QB=>OPEN, D=>nx2034, CLK=>CLK); ix2035 : xnor2 port map ( Y=>nx2034, A0=>nx2429, A1=>nx2032); ix2430 : aoi22 port map ( Y=>nx2429, A0=>nx1788, A1=>PRI_OUT_4_8_EXMPLR, B0=>nx1800, B1=>nx1802); ix2033 : xnor2 port map ( Y=>nx2032, A0=>PRI_OUT_4_9_EXMPLR, A1=>nx2433); ix2434 : mux21 port map ( Y=>nx2433, A0=>reg_2_q_c_9, A1=> PRI_OUT_0_9_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_9 : dff port map ( Q=>PRI_OUT_1_9_EXMPLR, QB=>OPEN, D=>nx2056, CLK=>CLK); ix2057 : xnor2 port map ( Y=>nx2056, A0=>nx2439, A1=>nx2054); REG_9_reg_q_9 : dff port map ( Q=>reg_9_q_c_9, QB=>OPEN, D=>nx2162, CLK=> CLK); ix2163 : xnor2 port map ( Y=>nx2162, A0=>nx2457, A1=>nx2160); ix2458 : mux21 port map ( Y=>nx2457, A0=>nx2459, A1=>nx1900, S0=>nx1930); ix2460 : inv02 port map ( Y=>nx2459, A=>PRI_IN_3(8)); ix2161 : xnor2 port map ( Y=>nx2160, A0=>PRI_IN_3(9), A1=>nx2158); ix2159 : ao21 port map ( Y=>nx2158, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_9, B0 =>nx2134); REG_1_reg_q_9 : dff port map ( Q=>reg_1_q_c_9, QB=>OPEN, D=>nx2148, CLK=> CLK); ix2149 : xnor2 port map ( Y=>nx2148, A0=>nx2469, A1=>nx2146); ix2470 : aoi22 port map ( Y=>nx2469, A0=>nx2471, A1=>PRI_OUT_2_8_EXMPLR, B0=>nx1914, B1=>nx1916); ix2472 : inv02 port map ( Y=>nx2471, A=>PRI_IN_0(8)); ix2147 : xnor2 port map ( Y=>nx2146, A0=>PRI_IN_0(9), A1=> PRI_OUT_2_9_EXMPLR); ix2135 : nor02 port map ( Y=>nx2134, A0=>C_MUX2_3_SEL, A1=>nx2433); REG_8_reg_q_10 : dff port map ( Q=>PRI_OUT_4_10_EXMPLR, QB=>OPEN, D=> nx2402, CLK=>CLK); ix2403 : xnor2 port map ( Y=>nx2402, A0=>nx2483, A1=>nx2400); ix2484 : aoi22 port map ( Y=>nx2483, A0=>nx2453, A1=>reg_9_q_c_9, B0=> nx1958, B1=>nx2170); ix2401 : xnor2 port map ( Y=>nx2400, A0=>reg_5_q_c_10, A1=>reg_9_q_c_10); REG_5_reg_q_10 : dff port map ( Q=>reg_5_q_c_10, QB=>OPEN, D=>nx2344, CLK =>CLK); ix2345 : xor2 port map ( Y=>nx2344, A0=>nx2491, A1=>nx2495); ix2492 : mux21 port map ( Y=>nx2491, A0=>nx1968, A1=>nx2493, S0=>nx2381); ix2494 : inv02 port map ( Y=>nx2493, A=>PRI_IN_4(9)); ix2496 : xnor2 port map ( Y=>nx2495, A0=>PRI_IN_4(10), A1=>nx2497); ix2498 : mux21 port map ( Y=>nx2497, A0=>reg_5_q_c_10, A1=>reg_2_q_c_10, S0=>C_MUX2_2_SEL); ix2331 : xor2 port map ( Y=>nx2330, A0=>nx2501, A1=>nx2505); ix2502 : aoi22 port map ( Y=>nx2501, A0=>reg_10_q_c_9, A1=>PRI_IN_2(9), B0=>nx1980, B1=>nx2098); REG_10_reg_q_10 : dff port map ( Q=>OPEN, QB=>nx2561, D=>nx2320, CLK=>CLK ); ix2321 : xor2 port map ( Y=>nx2320, A0=>nx2511, A1=>nx2515); REG_3_reg_q_10 : dff port map ( Q=>PRI_OUT_0_dup0_10, QB=>OPEN, D=>nx2310, CLK=>CLK); ix2311 : xor2 port map ( Y=>nx2310, A0=>nx2520, A1=>nx2523); ix2521 : aoi22 port map ( Y=>nx2520, A0=>reg_10_q_c_9, A1=> PRI_OUT_3_9_EXMPLR, B0=>nx1996, B1=>nx2078); REG_4_reg_q_10 : dff port map ( Q=>PRI_OUT_3_10_EXMPLR, QB=>OPEN, D=> nx2300, CLK=>CLK); ix2301 : xnor2 port map ( Y=>nx2300, A0=>nx2529, A1=>nx2298); ix2537 : mux21 port map ( Y=>nx2536, A0=>PRI_OUT_3_10_EXMPLR, A1=>nx2248, S0=>C_MUX2_5_SEL); REG_2_reg_q_10 : dff port map ( Q=>reg_2_q_c_10, QB=>OPEN, D=>nx2330, CLK =>CLK); REG_6_reg_q_10 : dff port map ( Q=>PRI_OUT_2_10_EXMPLR, QB=>OPEN, D=> nx2264, CLK=>CLK); ix2265 : xor2 port map ( Y=>nx2264, A0=>nx2260, A1=>nx2262); ix2261 : mux21 port map ( Y=>nx2260, A0=>nx2433, A1=>nx2429, S0=>nx2032); ix2263 : xnor2 port map ( Y=>nx2262, A0=>PRI_OUT_4_10_EXMPLR, A1=>nx2549 ); ix2550 : mux21 port map ( Y=>nx2549, A0=>reg_2_q_c_10, A1=> PRI_OUT_0_10_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_10 : dff port map ( Q=>PRI_OUT_1_10_EXMPLR, QB=>OPEN, D=> nx2286, CLK=>CLK); ix2287 : xor2 port map ( Y=>nx2286, A0=>nx3549, A1=>nx2284); REG_9_reg_q_10 : dff port map ( Q=>reg_9_q_c_10, QB=>OPEN, D=>nx2392, CLK =>CLK); ix2393 : xor2 port map ( Y=>nx2392, A0=>nx2360, A1=>nx2390); ix2361 : mux21 port map ( Y=>nx2360, A0=>PRI_IN_3(9), A1=>nx2457, S0=> nx2160); ix2391 : xnor2 port map ( Y=>nx2390, A0=>PRI_IN_3(10), A1=>nx2388); ix2389 : ao21 port map ( Y=>nx2388, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_10, B0=>nx2364); REG_1_reg_q_10 : dff port map ( Q=>reg_1_q_c_10, QB=>OPEN, D=>nx2378, CLK =>CLK); ix2379 : xor2 port map ( Y=>nx2378, A0=>nx2374, A1=>nx2376); ix2375 : mux21 port map ( Y=>nx2374, A0=>PRI_IN_0(9), A1=>nx2469, S0=> nx2146); ix2377 : xnor2 port map ( Y=>nx2376, A0=>PRI_IN_0(10), A1=> PRI_OUT_2_10_EXMPLR); ix2365 : nor02 port map ( Y=>nx2364, A0=>C_MUX2_3_SEL, A1=>nx2549); REG_8_reg_q_11 : dff port map ( Q=>PRI_OUT_4_11_EXMPLR, QB=>OPEN, D=> nx2632, CLK=>CLK); ix2633 : xor2 port map ( Y=>nx2632, A0=>nx2418, A1=>nx2630); ix2419 : mux21 port map ( Y=>nx2418, A0=>reg_5_q_c_10, A1=>nx2483, S0=> nx2400); REG_5_reg_q_11 : dff port map ( Q=>reg_5_q_c_11, QB=>nx2661, D=>nx2574, CLK=>CLK); ix2575 : xnor2 port map ( Y=>nx2574, A0=>nx2428, A1=>nx2589); ix2429 : mux21 port map ( Y=>nx2428, A0=>nx2491, A1=>PRI_IN_4(10), S0=> nx2495); ix2590 : xnor2 port map ( Y=>nx2589, A0=>PRI_IN_4(11), A1=>nx2591); ix2592 : mux21 port map ( Y=>nx2591, A0=>reg_5_q_c_11, A1=>reg_2_q_c_11, S0=>C_MUX2_2_SEL); ix2561 : xnor2 port map ( Y=>nx2560, A0=>nx2440, A1=>nx2597); ix2441 : mux21 port map ( Y=>nx2440, A0=>nx2501, A1=>nx2561, S0=>nx2505); ix2598 : xnor2 port map ( Y=>nx2597, A0=>PRI_IN_2(11), A1=>reg_10_q_c_11 ); REG_10_reg_q_11 : dff port map ( Q=>reg_10_q_c_11, QB=>OPEN, D=>nx2550, CLK=>CLK); ix2551 : xnor2 port map ( Y=>nx2550, A0=>nx2448, A1=>nx2607); ix2608 : xnor2 port map ( Y=>nx2607, A0=>PRI_IN_1(11), A1=> PRI_OUT_0_11_EXMPLR); REG_3_reg_q_11 : dff port map ( Q=>PRI_OUT_0_11_EXMPLR, QB=>OPEN, D=> nx2540, CLK=>CLK); ix2541 : xnor2 port map ( Y=>nx2540, A0=>nx2456, A1=>nx2613); ix2457 : mux21 port map ( Y=>nx2456, A0=>nx2520, A1=>nx2561, S0=>nx2523); ix2614 : xnor2 port map ( Y=>nx2613, A0=>PRI_OUT_3_11_EXMPLR, A1=> reg_10_q_c_11); REG_4_reg_q_11 : dff port map ( Q=>PRI_OUT_3_11_EXMPLR, QB=>OPEN, D=> nx2530, CLK=>CLK); ix2531 : xnor2 port map ( Y=>nx2530, A0=>nx2617, A1=>nx2528); REG_2_reg_q_11 : dff port map ( Q=>reg_2_q_c_11, QB=>OPEN, D=>nx2560, CLK =>CLK); REG_6_reg_q_11 : dff port map ( Q=>PRI_OUT_2_11_EXMPLR, QB=>OPEN, D=> nx2494, CLK=>CLK); ix2495 : xnor2 port map ( Y=>nx2494, A0=>nx2637, A1=>nx2492); ix2638 : aoi22 port map ( Y=>nx2637, A0=>nx2248, A1=>PRI_OUT_4_10_EXMPLR, B0=>nx2260, B1=>nx2262); ix2493 : xnor2 port map ( Y=>nx2492, A0=>PRI_OUT_4_11_EXMPLR, A1=>nx2640 ); ix2642 : mux21 port map ( Y=>nx2640, A0=>reg_2_q_c_11, A1=> PRI_OUT_0_11_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_11 : dff port map ( Q=>PRI_OUT_1_11_EXMPLR, QB=>OPEN, D=> nx2516, CLK=>CLK); ix2517 : xnor2 port map ( Y=>nx2516, A0=>nx2647, A1=>nx2514); REG_9_reg_q_11 : dff port map ( Q=>reg_9_q_c_11, QB=>OPEN, D=>nx2622, CLK =>CLK); ix2623 : xnor2 port map ( Y=>nx2622, A0=>nx2665, A1=>nx2620); ix2666 : mux21 port map ( Y=>nx2665, A0=>nx2667, A1=>nx2360, S0=>nx2390); ix2668 : inv02 port map ( Y=>nx2667, A=>PRI_IN_3(10)); ix2621 : xnor2 port map ( Y=>nx2620, A0=>PRI_IN_3(11), A1=>nx2618); ix2619 : ao21 port map ( Y=>nx2618, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_11, B0=>nx2594); REG_1_reg_q_11 : dff port map ( Q=>reg_1_q_c_11, QB=>OPEN, D=>nx2608, CLK =>CLK); ix2609 : xnor2 port map ( Y=>nx2608, A0=>nx2677, A1=>nx2606); ix2678 : aoi22 port map ( Y=>nx2677, A0=>nx2679, A1=>PRI_OUT_2_10_EXMPLR, B0=>nx2374, B1=>nx2376); ix2680 : inv02 port map ( Y=>nx2679, A=>PRI_IN_0(10)); ix2607 : xnor2 port map ( Y=>nx2606, A0=>PRI_IN_0(11), A1=> PRI_OUT_2_11_EXMPLR); ix2595 : nor02 port map ( Y=>nx2594, A0=>C_MUX2_3_SEL, A1=>nx2640); REG_8_reg_q_12 : dff port map ( Q=>PRI_OUT_4_12_EXMPLR, QB=>OPEN, D=> nx2862, CLK=>CLK); ix2863 : xnor2 port map ( Y=>nx2862, A0=>nx2691, A1=>nx2860); ix2692 : aoi22 port map ( Y=>nx2691, A0=>nx2661, A1=>reg_9_q_c_11, B0=> nx2418, B1=>nx2630); ix2861 : xnor2 port map ( Y=>nx2860, A0=>reg_5_q_c_12, A1=>reg_9_q_c_12); REG_5_reg_q_12 : dff port map ( Q=>reg_5_q_c_12, QB=>OPEN, D=>nx2804, CLK =>CLK); ix2805 : xor2 port map ( Y=>nx2804, A0=>nx2699, A1=>nx2703); ix2700 : mux21 port map ( Y=>nx2699, A0=>nx2428, A1=>nx2701, S0=>nx2589); ix2702 : inv02 port map ( Y=>nx2701, A=>PRI_IN_4(11)); ix2704 : xnor2 port map ( Y=>nx2703, A0=>PRI_IN_4(12), A1=>nx2705); ix2706 : mux21 port map ( Y=>nx2705, A0=>reg_5_q_c_12, A1=>reg_2_q_c_12, S0=>C_MUX2_2_SEL); ix2791 : xor2 port map ( Y=>nx2790, A0=>nx2711, A1=>nx2715); ix2712 : aoi22 port map ( Y=>nx2711, A0=>reg_10_q_c_11, A1=>PRI_IN_2(11), B0=>nx2440, B1=>nx2558); REG_10_reg_q_12 : dff port map ( Q=>OPEN, QB=>nx2774, D=>nx2780, CLK=>CLK ); ix2781 : xor2 port map ( Y=>nx2780, A0=>nx2721, A1=>nx2725); ix2722 : aoi22 port map ( Y=>nx2721, A0=>PRI_OUT_0_11_EXMPLR, A1=> PRI_IN_1(11), B0=>nx3634, B1=>nx2548); ix2726 : xnor2 port map ( Y=>nx2725, A0=>PRI_IN_1(12), A1=> PRI_OUT_0_12_EXMPLR); REG_3_reg_q_12 : dff port map ( Q=>PRI_OUT_0_12_EXMPLR, QB=>OPEN, D=> nx2770, CLK=>CLK); ix2771 : xor2 port map ( Y=>nx2770, A0=>nx2729, A1=>nx2732); ix2730 : aoi22 port map ( Y=>nx2729, A0=>reg_10_q_c_11, A1=> PRI_OUT_3_11_EXMPLR, B0=>nx2456, B1=>nx2538); REG_4_reg_q_12 : dff port map ( Q=>PRI_OUT_3_12_EXMPLR, QB=>OPEN, D=> nx2760, CLK=>CLK); ix2761 : xnor2 port map ( Y=>nx2760, A0=>nx2737, A1=>nx2758); ix2748 : mux21 port map ( Y=>nx2747, A0=>PRI_OUT_3_12_EXMPLR, A1=>nx2708, S0=>C_MUX2_5_SEL); REG_2_reg_q_12 : dff port map ( Q=>reg_2_q_c_12, QB=>OPEN, D=>nx2790, CLK =>CLK); REG_6_reg_q_12 : dff port map ( Q=>PRI_OUT_2_12_EXMPLR, QB=>OPEN, D=> nx2724, CLK=>CLK); ix2725 : xor2 port map ( Y=>nx2724, A0=>nx2720, A1=>nx2722); ix2721 : mux21 port map ( Y=>nx2720, A0=>nx2640, A1=>nx2637, S0=>nx2492); ix2723 : xnor2 port map ( Y=>nx2722, A0=>PRI_OUT_4_12_EXMPLR, A1=>nx2763 ); ix2764 : mux21 port map ( Y=>nx2763, A0=>reg_2_q_c_12, A1=> PRI_OUT_0_12_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_12 : dff port map ( Q=>PRI_OUT_1_12_EXMPLR, QB=>OPEN, D=> nx2746, CLK=>CLK); ix2747 : xor2 port map ( Y=>nx2746, A0=>nx2742, A1=>nx2744); REG_9_reg_q_12 : dff port map ( Q=>reg_9_q_c_12, QB=>OPEN, D=>nx2852, CLK =>CLK); ix2853 : xor2 port map ( Y=>nx2852, A0=>nx2820, A1=>nx2850); ix2821 : mux21 port map ( Y=>nx2820, A0=>PRI_IN_3(11), A1=>nx2665, S0=> nx2620); ix2851 : xnor2 port map ( Y=>nx2850, A0=>PRI_IN_3(12), A1=>nx2848); ix2849 : ao21 port map ( Y=>nx2848, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_12, B0=>nx2824); REG_1_reg_q_12 : dff port map ( Q=>reg_1_q_c_12, QB=>OPEN, D=>nx2838, CLK =>CLK); ix2839 : xor2 port map ( Y=>nx2838, A0=>nx2834, A1=>nx2836); ix2835 : mux21 port map ( Y=>nx2834, A0=>PRI_IN_0(11), A1=>nx2677, S0=> nx2606); ix2837 : xnor2 port map ( Y=>nx2836, A0=>PRI_IN_0(12), A1=> PRI_OUT_2_12_EXMPLR); ix2825 : nor02 port map ( Y=>nx2824, A0=>C_MUX2_3_SEL, A1=>nx2763); REG_8_reg_q_13 : dff port map ( Q=>PRI_OUT_4_13_EXMPLR, QB=>OPEN, D=> nx3092, CLK=>CLK); ix3093 : xor2 port map ( Y=>nx3092, A0=>nx2878, A1=>nx3090); ix2879 : mux21 port map ( Y=>nx2878, A0=>reg_5_q_c_12, A1=>nx2691, S0=> nx2860); REG_5_reg_q_13 : dff port map ( Q=>reg_5_q_c_13, QB=>nx2871, D=>nx3034, CLK=>CLK); ix3035 : xnor2 port map ( Y=>nx3034, A0=>nx2888, A1=>nx2799); ix2889 : mux21 port map ( Y=>nx2888, A0=>nx2699, A1=>PRI_IN_4(12), S0=> nx2703); ix2800 : xnor2 port map ( Y=>nx2799, A0=>PRI_IN_4(13), A1=>nx2801); ix2802 : mux21 port map ( Y=>nx2801, A0=>reg_5_q_c_13, A1=>reg_2_q_c_13, S0=>C_MUX2_2_SEL); ix3021 : xnor2 port map ( Y=>nx3020, A0=>nx2900, A1=>nx2808); ix2901 : mux21 port map ( Y=>nx2900, A0=>nx2711, A1=>nx2774, S0=>nx2715); ix2809 : xnor2 port map ( Y=>nx2808, A0=>PRI_IN_2(13), A1=>reg_10_q_c_13 ); REG_10_reg_q_13 : dff port map ( Q=>reg_10_q_c_13, QB=>OPEN, D=>nx3010, CLK=>CLK); ix3011 : xnor2 port map ( Y=>nx3010, A0=>nx2908, A1=>nx2815); ix2907 : nor02 port map ( Y=>nx2906, A0=>nx2721, A1=>nx2725); ix2816 : xnor2 port map ( Y=>nx2815, A0=>PRI_IN_1(13), A1=> PRI_OUT_0_13_EXMPLR); REG_3_reg_q_13 : dff port map ( Q=>PRI_OUT_0_dup0_13, QB=>OPEN, D=>nx3000, CLK=>CLK); ix3001 : xnor2 port map ( Y=>nx3000, A0=>nx2916, A1=>nx2823); ix2917 : mux21 port map ( Y=>nx2916, A0=>nx2729, A1=>nx2774, S0=>nx2732); ix2824 : xnor2 port map ( Y=>nx2823, A0=>PRI_OUT_3_13_EXMPLR, A1=> reg_10_q_c_13); REG_4_reg_q_13 : dff port map ( Q=>PRI_OUT_3_13_EXMPLR, QB=>OPEN, D=> nx2990, CLK=>CLK); ix2991 : xnor2 port map ( Y=>nx2990, A0=>nx2829, A1=>nx2988); REG_2_reg_q_13 : dff port map ( Q=>reg_2_q_c_13, QB=>OPEN, D=>nx3020, CLK =>CLK); REG_6_reg_q_13 : dff port map ( Q=>PRI_OUT_2_13_EXMPLR, QB=>OPEN, D=> nx2954, CLK=>CLK); ix2955 : xnor2 port map ( Y=>nx2954, A0=>nx2851, A1=>nx2952); ix2852 : aoi22 port map ( Y=>nx2851, A0=>nx2708, A1=>PRI_OUT_4_12_EXMPLR, B0=>nx2720, B1=>nx2722); ix2953 : xnor2 port map ( Y=>nx2952, A0=>PRI_OUT_4_13_EXMPLR, A1=>nx2855 ); ix2856 : mux21 port map ( Y=>nx2855, A0=>reg_2_q_c_13, A1=> PRI_OUT_0_13_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_13 : dff port map ( Q=>PRI_OUT_1_13_EXMPLR, QB=>OPEN, D=> nx2976, CLK=>CLK); ix2977 : xnor2 port map ( Y=>nx2976, A0=>nx2861, A1=>nx2974); REG_9_reg_q_13 : dff port map ( Q=>reg_9_q_c_13, QB=>OPEN, D=>nx3082, CLK =>CLK); ix3083 : xnor2 port map ( Y=>nx3082, A0=>nx2875, A1=>nx3080); ix2876 : mux21 port map ( Y=>nx2875, A0=>nx2877, A1=>nx2820, S0=>nx2850); ix2878 : inv02 port map ( Y=>nx2877, A=>PRI_IN_3(12)); ix3081 : xnor2 port map ( Y=>nx3080, A0=>PRI_IN_3(13), A1=>nx3078); ix3079 : ao21 port map ( Y=>nx3078, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_13, B0=>nx3054); REG_1_reg_q_13 : dff port map ( Q=>reg_1_q_c_13, QB=>OPEN, D=>nx3068, CLK =>CLK); ix3069 : xnor2 port map ( Y=>nx3068, A0=>nx2887, A1=>nx3066); ix2888 : aoi22 port map ( Y=>nx2887, A0=>nx2889, A1=>PRI_OUT_2_12_EXMPLR, B0=>nx2834, B1=>nx2836); ix2890 : inv02 port map ( Y=>nx2889, A=>PRI_IN_0(12)); ix3067 : xnor2 port map ( Y=>nx3066, A0=>PRI_IN_0(13), A1=> PRI_OUT_2_13_EXMPLR); ix3055 : nor02 port map ( Y=>nx3054, A0=>C_MUX2_3_SEL, A1=>nx2855); REG_8_reg_q_14 : dff port map ( Q=>PRI_OUT_4_14_EXMPLR, QB=>OPEN, D=> nx3322, CLK=>CLK); ix3323 : xnor2 port map ( Y=>nx3322, A0=>nx2901, A1=>nx3320); ix2902 : aoi22 port map ( Y=>nx2901, A0=>nx2871, A1=>reg_9_q_c_13, B0=> nx2878, B1=>nx3090); ix3321 : xnor2 port map ( Y=>nx3320, A0=>reg_5_q_c_14, A1=>reg_9_q_c_14); REG_5_reg_q_14 : dff port map ( Q=>reg_5_q_c_14, QB=>OPEN, D=>nx3264, CLK =>CLK); ix3265 : xor2 port map ( Y=>nx3264, A0=>nx2909, A1=>nx2913); ix2910 : mux21 port map ( Y=>nx2909, A0=>nx2888, A1=>nx2911, S0=>nx2799); ix2912 : inv02 port map ( Y=>nx2911, A=>PRI_IN_4(13)); ix2914 : xnor2 port map ( Y=>nx2913, A0=>PRI_IN_4(14), A1=>nx2915); ix2916 : mux21 port map ( Y=>nx2915, A0=>reg_5_q_c_14, A1=>reg_2_q_c_14, S0=>C_MUX2_2_SEL); ix3251 : xor2 port map ( Y=>nx3250, A0=>nx2921, A1=>nx2925); ix2922 : aoi22 port map ( Y=>nx2921, A0=>reg_10_q_c_13, A1=>PRI_IN_2(13), B0=>nx2900, B1=>nx3018); REG_10_reg_q_14 : dff port map ( Q=>OPEN, QB=>nx2987, D=>nx3240, CLK=>CLK ); ix3241 : xor2 port map ( Y=>nx3240, A0=>nx2931, A1=>nx2935); REG_3_reg_q_14 : dff port map ( Q=>PRI_OUT_0_dup0_14, QB=>OPEN, D=>nx3230, CLK=>CLK); ix3231 : xor2 port map ( Y=>nx3230, A0=>nx2941, A1=>nx2945); ix2942 : aoi22 port map ( Y=>nx2941, A0=>reg_10_q_c_13, A1=> PRI_OUT_3_13_EXMPLR, B0=>nx2916, B1=>nx2998); REG_4_reg_q_14 : dff port map ( Q=>PRI_OUT_3_14_EXMPLR, QB=>OPEN, D=> nx3220, CLK=>CLK); ix3221 : xnor2 port map ( Y=>nx3220, A0=>nx2951, A1=>nx3218); ix3219 : xnor2 port map ( Y=>nx3218, A0=>nx2959, A1=>nx2965); ix2960 : mux21 port map ( Y=>nx2959, A0=>PRI_OUT_3_14_EXMPLR, A1=>nx3168, S0=>C_MUX2_5_SEL); REG_2_reg_q_14 : dff port map ( Q=>reg_2_q_c_14, QB=>OPEN, D=>nx3250, CLK =>CLK); ix2966 : mux21 port map ( Y=>nx2965, A0=>PRI_OUT_2_14_EXMPLR, A1=> PRI_OUT_1_14_EXMPLR, S0=>C_MUX2_4_SEL); REG_6_reg_q_14 : dff port map ( Q=>PRI_OUT_2_14_EXMPLR, QB=>OPEN, D=> nx3184, CLK=>CLK); ix3185 : xor2 port map ( Y=>nx3184, A0=>nx3180, A1=>nx3182); ix3181 : mux21 port map ( Y=>nx3180, A0=>nx2855, A1=>nx2851, S0=>nx2952); ix3183 : xnor2 port map ( Y=>nx3182, A0=>PRI_OUT_4_14_EXMPLR, A1=>nx2975 ); ix2976 : mux21 port map ( Y=>nx2975, A0=>reg_2_q_c_14, A1=> PRI_OUT_0_14_EXMPLR, S0=>C_MUX2_1_SEL); REG_7_reg_q_14 : dff port map ( Q=>PRI_OUT_1_14_EXMPLR, QB=>OPEN, D=> nx3206, CLK=>CLK); ix3207 : xor2 port map ( Y=>nx3206, A0=>nx3202, A1=>nx3204); REG_9_reg_q_14 : dff port map ( Q=>reg_9_q_c_14, QB=>OPEN, D=>nx3312, CLK =>CLK); ix3311 : xnor2 port map ( Y=>nx3310, A0=>PRI_IN_3(14), A1=>nx3308); ix3309 : ao21 port map ( Y=>nx3308, A0=>C_MUX2_3_SEL, A1=>reg_1_q_c_14, B0=>nx3284); REG_1_reg_q_14 : dff port map ( Q=>reg_1_q_c_14, QB=>OPEN, D=>nx3298, CLK =>CLK); ix3299 : xor2 port map ( Y=>nx3298, A0=>nx3294, A1=>nx3296); ix3295 : mux21 port map ( Y=>nx3294, A0=>PRI_IN_0(13), A1=>nx2887, S0=> nx3066); ix3297 : xnor2 port map ( Y=>nx3296, A0=>PRI_IN_0(14), A1=> PRI_OUT_2_14_EXMPLR); ix3285 : nor02 port map ( Y=>nx3284, A0=>C_MUX2_3_SEL, A1=>nx2975); REG_8_reg_q_15 : dff port map ( Q=>PRI_OUT_4_15_EXMPLR, QB=>OPEN, D=> nx3552, CLK=>CLK); ix3553 : xnor2 port map ( Y=>nx3552, A0=>nx3338, A1=>nx3009); ix3339 : mux21 port map ( Y=>nx3338, A0=>reg_5_q_c_14, A1=>nx2901, S0=> nx3320); ix3010 : xor2 port map ( Y=>nx3009, A0=>reg_5_q_c_15, A1=>reg_9_q_c_15); REG_5_reg_q_15 : dff port map ( Q=>reg_5_q_c_15, QB=>OPEN, D=>nx3494, CLK =>CLK); ix3495 : xnor2 port map ( Y=>nx3494, A0=>nx3348, A1=>nx3015); ix3349 : mux21 port map ( Y=>nx3348, A0=>nx2909, A1=>PRI_IN_4(14), S0=> nx2913); ix3016 : xnor2 port map ( Y=>nx3015, A0=>PRI_IN_4(15), A1=>nx3017); ix3018 : mux21 port map ( Y=>nx3017, A0=>reg_5_q_c_15, A1=>reg_2_q_c_15, S0=>C_MUX2_2_SEL); REG_2_reg_q_15 : dff port map ( Q=>reg_2_q_c_15, QB=>OPEN, D=>nx3480, CLK =>CLK); ix3481 : xnor2 port map ( Y=>nx3480, A0=>nx3360, A1=>nx3024); ix3361 : mux21 port map ( Y=>nx3360, A0=>nx2921, A1=>nx2987, S0=>nx2925); ix3025 : xnor2 port map ( Y=>nx3024, A0=>PRI_IN_2(15), A1=>reg_10_q_c_15 ); REG_10_reg_q_15 : dff port map ( Q=>reg_10_q_c_15, QB=>OPEN, D=>nx3470, CLK=>CLK); REG_3_reg_q_15 : dff port map ( Q=>PRI_OUT_0_15_EXMPLR, QB=>OPEN, D=> nx3460, CLK=>CLK); ix3461 : xnor2 port map ( Y=>nx3460, A0=>nx3376, A1=>nx3038); ix3377 : mux21 port map ( Y=>nx3376, A0=>nx2941, A1=>nx2987, S0=>nx2945); ix3039 : xnor2 port map ( Y=>nx3038, A0=>PRI_OUT_3_15_EXMPLR, A1=> reg_10_q_c_15); REG_4_reg_q_15 : dff port map ( Q=>PRI_OUT_3_15_EXMPLR, QB=>OPEN, D=> nx3450, CLK=>CLK); ix3451 : xnor2 port map ( Y=>nx3450, A0=>nx3386, A1=>nx3047); ix3048 : xnor2 port map ( Y=>nx3047, A0=>nx3402, A1=>nx3055); ix3403 : ao21 port map ( Y=>nx3402, A0=>nx1559, A1=>PRI_OUT_3_15_EXMPLR, B0=>nx3400); ix3401 : nor02 port map ( Y=>nx3400, A0=>nx1559, A1=>nx3053); ix3054 : mux21 port map ( Y=>nx3053, A0=>reg_2_q_c_15, A1=> PRI_OUT_0_15_EXMPLR, S0=>C_MUX2_1_SEL); ix3056 : mux21 port map ( Y=>nx3055, A0=>PRI_OUT_2_15_EXMPLR, A1=> PRI_OUT_1_15_EXMPLR, S0=>C_MUX2_4_SEL); REG_6_reg_q_15 : dff port map ( Q=>PRI_OUT_2_15_EXMPLR, QB=>OPEN, D=> nx3414, CLK=>CLK); ix3415 : xnor2 port map ( Y=>nx3414, A0=>nx3061, A1=>nx3412); ix3062 : aoi22 port map ( Y=>nx3061, A0=>nx3168, A1=>PRI_OUT_4_14_EXMPLR, B0=>nx3180, B1=>nx3182); ix3413 : xnor2 port map ( Y=>nx3412, A0=>PRI_OUT_4_15_EXMPLR, A1=>nx3053 ); REG_7_reg_q_15 : dff port map ( Q=>PRI_OUT_1_15_EXMPLR, QB=>OPEN, D=> nx3436, CLK=>CLK); ix3437 : xnor2 port map ( Y=>nx3436, A0=>nx3069, A1=>nx3434); ix3435 : xor2 port map ( Y=>nx3434, A0=>PRI_OUT_0_15_EXMPLR, A1=>nx3402); REG_9_reg_q_15 : dff port map ( Q=>reg_9_q_c_15, QB=>OPEN, D=>nx3542, CLK =>CLK); ix3543 : xnor2 port map ( Y=>nx3542, A0=>nx3510, A1=>nx3131); ix3132 : xnor2 port map ( Y=>nx3131, A0=>PRI_IN_3(15), A1=>nx3133); ix3134 : mux21 port map ( Y=>nx3133, A0=>nx3398, A1=>reg_1_q_c_15, S0=> C_MUX2_3_SEL); REG_1_reg_q_15 : dff port map ( Q=>reg_1_q_c_15, QB=>OPEN, D=>nx3528, CLK =>CLK); ix3529 : xnor2 port map ( Y=>nx3528, A0=>nx3143, A1=>nx3526); ix3144 : aoi22 port map ( Y=>nx3143, A0=>nx3145, A1=>PRI_OUT_2_14_EXMPLR, B0=>nx3294, B1=>nx3296); ix3146 : inv02 port map ( Y=>nx3145, A=>PRI_IN_0(14)); ix3527 : xnor2 port map ( Y=>nx3526, A0=>PRI_IN_0(15), A1=> PRI_OUT_2_15_EXMPLR); ix3399 : inv02 port map ( Y=>nx3398, A=>nx3053); ix3169 : inv02 port map ( Y=>nx3168, A=>nx2975); ix3019 : inv02 port map ( Y=>nx3018, A=>nx2808); ix2999 : inv02 port map ( Y=>nx2998, A=>nx2823); ix2939 : inv02 port map ( Y=>nx2938, A=>nx2855); ix2709 : inv02 port map ( Y=>nx2708, A=>nx2763); ix2559 : inv02 port map ( Y=>nx2558, A=>nx2597); ix2549 : inv02 port map ( Y=>nx2548, A=>nx2607); ix2539 : inv02 port map ( Y=>nx2538, A=>nx2613); ix2479 : inv02 port map ( Y=>nx2478, A=>nx2640); ix2249 : inv02 port map ( Y=>nx2248, A=>nx2549); ix2099 : inv02 port map ( Y=>nx2098, A=>nx2389); ix2079 : inv02 port map ( Y=>nx2078, A=>nx2403); ix2019 : inv02 port map ( Y=>nx2018, A=>nx2433); ix1789 : inv02 port map ( Y=>nx1788, A=>nx2334); ix1639 : inv02 port map ( Y=>nx1638, A=>nx2176); ix1619 : inv02 port map ( Y=>nx1618, A=>nx2191); ix1559 : inv02 port map ( Y=>nx1558, A=>nx2223); ix1333 : inv02 port map ( Y=>nx1332, A=>nx2105); ix1329 : inv02 port map ( Y=>nx1328, A=>nx2119); ix1179 : inv02 port map ( Y=>nx1178, A=>nx1959); ix1169 : inv02 port map ( Y=>nx1168, A=>nx1969); ix1159 : inv02 port map ( Y=>nx1158, A=>nx1975); ix1099 : inv02 port map ( Y=>nx1098, A=>nx2009); ix873 : inv02 port map ( Y=>nx872, A=>nx1891); ix869 : inv02 port map ( Y=>nx868, A=>nx1907); ix719 : inv02 port map ( Y=>nx718, A=>nx1749); ix699 : inv02 port map ( Y=>nx698, A=>nx1767); ix639 : inv02 port map ( Y=>nx638, A=>nx1797); ix627 : inv02 port map ( Y=>nx626, A=>nx1773); ix413 : inv02 port map ( Y=>nx412, A=>nx1675); ix409 : inv02 port map ( Y=>nx408, A=>nx1692); ix397 : inv02 port map ( Y=>nx396, A=>nx1662); ix279 : inv02 port map ( Y=>nx278, A=>nx1535); ix269 : inv02 port map ( Y=>nx268, A=>nx1543); ix259 : inv02 port map ( Y=>nx258, A=>nx1551); ix215 : inv02 port map ( Y=>nx214, A=>nx1581); ix185 : inv02 port map ( Y=>nx184, A=>nx1513); ix109 : xor2 port map ( Y=>nx108, A0=>PRI_IN_2(0), A1=>reg_10_q_c_0); ix81 : xor2 port map ( Y=>nx80, A0=>PRI_OUT_3_0_EXMPLR, A1=>reg_10_q_c_0 ); ix331 : xor2 port map ( Y=>nx330, A0=>nx1598, A1=>reg_9_q_c_1); ix1642 : xor2 port map ( Y=>nx1641, A0=>PRI_IN_2(2), A1=>nx1705); ix1659 : xor2 port map ( Y=>nx1658, A0=>PRI_OUT_3_2_EXMPLR, A1=>nx1705); ix791 : xor2 port map ( Y=>nx790, A0=>nx1813, A1=>reg_9_q_c_3); ix1864 : xor2 port map ( Y=>nx1863, A0=>PRI_IN_2(4), A1=>nx1921); ix1880 : xor2 port map ( Y=>nx1879, A0=>PRI_OUT_3_4_EXMPLR, A1=>nx1921); ix1251 : xor2 port map ( Y=>nx1250, A0=>nx2029, A1=>reg_9_q_c_5); ix2077 : xor2 port map ( Y=>nx2076, A0=>PRI_IN_2(6), A1=>nx2133); ix2094 : xor2 port map ( Y=>nx2093, A0=>PRI_OUT_3_6_EXMPLR, A1=>nx2133); ix1711 : xor2 port map ( Y=>nx1710, A0=>nx2242, A1=>reg_9_q_c_7); ix2291 : xor2 port map ( Y=>nx2290, A0=>PRI_IN_2(8), A1=>nx2347); ix2308 : xor2 port map ( Y=>nx2307, A0=>PRI_OUT_3_8_EXMPLR, A1=>nx2347); ix2171 : xor2 port map ( Y=>nx2170, A0=>nx2453, A1=>reg_9_q_c_9); ix2506 : xor2 port map ( Y=>nx2505, A0=>PRI_IN_2(10), A1=>nx2561); ix2524 : xor2 port map ( Y=>nx2523, A0=>PRI_OUT_3_10_EXMPLR, A1=>nx2561); ix2631 : xor2 port map ( Y=>nx2630, A0=>nx2661, A1=>reg_9_q_c_11); ix2716 : xor2 port map ( Y=>nx2715, A0=>PRI_IN_2(12), A1=>nx2774); ix2733 : xor2 port map ( Y=>nx2732, A0=>PRI_OUT_3_12_EXMPLR, A1=>nx2774); ix3091 : xor2 port map ( Y=>nx3090, A0=>nx2871, A1=>reg_9_q_c_13); ix2926 : xor2 port map ( Y=>nx2925, A0=>PRI_IN_2(14), A1=>nx2987); ix2946 : xor2 port map ( Y=>nx2945, A0=>PRI_OUT_3_14_EXMPLR, A1=>nx2987); REG_4_reg_q_3 : dff port map ( Q=>PRI_OUT_3_dup0_3, QB=>OPEN, D=>nx690, CLK=>CLK); ix691 : xnor2 port map ( Y=>nx690, A0=>nx1773, A1=>nx688); REG_4_reg_q_0 : dff port map ( Q=>PRI_OUT_3_dup0_0, QB=>OPEN, D=>nx66, CLK=>CLK); ix67 : xor2 port map ( Y=>nx66, A0=>nx1473, A1=>nx1479); ix3681 : buf04 port map ( Y=>PRI_OUT_3_3_EXMPLR, A=>PRI_OUT_3_dup0_3); ix3682 : buf04 port map ( Y=>PRI_OUT_3_0_EXMPLR, A=>PRI_OUT_3_dup0_0); ix3683 : inv02 port map ( Y=>nx3335, A=>nx2839); ix3684 : inv02 port map ( Y=>nx3336, A=>C_MUX2_4_SEL); ix3685 : aoi22 port map ( Y=>nx3337, A0=>PRI_OUT_2_13_EXMPLR, A1=>nx3359, B0=>PRI_OUT_1_13_EXMPLR, B1=>C_MUX2_4_SEL); ix3686 : nor02 port map ( Y=>nx3339, A0=>nx3335, A1=>nx3337); ix3687 : aoi221 port map ( Y=>nx3340, A0=>C_MUX2_4_SEL, A1=> PRI_OUT_1_11_EXMPLR, B0=>PRI_OUT_2_11_EXMPLR, B1=>nx3359, C0=>nx2626); ix3688 : inv02 port map ( Y=>nx3341, A=>nx2626); ix3689 : aoi22 port map ( Y=>nx3342, A0=>PRI_OUT_2_11_EXMPLR, A1=>nx3359, B0=>C_MUX2_4_SEL, B1=>PRI_OUT_1_11_EXMPLR); nx2737_EXMPLR : oai22 port map ( Y=>nx2737, A0=>nx3340, A1=>nx2466, B0=> nx3341, B1=>nx3342); ix3690 : inv02 port map ( Y=>nx3343, A=>nx3677); ix3691 : aoi22 port map ( Y=>nx3344, A0=>PRI_OUT_2_12_EXMPLR, A1=>nx3361, B0=>C_MUX2_4_SEL, B1=>PRI_OUT_1_12_EXMPLR); ix3692 : nand02 port map ( Y=>nx3345, A0=>nx3343, A1=>nx3344); ix3693 : nor02 port map ( Y=>nx3346, A0=>nx3343, A1=>nx3344); ix3694 : aoi21 port map ( Y=>nx3347, A0=>nx2737, A1=>nx3345, B0=>nx3346); ix3695 : aoi21 port map ( Y=>nx3349, A0=>nx3335, A1=>nx3337, B0=>nx3347); ix3696 : inv02 port map ( Y=>nx3350, A=>PRI_OUT_2_13_EXMPLR); ix3697 : inv02 port map ( Y=>nx3351, A=>PRI_OUT_1_13_EXMPLR); ix3698 : aoi22 port map ( Y=>nx3352, A0=>nx3361, A1=>nx3350, B0=> C_MUX2_4_SEL, B1=>nx3351); nx2988_EXMPLR : oai22 port map ( Y=>nx2988, A0=>nx3335, A1=>nx3352, B0=> nx3337, B1=>nx2839); nx2829_EXMPLR : inv01 port map ( Y=>nx2829, A=>nx3347); ix3699 : inv02 port map ( Y=>nx3353, A=>PRI_OUT_2_12_EXMPLR); ix3700 : inv02 port map ( Y=>nx3354, A=>PRI_OUT_1_12_EXMPLR); ix3701 : aoi22 port map ( Y=>nx3355, A0=>nx3361, A1=>nx3353, B0=> C_MUX2_4_SEL, B1=>nx3354); nx2758_EXMPLR : oai22 port map ( Y=>nx2758, A0=>nx3343, A1=>nx3355, B0=> nx3344, B1=>nx3677); ix3702 : inv02 port map ( Y=>nx3356, A=>PRI_OUT_2_11_EXMPLR); ix3703 : inv02 port map ( Y=>nx3357, A=>PRI_OUT_1_11_EXMPLR); ix3704 : aoi22 port map ( Y=>nx3358, A0=>nx3361, A1=>nx3356, B0=> C_MUX2_4_SEL, B1=>nx3357); nx2528_EXMPLR : oai22 port map ( Y=>nx2528, A0=>nx3341, A1=>nx3358, B0=> nx3342, B1=>nx2626); ix3705 : buf04 port map ( Y=>nx3359, A=>nx3336); ix3706 : buf04 port map ( Y=>nx3361, A=>nx3336); ix3707 : inv01 port map ( Y=>nx3362, A=>C_MUX2_5_SEL); ix3708 : inv01 port map ( Y=>nx3363, A=>PRI_OUT_1_0_EXMPLR); ix3709 : aoi22 port map ( Y=>nx3364, A0=>PRI_OUT_3_dup0_0, A1=>nx3362, B0 =>C_MUX2_4_SEL, B1=>nx3363); nx58_EXMPLR : oai221 port map ( Y=>nx58, A0=>nx3362, A1=>nx1485, B0=> C_MUX2_4_SEL, B1=>PRI_OUT_2_0_EXMPLR, C0=>nx3364); ix3710 : inv01 port map ( Y=>nx3365, A=>PRI_OUT_3_dup0_0); ix3711 : aoi22 port map ( Y=>nx3366, A0=>nx3365, A1=>nx3362, B0=> C_MUX2_5_SEL, B1=>nx1485); ix3712 : inv02 port map ( Y=>nx3367, A=>C_MUX2_4_SEL); ix3713 : aoi22 port map ( Y=>nx3368, A0=>PRI_OUT_2_0_EXMPLR, A1=>nx3367, B0=>PRI_OUT_1_0_EXMPLR, B1=>C_MUX2_4_SEL); nx1555_EXMPLR : nor02 port map ( Y=>nx1555, A0=>nx3366, A1=>nx3368); nx1479_EXMPLR : oai22 port map ( Y=>nx1479, A0=>C_MUX2_4_SEL, A1=> PRI_OUT_2_0_EXMPLR, B0=>nx3367, B1=>PRI_OUT_1_0_EXMPLR); nx18_EXMPLR : oai22 port map ( Y=>nx18, A0=>nx3365, A1=>C_MUX2_5_SEL, B0 =>nx3362, B1=>nx1485); nx1473_EXMPLR : oai22 port map ( Y=>nx1473, A0=>PRI_OUT_3_dup0_0, A1=> C_MUX2_5_SEL, B0=>nx3362, B1=>nx14); ix3714 : and02 port map ( Y=>nx3369, A0=>PRI_OUT_0_13_EXMPLR, A1=> PRI_IN_1(13)); ix3715 : and02 port map ( Y=>nx3370, A0=>PRI_OUT_0_12_EXMPLR, A1=> PRI_IN_1(12)); ix3716 : inv02 port map ( Y=>nx3371, A=>nx2815); nx2931_EXMPLR : oai32 port map ( Y=>nx2931, A0=>nx2906, A1=>nx3369, A2=> nx3370, B0=>nx3371, B1=>nx3369); ix3717 : inv02 port map ( Y=>nx3372, A=>PRI_IN_1(15)); ix3718 : inv02 port map ( Y=>nx3373, A=>PRI_OUT_0_15_EXMPLR); ix3719 : aoi22 port map ( Y=>nx3374, A0=>PRI_IN_1(15), A1=> PRI_OUT_0_15_EXMPLR, B0=>nx3372, B1=>nx3373); ix3720 : nor02 port map ( Y=>nx3375, A0=>PRI_OUT_0_14_EXMPLR, A1=> PRI_IN_1(14)); ix3721 : nand02 port map ( Y=>nx3377, A0=>PRI_OUT_0_13_EXMPLR, A1=> PRI_IN_1(13)); ix3722 : aoi221 port map ( Y=>nx3378, A0=>nx3679, A1=>PRI_IN_1(13), B0=> PRI_OUT_0_12_EXMPLR, B1=>PRI_IN_1(12), C0=>nx2906); ix3723 : aoi21 port map ( Y=>nx3379, A0=>nx2815, A1=>nx3377, B0=>nx3378); ix3724 : inv02 port map ( Y=>nx3380, A=>PRI_OUT_0_14_EXMPLR); ix3725 : inv02 port map ( Y=>nx3381, A=>PRI_IN_1(14)); ix3726 : oai21 port map ( Y=>nx3382, A0=>nx3380, A1=>nx3381, B0=>nx3374); nx3031_EXMPLR : oai22 port map ( Y=>nx3031, A0=>nx3372, A1=>nx3373, B0=> PRI_IN_1(15), B1=>PRI_OUT_0_15_EXMPLR); ix3727 : and02 port map ( Y=>nx3383, A0=>nx3680, A1=>PRI_IN_1(14)); ix3728 : aoi22 port map ( Y=>nx3384, A0=>nx3374, A1=>nx3375, B0=>nx3031, B1=>nx3383); nx3470_EXMPLR : oai321 port map ( Y=>nx3470, A0=>nx2931, A1=>nx3374, A2=> nx3375, B0=>nx3379, B1=>nx3382, C0=>nx3384); nx2935_EXMPLR : oai22 port map ( Y=>nx2935, A0=>nx3380, A1=>nx3381, B0=> nx3680, B1=>PRI_IN_1(14)); nx2908_EXMPLR : or02 port map ( Y=>nx2908, A0=>nx3370, A1=>nx2906); ix3729 : inv02 port map ( Y=>nx3385, A=>nx3675); ix3730 : inv02 port map ( Y=>nx3387, A=>C_MUX2_4_SEL); ix3731 : aoi22 port map ( Y=>nx3388, A0=>PRI_OUT_2_10_EXMPLR, A1=>nx3411, B0=>PRI_OUT_1_10_EXMPLR, B1=>C_MUX2_4_SEL); ix3732 : nor02 port map ( Y=>nx3389, A0=>nx3385, A1=>nx3388); ix3733 : aoi221 port map ( Y=>nx3390, A0=>C_MUX2_4_SEL, A1=> PRI_OUT_1_8_EXMPLR, B0=>PRI_OUT_2_8_EXMPLR, B1=>nx3411, C0=>nx3671); ix3734 : inv01 port map ( Y=>nx3391, A=>nx3671); ix3735 : aoi22 port map ( Y=>nx3392, A0=>PRI_OUT_2_8_EXMPLR, A1=>nx3411, B0=>C_MUX2_4_SEL, B1=>PRI_OUT_1_8_EXMPLR); nx2407_EXMPLR : oai22 port map ( Y=>nx2407, A0=>nx3390, A1=>nx1776, B0=> nx3391, B1=>nx3392); ix3736 : inv01 port map ( Y=>nx3393, A=>nx2415); ix3737 : aoi22 port map ( Y=>nx3394, A0=>PRI_OUT_2_9_EXMPLR, A1=>nx3413, B0=>C_MUX2_4_SEL, B1=>PRI_OUT_1_9_EXMPLR); ix3738 : nand02 port map ( Y=>nx3395, A0=>nx3393, A1=>nx3394); ix3739 : nor02 port map ( Y=>nx3396, A0=>nx3393, A1=>nx3394); ix3740 : aoi21 port map ( Y=>nx3397, A0=>nx2407, A1=>nx3395, B0=>nx3396); ix3741 : aoi21 port map ( Y=>nx3399, A0=>nx3385, A1=>nx3388, B0=>nx3397); nx2466_EXMPLR : nor02 port map ( Y=>nx2466, A0=>nx3389, A1=>nx3399); nx2617_EXMPLR : inv01 port map ( Y=>nx2617, A=>nx2466); ix3742 : inv02 port map ( Y=>nx3401, A=>PRI_OUT_2_10_EXMPLR); ix3743 : inv02 port map ( Y=>nx3403, A=>PRI_OUT_1_10_EXMPLR); ix3744 : aoi22 port map ( Y=>nx3404, A0=>nx3413, A1=>nx3401, B0=> C_MUX2_4_SEL, B1=>nx3403); nx2298_EXMPLR : oai22 port map ( Y=>nx2298, A0=>nx3385, A1=>nx3404, B0=> nx3388, B1=>nx3675); nx2529_EXMPLR : inv02 port map ( Y=>nx2529, A=>nx3397); ix3745 : inv02 port map ( Y=>nx3405, A=>PRI_OUT_2_9_EXMPLR); ix3746 : inv02 port map ( Y=>nx3406, A=>PRI_OUT_1_9_EXMPLR); ix3747 : aoi22 port map ( Y=>nx3407, A0=>nx3413, A1=>nx3405, B0=> C_MUX2_4_SEL, B1=>nx3406); nx2068_EXMPLR : oai22 port map ( Y=>nx2068, A0=>nx3393, A1=>nx3407, B0=> nx3394, B1=>nx2415); ix3748 : inv02 port map ( Y=>nx3408, A=>PRI_OUT_2_8_EXMPLR); ix3749 : inv02 port map ( Y=>nx3409, A=>PRI_OUT_1_8_EXMPLR); ix3750 : aoi22 port map ( Y=>nx3410, A0=>nx3413, A1=>nx3408, B0=> C_MUX2_4_SEL, B1=>nx3409); nx1838_EXMPLR : oai22 port map ( Y=>nx1838, A0=>nx3391, A1=>nx3410, B0=> nx3392, B1=>nx3671); ix3751 : buf04 port map ( Y=>nx3411, A=>nx3387); ix3752 : buf04 port map ( Y=>nx3413, A=>nx3387); nx1645_EXMPLR : aoi32 port map ( Y=>nx1645, A0=>nx268, A1=>PRI_IN_1(0), A2=>PRI_OUT_0_0_EXMPLR, B0=>PRI_OUT_0_1_EXMPLR, B1=>PRI_IN_1(1)); ix3753 : nor02 port map ( Y=>nx3415, A0=>nx3665, A1=>PRI_IN_1(2)); ix3754 : nor02 port map ( Y=>nx3416, A0=>nx1645, A1=>nx3415); ix3755 : inv02 port map ( Y=>nx3417, A=>PRI_IN_1(4)); ix3756 : inv01 port map ( Y=>nx3418, A=>nx3666); ix3757 : aoi22 port map ( Y=>nx3419, A0=>nx3666, A1=>nx3417, B0=> PRI_IN_1(4), B1=>nx3418); ix3758 : inv02 port map ( Y=>nx3420, A=>PRI_OUT_0_3_EXMPLR); ix3759 : inv02 port map ( Y=>nx3421, A=>PRI_IN_1(3)); ix3760 : and02 port map ( Y=>nx3422, A0=>PRI_OUT_0_3_EXMPLR, A1=> PRI_IN_1(3)); ix3761 : inv02 port map ( Y=>nx3423, A=>nx3665); ix3762 : inv02 port map ( Y=>nx3424, A=>PRI_IN_1(2)); nx608_EXMPLR : oai22 port map ( Y=>nx608, A0=>nx3423, A1=>nx3424, B0=> nx1645, B1=>nx3415); ix3763 : inv02 port map ( Y=>nx3425, A=>nx1759); nx1867_EXMPLR : oai22 port map ( Y=>nx1867, A0=>nx3422, A1=>nx608, B0=> nx3425, B1=>nx3422); nx1871_EXMPLR : oai22 port map ( Y=>nx1871, A0=>nx3417, A1=>nx3418, B0=> PRI_IN_1(4), B1=>nx3666); nx1649_EXMPLR : oai22 port map ( Y=>nx1649, A0=>nx3423, A1=>nx3424, B0=> nx3665, B1=>PRI_IN_1(2)); ix3764 : inv01 port map ( Y=>nx3426, A=>nx1991); ix3765 : inv01 port map ( Y=>nx3427, A=>C_MUX2_4_SEL); ix3766 : aoi22 port map ( Y=>nx3428, A0=>PRI_OUT_2_5_EXMPLR, A1=>nx3451, B0=>PRI_OUT_1_5_EXMPLR, B1=>C_MUX2_4_SEL); ix3767 : nor02 port map ( Y=>nx3429, A0=>nx3426, A1=>nx3428); ix3768 : aoi221 port map ( Y=>nx3430, A0=>C_MUX2_4_SEL, A1=> PRI_OUT_1_3_EXMPLR, B0=>PRI_OUT_2_3_EXMPLR, B1=>nx3451, C0=>nx1781); ix3769 : inv01 port map ( Y=>nx3431, A=>nx1781); ix3770 : aoi22 port map ( Y=>nx3432, A0=>PRI_OUT_2_3_EXMPLR, A1=>nx3451, B0=>C_MUX2_4_SEL, B1=>PRI_OUT_1_3_EXMPLR); nx1885_EXMPLR : oai22 port map ( Y=>nx1885, A0=>nx3430, A1=>nx626, B0=> nx3431, B1=>nx3432); ix3771 : inv01 port map ( Y=>nx3433, A=>nx1891); ix3772 : aoi22 port map ( Y=>nx3435, A0=>PRI_OUT_2_4_EXMPLR, A1=>nx3452, B0=>C_MUX2_4_SEL, B1=>PRI_OUT_1_4_EXMPLR); ix3773 : nand02 port map ( Y=>nx3437, A0=>nx3433, A1=>nx3435); ix3774 : nor02 port map ( Y=>nx3438, A0=>nx3433, A1=>nx3435); ix3775 : aoi21 port map ( Y=>nx3439, A0=>nx1885, A1=>nx3437, B0=>nx3438); ix3776 : aoi21 port map ( Y=>nx3440, A0=>nx3426, A1=>nx3428, B0=>nx3439); nx2097_EXMPLR : inv02 port map ( Y=>nx2097, A=>nx1316); ix3777 : inv02 port map ( Y=>nx3441, A=>PRI_OUT_2_5_EXMPLR); ix3778 : inv02 port map ( Y=>nx3442, A=>PRI_OUT_1_5_EXMPLR); ix3779 : aoi22 port map ( Y=>nx3443, A0=>nx3452, A1=>nx3441, B0=> C_MUX2_4_SEL, B1=>nx3442); nx1148_EXMPLR : oai22 port map ( Y=>nx1148, A0=>nx3426, A1=>nx3443, B0=> nx3428, B1=>nx1991); nx1981_EXMPLR : inv02 port map ( Y=>nx1981, A=>nx3439); ix3780 : inv02 port map ( Y=>nx3444, A=>PRI_OUT_2_4_EXMPLR); ix3781 : inv02 port map ( Y=>nx3445, A=>PRI_OUT_1_4_EXMPLR); ix3782 : aoi22 port map ( Y=>nx3446, A0=>nx3452, A1=>nx3444, B0=> C_MUX2_4_SEL, B1=>nx3445); nx918_EXMPLR : oai22 port map ( Y=>nx918, A0=>nx3433, A1=>nx3446, B0=> nx3435, B1=>nx1891); ix3783 : inv02 port map ( Y=>nx3447, A=>PRI_OUT_2_3_EXMPLR); ix3784 : inv02 port map ( Y=>nx3448, A=>PRI_OUT_1_3_EXMPLR); ix3785 : aoi22 port map ( Y=>nx3449, A0=>nx3452, A1=>nx3447, B0=> C_MUX2_4_SEL, B1=>nx3448); nx688_EXMPLR : oai22 port map ( Y=>nx688, A0=>nx3431, A1=>nx3449, B0=> nx3432, B1=>nx1781); ix3786 : buf04 port map ( Y=>nx3451, A=>nx3427); ix3787 : buf04 port map ( Y=>nx3452, A=>nx3427); ix3788 : inv01 port map ( Y=>nx3453, A=>nx3659); ix3789 : inv01 port map ( Y=>nx3454, A=>nx3661); ix3790 : aoi22 port map ( Y=>nx3455, A0=>nx3594, A1=>nx3453, B0=> C_MUX2_1_SEL, B1=>nx3454); ix3791 : inv02 port map ( Y=>nx3456, A=>PRI_IN_3(0)); ix3792 : inv02 port map ( Y=>nx3457, A=>C_MUX2_3_SEL); nx1601_EXMPLR : oai33 port map ( Y=>nx1601, A0=>nx3455, A1=>nx3456, A2=> C_MUX2_3_SEL, B0=>reg_1_q_c_0, B1=>nx3457, B2=>nx3456); ix3793 : inv02 port map ( Y=>nx3458, A=>reg_1_q_c_0); ix3794 : aoi22 port map ( Y=>nx3459, A0=>nx3659, A1=>nx3594, B0=>nx3661, B1=>C_MUX2_1_SEL); nx162_EXMPLR : oai22 port map ( Y=>nx162, A0=>nx3457, A1=>nx3458, B0=> nx3459, B1=>C_MUX2_3_SEL); ix3795 : inv01 port map ( Y=>nx3461, A=>C_MUX2_4_SEL); ix3796 : inv01 port map ( Y=>nx3462, A=>PRI_OUT_2_7_EXMPLR); ix3797 : inv01 port map ( Y=>nx3463, A=>PRI_OUT_1_7_EXMPLR); ix3798 : aoi22 port map ( Y=>nx3464, A0=>nx3461, A1=>nx3462, B0=> C_MUX2_4_SEL, B1=>nx3463); ix3799 : and02 port map ( Y=>nx3465, A0=>nx2205, A1=>nx3464); ix3800 : inv01 port map ( Y=>nx3466, A=>nx2105); ix3801 : aoi22 port map ( Y=>nx3467, A0=>PRI_OUT_2_6_EXMPLR, A1=>nx3461, B0=>C_MUX2_4_SEL, B1=>PRI_OUT_1_6_EXMPLR); ix3802 : nor02 port map ( Y=>nx3468, A0=>nx3654, A1=>nx3563); ix3803 : aoi221 port map ( Y=>nx3469, A0=>PRI_OUT_1_7_EXMPLR, A1=> C_MUX2_4_SEL, B0=>PRI_OUT_2_7_EXMPLR, B1=>nx3461, C0=>nx2205); ix3804 : inv02 port map ( Y=>nx3471, A=>nx2205); ix3805 : aoi22 port map ( Y=>nx3472, A0=>PRI_OUT_2_7_EXMPLR, A1=>nx3461, B0=>PRI_OUT_1_7_EXMPLR, B1=>C_MUX2_4_SEL); nx2313_EXMPLR : oai22 port map ( Y=>nx2313, A0=>nx3468, A1=>nx3469, B0=> nx3471, B1=>nx3472); nx1608_EXMPLR : oai22 port map ( Y=>nx1608, A0=>nx3471, A1=>nx3464, B0=> nx3472, B1=>nx2205); nx2197_EXMPLR : inv01 port map ( Y=>nx2197, A=>nx3468); ix3806 : inv02 port map ( Y=>nx3473, A=>PRI_OUT_2_6_EXMPLR); ix3807 : inv02 port map ( Y=>nx3474, A=>PRI_OUT_1_6_EXMPLR); ix3808 : aoi22 port map ( Y=>nx3475, A0=>nx3461, A1=>nx3473, B0=> C_MUX2_4_SEL, B1=>nx3474); nx1378_EXMPLR : oai22 port map ( Y=>nx1378, A0=>nx3466, A1=>nx3475, B0=> nx3467, B1=>nx2105); ix3809 : or02 port map ( Y=>nx3476, A0=>PRI_OUT_0_10_EXMPLR, A1=> PRI_IN_1(10)); ix3810 : inv02 port map ( Y=>nx3477, A=>PRI_OUT_0_8_EXMPLR); ix3811 : inv02 port map ( Y=>nx3478, A=>PRI_IN_1(8)); ix3812 : nor02 port map ( Y=>nx3479, A0=>PRI_OUT_0_8_EXMPLR, A1=> PRI_IN_1(8)); ix3813 : inv02 port map ( Y=>nx3481, A=>nx2397); nx2448_EXMPLR : inv02 port map ( Y=>nx2448, A=>nx3645); ix3814 : and02 port map ( Y=>nx3482, A0=>PRI_OUT_0_9_EXMPLR, A1=> PRI_IN_1(9)); nx2511_EXMPLR : oai22 port map ( Y=>nx2511, A0=>nx3482, A1=>nx3646, B0=> nx3481, B1=>nx3482); ix3815 : inv02 port map ( Y=>nx3483, A=>PRI_OUT_0_10_EXMPLR); ix3816 : inv02 port map ( Y=>nx3484, A=>PRI_IN_1(10)); nx2515_EXMPLR : oai22 port map ( Y=>nx2515, A0=>nx3483, A1=>nx3484, B0=> PRI_OUT_0_10_EXMPLR, B1=>PRI_IN_1(10)); nx2299_EXMPLR : oai22 port map ( Y=>nx2299, A0=>nx3477, A1=>nx3478, B0=> nx3670, B1=>PRI_IN_1(8)); ix3817 : nor02 port map ( Y=>nx3485, A0=>nx3419, A1=>nx1759); ix3818 : inv02 port map ( Y=>nx3486, A=>nx3665); ix3819 : inv02 port map ( Y=>nx3487, A=>PRI_IN_1(2)); ix3820 : oai43 port map ( Y=>nx3488, A0=>nx3486, A1=>nx3487, A2=>nx3419, A3=>nx1759, B0=>nx3420, B1=>nx3419, B2=>nx3421); nx1066_EXMPLR : ao21 port map ( Y=>nx1066, A0=>nx3416, A1=>nx3485, B0=> nx3488); ix3821 : inv02 port map ( Y=>nx3489, A=>nx3680); ix3822 : or02 port map ( Y=>nx3490, A0=>nx3489, A1=>nx2959); ix3823 : inv02 port map ( Y=>nx3491, A=>nx3679); ix3824 : inv02 port map ( Y=>nx3492, A=>C_MUX2_5_SEL); ix3825 : and02 port map ( Y=>nx3493, A0=>PRI_OUT_3_13_EXMPLR, A1=>nx3520 ); ix3826 : nor02 port map ( Y=>nx3495, A0=>C_MUX2_5_SEL, A1=> PRI_OUT_3_13_EXMPLR); ix3827 : inv02 port map ( Y=>nx3496, A=>nx2938); ix3828 : oai33 port map ( Y=>nx3497, A0=>nx2938, A1=>nx3520, A2=>nx3491, B0=>nx3496, B1=>nx3520, B2=>nx3679); ix3829 : aoi221 port map ( Y=>nx3498, A0=>nx3491, A1=>nx3493, B0=>nx3679, B1=>nx3495, C0=>nx3497); ix3830 : inv02 port map ( Y=>nx3499, A=>PRI_OUT_0_12_EXMPLR); ix3831 : inv02 port map ( Y=>nx3500, A=>nx3674); ix3832 : inv02 port map ( Y=>nx3501, A=>PRI_OUT_0_11_EXMPLR); ix3833 : and02 port map ( Y=>nx3502, A0=>PRI_OUT_3_11_EXMPLR, A1=>nx3520 ); ix3834 : nor02 port map ( Y=>nx3503, A0=>C_MUX2_5_SEL, A1=> PRI_OUT_3_11_EXMPLR); ix3835 : inv02 port map ( Y=>nx3504, A=>nx2478); ix3836 : oai33 port map ( Y=>nx3505, A0=>nx2478, A1=>nx3521, A2=>nx3501, B0=>nx3504, B1=>nx3520, B2=>PRI_OUT_0_11_EXMPLR); ix3837 : aoi221 port map ( Y=>nx3506, A0=>nx3501, A1=>nx3502, B0=> PRI_OUT_0_11_EXMPLR, B1=>nx3503, C0=>nx3505); ix3838 : aoi21 port map ( Y=>nx3507, A0=>nx3675, A1=>nx3500, B0=>nx3506); ix3839 : ao22 port map ( Y=>nx3508, A0=>PRI_OUT_3_11_EXMPLR, A1=>nx3521, B0=>C_MUX2_5_SEL, B1=>nx2478); ix3840 : nor03 port map ( Y=>nx3509, A0=>nx3506, A1=>nx3500, A2=>nx3676); ix3841 : ao21 port map ( Y=>nx3511, A0=>nx3677, A1=>nx3499, B0=>nx3498); ix3842 : ao22 port map ( Y=>nx3512, A0=>PRI_OUT_3_13_EXMPLR, A1=>nx3521, B0=>nx2938, B1=>C_MUX2_5_SEL); ix3843 : nand02 port map ( Y=>nx3513, A0=>nx3512, A1=>nx3498); ix3844 : inv02 port map ( Y=>nx3514, A=>nx2959); nx3204_EXMPLR : oai22 port map ( Y=>nx3204, A0=>nx3489, A1=>nx3514, B0=> nx3680, B1=>nx2959); nx2839_EXMPLR : oai22 port map ( Y=>nx2839, A0=>C_MUX2_5_SEL, A1=> PRI_OUT_3_13_EXMPLR, B0=>nx3521, B1=>nx2938); ix3845 : or02 port map ( Y=>nx3515, A0=>nx3499, A1=>nx3677); ix3846 : and02 port map ( Y=>nx3516, A0=>nx3678, A1=>nx3499); nx2861_EXMPLR : ao21 port map ( Y=>nx2861, A0=>nx3515, A1=>nx3548, B0=> nx3516); nx2974_EXMPLR : inv02 port map ( Y=>nx2974, A=>nx3498); ix3847 : inv02 port map ( Y=>nx3517, A=>nx3678); nx2744_EXMPLR : oai22 port map ( Y=>nx2744, A0=>nx3499, A1=>nx3517, B0=> PRI_OUT_0_12_EXMPLR, B1=>nx3678); nx2626_EXMPLR : oai22 port map ( Y=>nx2626, A0=>C_MUX2_5_SEL, A1=> PRI_OUT_3_11_EXMPLR, B0=>nx3521, B1=>nx2478); ix3848 : nor02 port map ( Y=>nx3518, A0=>nx3500, A1=>nx3676); ix3849 : inv02 port map ( Y=>nx3519, A=>nx3676); nx2647_EXMPLR : oai22 port map ( Y=>nx2647, A0=>nx3518, A1=>nx3550, B0=> nx3519, B1=>nx3674); nx2514_EXMPLR : inv02 port map ( Y=>nx2514, A=>nx3506); nx2284_EXMPLR : oai22 port map ( Y=>nx2284, A0=>nx3500, A1=>nx3519, B0=> nx3674, B1=>nx3676); ix3850 : buf04 port map ( Y=>nx3520, A=>nx3492); ix3851 : buf04 port map ( Y=>nx3521, A=>nx3492); ix3852 : inv02 port map ( Y=>nx3522, A=>nx3310); ix3853 : inv02 port map ( Y=>nx3523, A=>PRI_IN_3(14)); ix3854 : inv01 port map ( Y=>nx3524, A=>C_MUX2_5_SEL); ix3855 : aoi221 port map ( Y=>nx3525, A0=>C_MUX2_5_SEL, A1=>nx1558, B0=> PRI_OUT_3_7_EXMPLR, B1=>nx3560, C0=>PRI_OUT_0_7_EXMPLR); ix3856 : inv02 port map ( Y=>nx3527, A=>nx3668); ix3857 : aoi22 port map ( Y=>nx3529, A0=>nx3669, A1=>nx3560, B0=> C_MUX2_5_SEL, B1=>nx1558); nx1822_EXMPLR : oai22 port map ( Y=>nx1822, A0=>nx3525, A1=>nx2229, B0=> nx3527, B1=>nx3529); ix3858 : inv01 port map ( Y=>nx3530, A=>nx1822); ix3859 : inv02 port map ( Y=>nx3531, A=>nx3670); ix3860 : inv02 port map ( Y=>nx3532, A=>PRI_OUT_0_9_EXMPLR); ix3861 : and02 port map ( Y=>nx3533, A0=>PRI_OUT_3_9_EXMPLR, A1=>nx3560); ix3862 : nor02 port map ( Y=>nx3534, A0=>C_MUX2_5_SEL, A1=> PRI_OUT_3_9_EXMPLR); ix3863 : inv01 port map ( Y=>nx3535, A=>nx2018); ix3864 : oai33 port map ( Y=>nx3536, A0=>nx2018, A1=>nx3560, A2=>nx3532, B0=>nx3535, B1=>nx3560, B2=>nx3673); ix3865 : aoi221 port map ( Y=>nx3537, A0=>nx3532, A1=>nx3533, B0=>nx3673, B1=>nx3534, C0=>nx3536); ix3866 : ao21 port map ( Y=>nx3538, A0=>nx3671, A1=>nx3531, B0=>nx3537); ix3867 : ao22 port map ( Y=>nx3539, A0=>PRI_OUT_3_9_EXMPLR, A1=>nx3561, B0=>nx2018, B1=>C_MUX2_5_SEL); ix3868 : nor03 port map ( Y=>nx3540, A0=>nx3537, A1=>nx3531, A2=>nx3672); ix3869 : aoi21 port map ( Y=>nx3541, A0=>nx3539, A1=>nx3537, B0=>nx3540); nx2282_EXMPLR : oai21 port map ( Y=>nx2282, A0=>nx3530, A1=>nx3538, B0=> nx3541); ix3870 : inv01 port map ( Y=>nx3543, A=>nx2282); ix3871 : inv02 port map ( Y=>nx3544, A=>nx3507); ix3872 : aoi21 port map ( Y=>nx3545, A0=>nx3508, A1=>nx3506, B0=>nx3509); ix3873 : or03 port map ( Y=>nx3546, A0=>nx3498, A1=>nx3499, A2=>nx3678); ix3874 : and02 port map ( Y=>nx3547, A0=>nx3513, A1=>nx3546); nx3202_EXMPLR : oai321 port map ( Y=>nx3202, A0=>nx3543, A1=>nx3544, A2=> nx3511, B0=>nx3545, B1=>nx3511, C0=>nx3547); nx2742_EXMPLR : aoi22 port map ( Y=>nx2742, A0=>nx3545, A1=>nx3543, B0=> nx3545, B1=>nx3544); ix3875 : inv01 port map ( Y=>nx3548, A=>nx2742); ix3876 : inv01 port map ( Y=>nx3549, A=>nx3543); ix3877 : inv01 port map ( Y=>nx3550, A=>nx3543); nx2415_EXMPLR : oai22 port map ( Y=>nx2415, A0=>C_MUX2_5_SEL, A1=> PRI_OUT_3_9_EXMPLR, B0=>nx3561, B1=>nx2018); ix3878 : nor02 port map ( Y=>nx3551, A0=>nx3531, A1=>nx3672); ix3879 : inv02 port map ( Y=>nx3553, A=>nx3530); ix3880 : inv02 port map ( Y=>nx3554, A=>nx3672); nx2439_EXMPLR : oai22 port map ( Y=>nx2439, A0=>nx3551, A1=>nx3553, B0=> nx3554, B1=>nx3670); nx2054_EXMPLR : inv02 port map ( Y=>nx2054, A=>nx3537); ix3881 : inv02 port map ( Y=>nx3555, A=>nx3530); nx1824_EXMPLR : oai22 port map ( Y=>nx1824, A0=>nx3531, A1=>nx3554, B0=> nx3670, B1=>nx3672); nx2205_EXMPLR : oai22 port map ( Y=>nx2205, A0=>C_MUX2_5_SEL, A1=>nx3669, B0=>nx3561, B1=>nx1558); ix3882 : inv02 port map ( Y=>nx3556, A=>nx1558); ix3883 : aoi33 port map ( Y=>nx3557, A0=>nx3556, A1=>C_MUX2_5_SEL, A2=> nx3668, B0=>nx1558, B1=>C_MUX2_5_SEL, B2=>nx3527); ix3884 : inv02 port map ( Y=>nx3558, A=>nx3669); ix3885 : aoi33 port map ( Y=>nx3559, A0=>nx3668, A1=>nx3561, A2=>nx3558, B0=>nx3527, B1=>nx3669, B2=>nx3561); nx1594_EXMPLR : nand02 port map ( Y=>nx1594, A0=>nx3557, A1=>nx3559); ix3886 : buf04 port map ( Y=>nx3560, A=>nx3524); ix3887 : buf04 port map ( Y=>nx3561, A=>nx3524); ix3888 : and02 port map ( Y=>nx3562, A0=>nx3466, A1=>nx3467); ix3889 : nor02 port map ( Y=>nx3563, A0=>nx3562, A1=>nx1316); ix3890 : nand02 port map ( Y=>nx3564, A0=>nx3310, A1=>nx3080); ix3891 : nor02 port map ( Y=>nx3565, A0=>nx3080, A1=>PRI_IN_3(13)); ix3892 : aoi22 port map ( Y=>nx3566, A0=>nx3522, A1=>nx3523, B0=>nx3310, B1=>nx3565); nx3510_EXMPLR : oai21 port map ( Y=>nx3510, A0=>nx2875, A1=>nx3564, B0=> nx3566); ix3893 : inv02 port map ( Y=>nx3567, A=>nx3080); ix3894 : and02 port map ( Y=>nx3568, A0=>nx3668, A1=>PRI_IN_1(7)); ix3895 : and02 port map ( Y=>nx3569, A0=>PRI_OUT_0_6_EXMPLR, A1=> PRI_IN_1(6)); ix3896 : inv02 port map ( Y=>nx3570, A=>nx2183); nx1528_EXMPLR : or02 port map ( Y=>nx1528, A0=>nx3569, A1=>nx1526); ix3897 : or02 port map ( Y=>nx3571, A0=>nx3310, A1=>nx3567); ix3898 : inv02 port map ( Y=>nx3572, A=>nx3080); ix3899 : inv02 port map ( Y=>nx3573, A=>PRI_IN_3(13)); ix3900 : inv02 port map ( Y=>nx3574, A=>nx3310); ix3901 : aoi21 port map ( Y=>nx3575, A0=>nx3572, A1=>nx3573, B0=>nx3574); ix3902 : nor02 port map ( Y=>nx3576, A0=>nx3080, A1=>PRI_IN_3(13)); ix3903 : aoi222 port map ( Y=>nx3577, A0=>nx3567, A1=>nx3575, B0=>nx3574, B1=>nx3576, C0=>nx2875, C1=>nx3575); nx3312_EXMPLR : oai21 port map ( Y=>nx3312, A0=>nx2875, A1=>nx3571, B0=> nx3577); ix3904 : inv02 port map ( Y=>nx3578, A=>nx3218); ix3905 : inv02 port map ( Y=>nx3579, A=>nx2965); nx3386_EXMPLR : oai32 port map ( Y=>nx3386, A0=>nx3349, A1=>nx3578, A2=> nx3339, B0=>nx3579, B1=>nx3218); ix3906 : ao21 port map ( Y=>nx3580, A0=>PRI_OUT_4_0_EXMPLR, A1=>nx3661, B0=>PRI_OUT_4_1_EXMPLR); ix3907 : inv01 port map ( Y=>nx3581, A=>nx3659); ix3908 : inv01 port map ( Y=>nx3582, A=>C_MUX2_1_SEL); ix3909 : inv01 port map ( Y=>nx3583, A=>nx3661); nx14_EXMPLR : oai22 port map ( Y=>nx14, A0=>nx3581, A1=>C_MUX2_1_SEL, B0 =>nx3593, B1=>nx3583); ix3910 : ao21 port map ( Y=>nx3584, A0=>PRI_OUT_4_0_EXMPLR, A1=>nx3659, B0=>PRI_OUT_4_1_EXMPLR); ix3911 : and02 port map ( Y=>nx3585, A0=>nx3662, A1=>nx3593); ix3912 : aoi332 port map ( Y=>nx3586, A0=>nx3580, A1=>nx3664, A2=> C_MUX2_1_SEL, B0=>nx14, B1=>PRI_OUT_4_0_EXMPLR, B2=>PRI_OUT_4_1_EXMPLR, C0=>nx3584, C1=>nx3585); nx420_EXMPLR : inv02 port map ( Y=>nx420, A=>nx3586); ix3913 : inv01 port map ( Y=>nx3587, A=>nx3586); nx1581_EXMPLR : oai22 port map ( Y=>nx1581, A0=>C_MUX2_1_SEL, A1=>nx3662, B0=>nx3593, B1=>nx3664); nx1578_EXMPLR : oai221 port map ( Y=>nx1578, A0=>C_MUX2_1_SEL, A1=>nx3659, B0=>nx3594, B1=>nx3661, C0=>PRI_OUT_4_0_EXMPLR); ix3914 : inv02 port map ( Y=>nx3588, A=>PRI_OUT_4_1_EXMPLR); ix3915 : inv02 port map ( Y=>nx3589, A=>nx3662); ix3916 : inv02 port map ( Y=>nx3590, A=>nx3664); ix3917 : aoi22 port map ( Y=>nx3591, A0=>nx3594, A1=>nx3589, B0=> C_MUX2_1_SEL, B1=>nx3590); ix3918 : aoi22 port map ( Y=>nx3592, A0=>nx3662, A1=>nx3594, B0=>nx3664, B1=>C_MUX2_1_SEL); nx220_EXMPLR : oai22 port map ( Y=>nx220, A0=>nx3588, A1=>nx3591, B0=> nx3592, B1=>PRI_OUT_4_1_EXMPLR); nx1485_EXMPLR : oai22 port map ( Y=>nx1485, A0=>C_MUX2_1_SEL, A1=>nx3660, B0=>nx3594, B1=>nx3661); ix3919 : buf04 port map ( Y=>nx3593, A=>nx3582); ix3920 : buf04 port map ( Y=>nx3594, A=>nx3582); ix3921 : inv02 port map ( Y=>nx3595, A=>nx3490); ix3922 : inv02 port map ( Y=>nx3596, A=>nx2959); ix3923 : inv02 port map ( Y=>nx3597, A=>nx3489); nx3069_EXMPLR : oai22 port map ( Y=>nx3069, A0=>nx3595, A1=>nx3202, B0=> nx3596, B1=>nx3597); nx2951_EXMPLR : or02 port map ( Y=>nx2951, A0=>nx3349, A1=>nx3339); ix3924 : inv01 port map ( Y=>nx3598, A=>nx3663); ix3925 : aoi22 port map ( Y=>nx3599, A0=>PRI_IN_4(1), A1=>C_MUX2_2_SEL, B0=>C_MUX2_2_SEL, B1=>nx3598); ix3926 : inv02 port map ( Y=>nx3600, A=>PRI_IN_4(0)); ix3927 : inv02 port map ( Y=>nx3601, A=>C_MUX2_2_SEL); ix3928 : inv01 port map ( Y=>nx3602, A=>reg_5_q_c_1); ix3929 : aoi22 port map ( Y=>nx3603, A0=>PRI_IN_4(1), A1=>nx3614, B0=> nx3602, B1=>nx3614); ix3930 : or02 port map ( Y=>nx3604, A0=>nx3600, A1=>reg_5_q_c_0); ix3931 : aoi33 port map ( Y=>nx3605, A0=>nx3598, A1=>PRI_IN_4(1), A2=> C_MUX2_2_SEL, B0=>nx3602, B1=>PRI_IN_4(1), B2=>nx3614); nx1735_EXMPLR : oai321 port map ( Y=>nx1735, A0=>nx3599, A1=>nx3600, A2=> nx3660, B0=>nx3603, B1=>nx3604, C0=>nx3605); ix3932 : aoi221 port map ( Y=>nx3606, A0=>reg_5_q_c_0, A1=>nx3614, B0=> C_MUX2_2_SEL, B1=>nx3660, C0=>nx3600); ix3933 : inv02 port map ( Y=>nx3607, A=>PRI_IN_4(1)); ix3934 : aoi221 port map ( Y=>nx3608, A0=>reg_5_q_c_1, A1=>nx3615, B0=> nx3663, B1=>C_MUX2_2_SEL, C0=>nx3607); ix3935 : aoi22 port map ( Y=>nx3609, A0=>reg_5_q_c_1, A1=>nx3615, B0=> nx3663, B1=>C_MUX2_2_SEL); nx358_EXMPLR : oai22 port map ( Y=>nx358, A0=>nx3606, A1=>nx3608, B0=> nx3609, B1=>PRI_IN_4(1)); ix3936 : aoi22 port map ( Y=>nx3610, A0=>nx3663, A1=>nx3607, B0=> PRI_IN_4(1), B1=>nx3598); ix3937 : aoi22 port map ( Y=>nx3611, A0=>reg_5_q_c_1, A1=>nx3607, B0=> PRI_IN_4(1), B1=>nx3602); nx1525_EXMPLR : oai22 port map ( Y=>nx1525, A0=>nx3615, A1=>nx3610, B0=> nx3611, B1=>C_MUX2_2_SEL); ix3938 : inv02 port map ( Y=>nx3612, A=>reg_5_q_c_0); ix3939 : inv02 port map ( Y=>nx3613, A=>nx3660); nx122_EXMPLR : oai221 port map ( Y=>nx122, A0=>nx3612, A1=>C_MUX2_2_SEL, B0=>nx3615, B1=>nx3613, C0=>PRI_IN_4(0)); nx1457_EXMPLR : oai22 port map ( Y=>nx1457, A0=>reg_5_q_c_0, A1=> C_MUX2_2_SEL, B0=>nx3615, B1=>nx3660); ix3940 : buf04 port map ( Y=>nx3614, A=>nx3601); ix3941 : buf04 port map ( Y=>nx3615, A=>nx3601); ix3942 : inv01 port map ( Y=>nx3616, A=>nx3429); ix3943 : nand02 port map ( Y=>nx3617, A0=>nx3658, A1=>nx3616); ix3944 : inv01 port map ( Y=>nx3618, A=>nx3657); nx1776_EXMPLR : oai21 port map ( Y=>nx1776, A0=>nx3440, A1=>nx3617, B0=> nx3618); nx1316_EXMPLR : nor02 port map ( Y=>nx1316, A0=>nx3440, A1=>nx3429); ix3945 : inv01 port map ( Y=>nx3619, A=>nx2081); ix3946 : inv02 port map ( Y=>nx3620, A=>PRI_IN_1(6)); ix3947 : inv02 port map ( Y=>nx3621, A=>nx3667); ix3948 : aoi22 port map ( Y=>nx3622, A0=>nx3667, A1=>nx3620, B0=> PRI_IN_1(6), B1=>nx3621); ix3949 : inv02 port map ( Y=>nx3623, A=>nx3570); ix3950 : nor03 port map ( Y=>nx3624, A0=>nx3622, A1=>nx3623, A2=>nx3479); ix3951 : aoi21 port map ( Y=>nx3625, A0=>nx3569, A1=>nx3570, B0=>nx3568); ix3952 : oai22 port map ( Y=>nx3626, A0=>nx3477, A1=>nx3478, B0=>nx3625, B1=>nx3479); ix3953 : aoi21 port map ( Y=>nx3627, A0=>nx3619, A1=>nx3624, B0=>nx3626); ix3954 : inv02 port map ( Y=>nx3628, A=>nx3476); ix3955 : inv02 port map ( Y=>nx3629, A=>nx3481); ix3956 : inv02 port map ( Y=>nx3630, A=>nx3673); ix3957 : inv02 port map ( Y=>nx3631, A=>PRI_IN_1(9)); ix3958 : inv02 port map ( Y=>nx3632, A=>nx3674); ix3959 : inv02 port map ( Y=>nx3633, A=>PRI_IN_1(10)); ix3960 : oai332 port map ( Y=>nx3634, A0=>nx3650, A1=>nx3628, A2=>nx3629, B0=>nx3628, B1=>nx3630, B2=>nx3631, C0=>nx3632, C1=>nx3633); ix3961 : nor02 port map ( Y=>nx3635, A0=>PRI_IN_1(10), A1=>nx3673); ix3962 : aoi32 port map ( Y=>nx3636, A0=>nx3650, A1=>nx3632, A2=>nx3631, B0=>nx3650, B1=>nx3635); ix3963 : nor02 port map ( Y=>nx3637, A0=>PRI_IN_1(10), A1=>PRI_IN_1(9)); ix3964 : nor02 port map ( Y=>nx3638, A0=>nx3674, A1=>nx3673); ix3965 : aoi22 port map ( Y=>nx3639, A0=>nx3629, A1=>nx3635, B0=>nx3629, B1=>nx3637); ix3966 : nor02 port map ( Y=>nx3640, A0=>nx3674, A1=>PRI_IN_1(9)); ix3967 : aoi22 port map ( Y=>nx3641, A0=>nx3629, A1=>nx3638, B0=>nx3629, B1=>nx3640); ix3968 : aoi22 port map ( Y=>nx3642, A0=>nx3632, A1=>nx3628, B0=>nx3633, B1=>nx3628); ix3969 : nand03 port map ( Y=>nx3643, A0=>nx3639, A1=>nx3641, A2=>nx3642 ); ix3970 : aoi221 port map ( Y=>nx3644, A0=>nx3651, A1=>nx3637, B0=>nx3651, B1=>nx3638, C0=>nx3643); ix3971 : nand02 port map ( Y=>nx3645, A0=>nx3636, A1=>nx3644); nx1988_EXMPLR : inv02 port map ( Y=>nx1988, A=>nx3651); ix3972 : inv02 port map ( Y=>nx3646, A=>nx3651); ix3973 : nor02 port map ( Y=>nx3647, A0=>nx3568, A1=>nx3569); ix3974 : aoi22 port map ( Y=>nx3648, A0=>PRI_IN_1(6), A1=>nx3667, B0=> nx3620, B1=>nx3621); ix3975 : oai32 port map ( Y=>nx3649, A0=>nx3648, A1=>nx3568, A2=>nx3569, B0=>nx3570, B1=>nx3568); nx2295_EXMPLR : ao21 port map ( Y=>nx2295, A0=>nx2081, A1=>nx3647, B0=> nx3649); nx1526_EXMPLR : nor02 port map ( Y=>nx1526, A0=>nx3622, A1=>nx2081); nx2084_EXMPLR : oai22 port map ( Y=>nx2084, A0=>nx3620, A1=>nx3621, B0=> PRI_IN_1(6), B1=>nx3667); ix3976 : buf04 port map ( Y=>nx3650, A=>nx3627); ix3977 : buf04 port map ( Y=>nx3651, A=>nx3627); ix3978 : inv01 port map ( Y=>nx3652, A=>nx3466); ix3979 : inv01 port map ( Y=>nx3653, A=>nx3467); ix3980 : nor02 port map ( Y=>nx3654, A0=>nx3466, A1=>nx3467); ix3981 : and02 port map ( Y=>nx3655, A0=>nx3652, A1=>nx3653); ix3982 : inv01 port map ( Y=>nx3656, A=>nx3562); ix3983 : oai32 port map ( Y=>nx3657, A0=>nx3655, A1=>nx3656, A2=>nx3465, B0=>nx3464, B1=>nx2205); ix3984 : aoi21 port map ( Y=>nx3658, A0=>nx3652, A1=>nx3653, B0=>nx3465); ix3985 : buf16 port map ( Y=>nx3659, A=>reg_2_q_c_0); ix3986 : buf16 port map ( Y=>nx3660, A=>reg_2_q_c_0); ix3987 : buf16 port map ( Y=>PRI_OUT_0_0_EXMPLR, A=>PRI_OUT_0_dup0_0); ix3988 : buf16 port map ( Y=>nx3661, A=>PRI_OUT_0_dup0_0); ix3989 : buf16 port map ( Y=>nx3662, A=>reg_2_q_c_1); ix3990 : buf16 port map ( Y=>nx3663, A=>reg_2_q_c_1); ix3991 : buf16 port map ( Y=>PRI_OUT_0_1_EXMPLR, A=>PRI_OUT_0_dup0_1); ix3992 : buf16 port map ( Y=>nx3664, A=>PRI_OUT_0_dup0_1); ix3993 : buf16 port map ( Y=>PRI_OUT_0_2_EXMPLR, A=>PRI_OUT_0_dup0_2); ix3994 : buf16 port map ( Y=>nx3665, A=>PRI_OUT_0_dup0_2); ix3995 : buf16 port map ( Y=>PRI_OUT_0_4_EXMPLR, A=>PRI_OUT_0_dup0_4); ix3996 : buf16 port map ( Y=>nx3666, A=>PRI_OUT_0_dup0_4); ix3997 : buf16 port map ( Y=>PRI_OUT_0_6_EXMPLR, A=>PRI_OUT_0_dup0_6); ix3998 : buf16 port map ( Y=>nx3667, A=>PRI_OUT_0_dup0_6); ix3999 : buf16 port map ( Y=>PRI_OUT_0_7_EXMPLR, A=>PRI_OUT_0_dup0_7); ix4000 : buf16 port map ( Y=>nx3668, A=>PRI_OUT_0_dup0_7); ix4001 : buf16 port map ( Y=>PRI_OUT_3_7_EXMPLR, A=>PRI_OUT_3_dup0_7); ix4002 : buf16 port map ( Y=>nx3669, A=>PRI_OUT_3_dup0_7); ix4003 : buf16 port map ( Y=>PRI_OUT_0_8_EXMPLR, A=>PRI_OUT_0_dup0_8); ix4004 : buf16 port map ( Y=>nx3670, A=>PRI_OUT_0_dup0_8); ix4005 : buf16 port map ( Y=>nx3671, A=>nx2319); ix4006 : buf16 port map ( Y=>nx3672, A=>nx2319); ix4007 : buf16 port map ( Y=>PRI_OUT_0_9_EXMPLR, A=>PRI_OUT_0_dup0_9); ix4008 : buf16 port map ( Y=>nx3673, A=>PRI_OUT_0_dup0_9); ix4009 : buf16 port map ( Y=>PRI_OUT_0_10_EXMPLR, A=>PRI_OUT_0_dup0_10); ix4010 : buf16 port map ( Y=>nx3674, A=>PRI_OUT_0_dup0_10); ix4011 : buf16 port map ( Y=>nx3675, A=>nx2536); ix4012 : buf16 port map ( Y=>nx3676, A=>nx2536); ix4013 : buf16 port map ( Y=>nx3677, A=>nx2747); ix4014 : buf16 port map ( Y=>nx3678, A=>nx2747); ix4015 : buf16 port map ( Y=>PRI_OUT_0_13_EXMPLR, A=>PRI_OUT_0_dup0_13); ix4016 : buf16 port map ( Y=>nx3679, A=>PRI_OUT_0_dup0_13); ix4017 : buf16 port map ( Y=>PRI_OUT_0_14_EXMPLR, A=>PRI_OUT_0_dup0_14); ix4018 : buf16 port map ( Y=>nx3680, A=>PRI_OUT_0_dup0_14); end CIRCUIT_arch ;